1
2#include <linux/clk-provider.h>
3#include <linux/mfd/syscon.h>
4#include <linux/slab.h>
5
6#include <dt-bindings/clock/at91.h>
7
8#include "pmc.h"
9
10static DEFINE_SPINLOCK(at91sam9n12_mck_lock);
11
12static const struct clk_master_characteristics mck_characteristics = {
13 .output = { .min = 0, .max = 133333333 },
14 .divisors = { 1, 2, 4, 3 },
15 .have_div3_pres = 1,
16};
17
18static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
19
20static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
21
22static const struct clk_range plla_outputs[] = {
23 { .min = 745000000, .max = 800000000 },
24 { .min = 695000000, .max = 750000000 },
25 { .min = 645000000, .max = 700000000 },
26 { .min = 595000000, .max = 650000000 },
27 { .min = 545000000, .max = 600000000 },
28 { .min = 495000000, .max = 555000000 },
29 { .min = 445000000, .max = 500000000 },
30 { .min = 400000000, .max = 450000000 },
31};
32
33static const struct clk_pll_characteristics plla_characteristics = {
34 .input = { .min = 2000000, .max = 32000000 },
35 .num_output = ARRAY_SIZE(plla_outputs),
36 .output = plla_outputs,
37 .icpll = plla_icpll,
38 .out = plla_out,
39};
40
41static u8 pllb_out[] = { 0 };
42
43static const struct clk_range pllb_outputs[] = {
44 { .min = 30000000, .max = 100000000 },
45};
46
47static const struct clk_pll_characteristics pllb_characteristics = {
48 .input = { .min = 2000000, .max = 32000000 },
49 .num_output = ARRAY_SIZE(pllb_outputs),
50 .output = pllb_outputs,
51 .out = pllb_out,
52};
53
54static const struct {
55 char *n;
56 char *p;
57 u8 id;
58} at91sam9n12_systemck[] = {
59 { .n = "ddrck", .p = "masterck_div", .id = 2 },
60 { .n = "lcdck", .p = "masterck_div", .id = 3 },
61 { .n = "uhpck", .p = "usbck", .id = 6 },
62 { .n = "udpck", .p = "usbck", .id = 7 },
63 { .n = "pck0", .p = "prog0", .id = 8 },
64 { .n = "pck1", .p = "prog1", .id = 9 },
65};
66
67static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
68 .offset = 0x10c,
69 .cmd = BIT(12),
70 .pid_mask = GENMASK(5, 0),
71 .div_mask = GENMASK(17, 16),
72};
73
74struct pck {
75 char *n;
76 u8 id;
77};
78
79static const struct pck at91sam9n12_periphck[] = {
80 { .n = "pioAB_clk", .id = 2, },
81 { .n = "pioCD_clk", .id = 3, },
82 { .n = "fuse_clk", .id = 4, },
83 { .n = "usart0_clk", .id = 5, },
84 { .n = "usart1_clk", .id = 6, },
85 { .n = "usart2_clk", .id = 7, },
86 { .n = "usart3_clk", .id = 8, },
87 { .n = "twi0_clk", .id = 9, },
88 { .n = "twi1_clk", .id = 10, },
89 { .n = "mci0_clk", .id = 12, },
90 { .n = "spi0_clk", .id = 13, },
91 { .n = "spi1_clk", .id = 14, },
92 { .n = "uart0_clk", .id = 15, },
93 { .n = "uart1_clk", .id = 16, },
94 { .n = "tcb_clk", .id = 17, },
95 { .n = "pwm_clk", .id = 18, },
96 { .n = "adc_clk", .id = 19, },
97 { .n = "dma0_clk", .id = 20, },
98 { .n = "uhphs_clk", .id = 22, },
99 { .n = "udphs_clk", .id = 23, },
100 { .n = "lcdc_clk", .id = 25, },
101 { .n = "sha_clk", .id = 27, },
102 { .n = "ssc0_clk", .id = 28, },
103 { .n = "aes_clk", .id = 29, },
104 { .n = "trng_clk", .id = 30, },
105};
106
107static void __init at91sam9n12_pmc_setup(struct device_node *np)
108{
109 struct clk_range range = CLK_RANGE(0, 0);
110 const char *slck_name, *mainxtal_name;
111 struct pmc_data *at91sam9n12_pmc;
112 const char *parent_names[6];
113 struct regmap *regmap;
114 struct clk_hw *hw;
115 int i;
116 bool bypass;
117
118 i = of_property_match_string(np, "clock-names", "slow_clk");
119 if (i < 0)
120 return;
121
122 slck_name = of_clk_get_parent_name(np, i);
123
124 i = of_property_match_string(np, "clock-names", "main_xtal");
125 if (i < 0)
126 return;
127 mainxtal_name = of_clk_get_parent_name(np, i);
128
129 regmap = device_node_to_regmap(np);
130 if (IS_ERR(regmap))
131 return;
132
133 at91sam9n12_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
134 nck(at91sam9n12_systemck), 31, 0, 2);
135 if (!at91sam9n12_pmc)
136 return;
137
138 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
139 50000000);
140 if (IS_ERR(hw))
141 goto err_free;
142
143 bypass = of_property_read_bool(np, "atmel,osc-bypass");
144
145 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
146 bypass);
147 if (IS_ERR(hw))
148 goto err_free;
149
150 parent_names[0] = "main_rc_osc";
151 parent_names[1] = "main_osc";
152 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
153 if (IS_ERR(hw))
154 goto err_free;
155
156 at91sam9n12_pmc->chws[PMC_MAIN] = hw;
157
158 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
159 &at91rm9200_pll_layout, &plla_characteristics);
160 if (IS_ERR(hw))
161 goto err_free;
162
163 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
164 if (IS_ERR(hw))
165 goto err_free;
166
167 at91sam9n12_pmc->chws[PMC_PLLACK] = hw;
168
169 hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
170 &at91rm9200_pll_layout, &pllb_characteristics);
171 if (IS_ERR(hw))
172 goto err_free;
173
174 at91sam9n12_pmc->chws[PMC_PLLBCK] = hw;
175
176 parent_names[0] = slck_name;
177 parent_names[1] = "mainck";
178 parent_names[2] = "plladivck";
179 parent_names[3] = "pllbck";
180 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
181 parent_names,
182 &at91sam9x5_master_layout,
183 &mck_characteristics,
184 &at91sam9n12_mck_lock,
185 CLK_SET_RATE_GATE, INT_MIN);
186 if (IS_ERR(hw))
187 goto err_free;
188
189 hw = at91_clk_register_master_div(regmap, "masterck_div",
190 "masterck_pres",
191 &at91sam9x5_master_layout,
192 &mck_characteristics,
193 &at91sam9n12_mck_lock,
194 CLK_SET_RATE_GATE);
195 if (IS_ERR(hw))
196 goto err_free;
197
198 at91sam9n12_pmc->chws[PMC_MCK] = hw;
199
200 hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck");
201 if (IS_ERR(hw))
202 goto err_free;
203
204 parent_names[0] = slck_name;
205 parent_names[1] = "mainck";
206 parent_names[2] = "plladivck";
207 parent_names[3] = "pllbck";
208 parent_names[4] = "masterck_div";
209 for (i = 0; i < 2; i++) {
210 char name[6];
211
212 snprintf(name, sizeof(name), "prog%d", i);
213
214 hw = at91_clk_register_programmable(regmap, name,
215 parent_names, 5, i,
216 &at91sam9x5_programmable_layout,
217 NULL);
218 if (IS_ERR(hw))
219 goto err_free;
220
221 at91sam9n12_pmc->pchws[i] = hw;
222 }
223
224 for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) {
225 hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n,
226 at91sam9n12_systemck[i].p,
227 at91sam9n12_systemck[i].id);
228 if (IS_ERR(hw))
229 goto err_free;
230
231 at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw;
232 }
233
234 for (i = 0; i < ARRAY_SIZE(at91sam9n12_periphck); i++) {
235 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
236 &at91sam9n12_pcr_layout,
237 at91sam9n12_periphck[i].n,
238 "masterck_div",
239 at91sam9n12_periphck[i].id,
240 &range, INT_MIN);
241 if (IS_ERR(hw))
242 goto err_free;
243
244 at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw;
245 }
246
247 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc);
248
249 return;
250
251err_free:
252 kfree(at91sam9n12_pmc);
253}
254
255
256
257
258CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup);
259
