1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2017-2018, Intel Corporation 4 * Copyright (C) 2015 Altera Corporation 5 */ 6 7#ifndef _ALTERA_EDAC_H 8#define _ALTERA_EDAC_H 9 10#include <linux/arm-smccc.h> 11#include <linux/edac.h> 12#include <linux/types.h> 13 14/* SDRAM Controller CtrlCfg Register */ 15#define CV_CTLCFG_OFST 0x00 16 17/* SDRAM Controller CtrlCfg Register Bit Masks */ 18#define CV_CTLCFG_ECC_EN 0x400 19#define CV_CTLCFG_ECC_CORR_EN 0x800 20#define CV_CTLCFG_GEN_SB_ERR 0x2000 21#define CV_CTLCFG_GEN_DB_ERR 0x4000 22 23#define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN) 24 25/* SDRAM Controller Address Width Register */ 26#define CV_DRAMADDRW_OFST 0x2C 27 28/* SDRAM Controller Address Widths Field Register */ 29#define DRAMADDRW_COLBIT_MASK 0x001F 30#define DRAMADDRW_COLBIT_SHIFT 0 31#define DRAMADDRW_ROWBIT_MASK 0x03E0 32#define DRAMADDRW_ROWBIT_SHIFT 5 33#define CV_DRAMADDRW_BANKBIT_MASK 0x1C00 34#define CV_DRAMADDRW_BANKBIT_SHIFT 10 35#define CV_DRAMADDRW_CSBIT_MASK 0xE000 36#define CV_DRAMADDRW_CSBIT_SHIFT 13 37 38/* SDRAM Controller Interface Data Width Register */ 39#define CV_DRAMIFWIDTH_OFST 0x30 40 41/* SDRAM Controller Interface Data Width Defines */ 42#define CV_DRAMIFWIDTH_16B_ECC 24 43#define CV_DRAMIFWIDTH_32B_ECC 40 44 45/* SDRAM Controller DRAM Status Register */ 46#define CV_DRAMSTS_OFST 0x38 47 48/* SDRAM Controller DRAM Status Register Bit Masks */ 49#define CV_DRAMSTS_SBEERR 0x04 50#define CV_DRAMSTS_DBEERR 0x08 51#define CV_DRAMSTS_CORR_DROP 0x10 52 53/* SDRAM Controller DRAM IRQ Register */ 54#define CV_DRAMINTR_OFST 0x3C 55 56/* SDRAM Controller DRAM IRQ Register Bit Masks */ 57#define CV_DRAMINTR_INTREN 0x01 58#define CV_DRAMINTR_SBEMASK 0x02 59#define CV_DRAMINTR_DBEMASK 0x04 60#define CV_DRAMINTR_CORRDROPMASK 0x08 61#define CV_DRAMINTR_INTRCLR 0x10 62 63/* SDRAM Controller Single Bit Error Count Register */ 64#define CV_SBECOUNT_OFST 0x40 65 66/* SDRAM Controller Double Bit Error Count Register */ 67#define CV_DBECOUNT_OFST 0x44 68 69/* SDRAM Controller ECC Error Address Register */ 70#define CV_ERRADDR_OFST 0x48 71 72/*-----------------------------------------*/ 73 74/* SDRAM Controller EccCtrl Register */ 75#define A10_ECCCTRL1_OFST 0x00 76 77/* SDRAM Controller EccCtrl Register Bit Masks */ 78#define A10_ECCCTRL1_ECC_EN 0x001 79#define A10_ECCCTRL1_CNT_RST 0x010 80#define A10_ECCCTRL1_AWB_CNT_RST 0x100 81#define A10_ECC_CNT_RESET_MASK (A10_ECCCTRL1_CNT_RST | \ 82 A10_ECCCTRL1_AWB_CNT_RST) 83 84/* SDRAM Controller Address Width Register */ 85#define CV_DRAMADDRW 0xFFC2502C 86#define A10_DRAMADDRW 0xFFCFA0A8 87#define S10_DRAMADDRW 0xF80110E0 88 89/* SDRAM Controller Address Widths Field Register */ 90#define DRAMADDRW_COLBIT_MASK 0x001F 91#define DRAMADDRW_COLBIT_SHIFT 0 92#define DRAMADDRW_ROWBIT_MASK 0x03E0 93#define DRAMADDRW_ROWBIT_SHIFT 5 94#define CV_DRAMADDRW_BANKBIT_MASK 0x1C00 95#define CV_DRAMADDRW_BANKBIT_SHIFT 10 96#define CV_DRAMADDRW_CSBIT_MASK 0xE000 97#define CV_DRAMADDRW_CSBIT_SHIFT 13 98 99#define A10_DRAMADDRW_BANKBIT_MASK 0x3C00 100#define A10_DRAMADDRW_BANKBIT_SHIFT 10 101#define A10_DRAMADDRW_GRPBIT_MASK 0xC000 102#define A10_DRAMADDRW_GRPBIT_SHIFT 14 103#define A10_DRAMADDRW_CSBIT_MASK 0x70000 104#define A10_DRAMADDRW_CSBIT_SHIFT 16 105 106/* SDRAM Controller Interface Data Width Register */ 107#define CV_DRAMIFWIDTH 0xFFC25030 108#define A10_DRAMIFWIDTH 0xFFCFB008 109#define S10_DRAMIFWIDTH 0xF8011008 110 111/* SDRAM Controller Interface Data Width Defines */ 112#define CV_DRAMIFWIDTH_16B_ECC 24 113#define CV_DRAMIFWIDTH_32B_ECC 40 114 115#define A10_DRAMIFWIDTH_16B 0x0 116#define A10_DRAMIFWIDTH_32B 0x1 117#define A10_DRAMIFWIDTH_64B 0x2 118 119/* SDRAM Controller DRAM IRQ Register */ 120#define A10_ERRINTEN_OFST 0x10 121 122/* SDRAM Controller DRAM IRQ Register Bit Masks */ 123#define A10_ERRINTEN_SERRINTEN 0x01 124#define A10_ERRINTEN_DERRINTEN 0x02 125#define A10_ECC_IRQ_EN_MASK (A10_ERRINTEN_SERRINTEN | \ 126 A10_ERRINTEN_DERRINTEN) 127 128/* SDRAM Interrupt Mode Register */ 129#define A10_INTMODE_OFST 0x1C 130#define A10_INTMODE_SB_INT 1 131 132/* SDRAM Controller Error Status Register */ 133#define A10_INTSTAT_OFST 0x20 134 135/* SDRAM Controller Error Status Register Bit Masks */ 136#define A10_INTSTAT_SBEERR 0x01 137#define A10_INTSTAT_DBEERR 0x02 138 139/* SDRAM Controller ECC Error Address Register */ 140#define A10_DERRADDR_OFST 0x2C 141#define A10_SERRADDR_OFST 0x30 142 143/* SDRAM Controller ECC Diagnostic Register */ 144#define A10_DIAGINTTEST_OFST 0x24 145 146#define A10_DIAGINT_TSERRA_MASK 0x0001 147#define A10_DIAGINT_TDERRA_MASK 0x0100 148 149#define A10_SBERR_IRQ 34 150#define A10_DBERR_IRQ 32 151 152/* SDRAM Single Bit Error Count Compare Set Register */ 153#define A10_SERRCNTREG_OFST 0x3C 154 155#define A10_SYMAN_INTMASK_CLR 0xFFD06098 156#define A10_INTMASK_CLR_OFST 0x10 157#define A10_DDR0_IRQ_MASK BIT(17) 158 159struct altr_sdram_prv_data { 160 int ecc_ctrl_offset; 161 int ecc_ctl_en_mask; 162 int ecc_cecnt_offset; 163 int ecc_uecnt_offset; 164 int ecc_stat_offset; 165 int ecc_stat_ce_mask; 166 int ecc_stat_ue_mask; 167 int ecc_saddr_offset; 168 int ecc_daddr_offset; 169 int ecc_irq_en_offset; 170 int ecc_irq_en_mask; 171 int ecc_irq_clr_offset; 172 int ecc_irq_clr_mask; 173 int ecc_cnt_rst_offset; 174 int ecc_cnt_rst_mask; 175 struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr; 176 int ecc_enable_mask; 177 int ce_set_mask; 178 int ue_set_mask; 179 int ce_ue_trgr_offset; 180}; 181 182/* Altera SDRAM Memory Controller data */ 183struct altr_sdram_mc_data { 184 struct regmap *mc_vbase; 185 int sb_irq; 186 int db_irq; 187 const struct altr_sdram_prv_data *data; 188}; 189 190/************************** EDAC Device Defines **************************/ 191/***** General Device Trigger Defines *****/ 192#define ALTR_UE_TRIGGER_CHAR 'U' /* Trigger for UE */ 193#define ALTR_TRIGGER_READ_WRD_CNT 32 /* Line size x 4 */ 194#define ALTR_TRIG_OCRAM_BYTE_SIZE 128 /* Line size x 4 */ 195#define ALTR_TRIG_L2C_BYTE_SIZE 4096 /* Full Page */ 196 197/******* Cyclone5 and Arria5 Defines *******/ 198/* OCRAM ECC Management Group Defines */ 199#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET 0x04 200#define ALTR_OCR_ECC_REG_OFFSET 0x00 201#define ALTR_OCR_ECC_EN BIT(0) 202#define ALTR_OCR_ECC_INJS BIT(1) 203#define ALTR_OCR_ECC_INJD BIT(2) 204#define ALTR_OCR_ECC_SERR BIT(3) 205#define ALTR_OCR_ECC_DERR BIT(4) 206 207/* L2 ECC Management Group Defines */ 208#define ALTR_MAN_GRP_L2_ECC_OFFSET 0x00 209#define ALTR_L2_ECC_REG_OFFSET 0x00 210#define ALTR_L2_ECC_EN BIT(0) 211#define ALTR_L2_ECC_INJS BIT(1) 212#define ALTR_L2_ECC_INJD BIT(2) 213 214/* Arria10 General ECC Block Module Defines */ 215#define ALTR_A10_ECC_CTRL_OFST 0x08 216#define ALTR_A10_ECC_EN BIT(0) 217#define ALTR_A10_ECC_INITA BIT(16) 218#define ALTR_A10_ECC_INITB BIT(24) 219 220#define ALTR_A10_ECC_INITSTAT_OFST 0x0C 221#define ALTR_A10_ECC_INITCOMPLETEA BIT(0) 222#define ALTR_A10_ECC_INITCOMPLETEB BIT(8) 223 224#define ALTR_A10_ECC_ERRINTEN_OFST 0x10 225#define ALTR_A10_ECC_ERRINTENS_OFST 0x14 226#define ALTR_A10_ECC_ERRINTENR_OFST 0x18 227#define ALTR_A10_ECC_SERRINTEN BIT(0) 228 229#define ALTR_A10_ECC_INTMODE_OFST 0x1C 230#define ALTR_A10_ECC_INTMODE BIT(0) 231 232#define ALTR_A10_ECC_INTSTAT_OFST 0x20 233#define ALTR_A10_ECC_SERRPENA BIT(0) 234#define ALTR_A10_ECC_DERRPENA BIT(8) 235#define ALTR_A10_ECC_ERRPENA_MASK (ALTR_A10_ECC_SERRPENA | \ 236 ALTR_A10_ECC_DERRPENA) 237#define ALTR_A10_ECC_SERRPENB BIT(16) 238#define ALTR_A10_ECC_DERRPENB BIT(24) 239#define ALTR_A10_ECC_ERRPENB_MASK (ALTR_A10_ECC_SERRPENB | \ 240 ALTR_A10_ECC_DERRPENB) 241 242#define ALTR_A10_ECC_INTTEST_OFST 0x24 243#define ALTR_A10_ECC_TSERRA BIT(0) 244#define ALTR_A10_ECC_TDERRA BIT(8) 245#define ALTR_A10_ECC_TSERRB BIT(16) 246#define ALTR_A10_ECC_TDERRB BIT(24) 247 248/* ECC Manager Defines */ 249#define A10_SYSMGR_ECC_INTMASK_SET_OFST 0x94 250#define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98 251#define A10_SYSMGR_ECC_INTMASK_OCRAM BIT(1) 252 253#define A10_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9C 254#define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0 255#define A10_SYSMGR_ECC_INTSTAT_L2 BIT(0) 256#define A10_SYSMGR_ECC_INTSTAT_OCRAM BIT(1) 257 258#define A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST 0xA8 259#define A10_SYSGMR_MPU_CLEAR_L2_ECC_SB BIT(15) 260#define A10_SYSGMR_MPU_CLEAR_L2_ECC_MB BIT(31) 261 262/* Arria 10 L2 ECC Management Group Defines */ 263#define ALTR_A10_L2_ECC_CTL_OFST 0x0 264#define ALTR_A10_L2_ECC_EN_CTL BIT(0) 265 266#define ALTR_A10_L2_ECC_STATUS 0xFFD060A4 267#define ALTR_A10_L2_ECC_STAT_OFST 0xA4 268#define ALTR_A10_L2_ECC_SERR_PEND BIT(0) 269#define ALTR_A10_L2_ECC_MERR_PEND BIT(0) 270 271#define ALTR_A10_L2_ECC_CLR_OFST 0x4 272#define ALTR_A10_L2_ECC_SERR_CLR BIT(15) 273#define ALTR_A10_L2_ECC_MERR_CLR BIT(31) 274 275#define ALTR_A10_L2_ECC_INJ_OFST ALTR_A10_L2_ECC_CTL_OFST 276#define ALTR_A10_L2_ECC_CE_INJ_MASK 0x00000101 277#define ALTR_A10_L2_ECC_UE_INJ_MASK 0x00010101 278 279/* Arria 10 OCRAM ECC Management Group Defines */ 280#define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0)) 281 282/* Arria 10 Ethernet ECC Management Group Defines */ 283#define ALTR_A10_COMMON_ECC_EN_CTL BIT(0) 284 285/* Arria 10 SDMMC ECC Management Group Defines */ 286#define ALTR_A10_SDMMC_IRQ_MASK (BIT(16) | BIT(15)) 287 288/* A10 ECC Controller memory initialization timeout */ 289#define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000 290 291/************* Stratix10 Defines **************/ 292#define ALTR_S10_ECC_CTRL_SDRAM_OFST 0x00 293#define ALTR_S10_ECC_EN BIT(0) 294 295#define ALTR_S10_ECC_ERRINTEN_OFST 0x10 296#define ALTR_S10_ECC_ERRINTENS_OFST 0x14 297#define ALTR_S10_ECC_ERRINTENR_OFST 0x18 298#define ALTR_S10_ECC_SERRINTEN BIT(0) 299 300#define ALTR_S10_ECC_INTMODE_OFST 0x1C 301#define ALTR_S10_ECC_INTMODE BIT(0) 302 303#define ALTR_S10_ECC_INTSTAT_OFST 0x20 304#define ALTR_S10_ECC_SERRPENA BIT(0) 305#define ALTR_S10_ECC_DERRPENA BIT(8) 306#define ALTR_S10_ECC_ERRPENA_MASK (ALTR_S10_ECC_SERRPENA | \ 307 ALTR_S10_ECC_DERRPENA) 308 309#define ALTR_S10_ECC_INTTEST_OFST 0x24 310#define ALTR_S10_ECC_TSERRA BIT(0) 311#define ALTR_S10_ECC_TDERRA BIT(8) 312#define ALTR_S10_ECC_TSERRB BIT(16) 313#define ALTR_S10_ECC_TDERRB BIT(24) 314 315#define ALTR_S10_DERR_ADDRA_OFST 0x2C 316 317/* Stratix10 ECC Manager Defines */ 318#define S10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98 319#define S10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0 320 321/* Sticky registers for Uncorrected Errors */ 322#define S10_SYSMGR_UE_VAL_OFST 0x220 323#define S10_SYSMGR_UE_ADDR_OFST 0x224 324 325#define S10_DDR0_IRQ_MASK BIT(16) 326#define S10_DBE_IRQ_MASK 0x3FFFE 327 328/* Define ECC Block Offsets for peripherals */ 329#define ECC_BLK_ADDRESS_OFST 0x40 330#define ECC_BLK_RDATA0_OFST 0x44 331#define ECC_BLK_RDATA1_OFST 0x48 332#define ECC_BLK_RDATA2_OFST 0x4C 333#define ECC_BLK_RDATA3_OFST 0x50 334#define ECC_BLK_WDATA0_OFST 0x54 335#define ECC_BLK_WDATA1_OFST 0x58 336#define ECC_BLK_WDATA2_OFST 0x5C 337#define ECC_BLK_WDATA3_OFST 0x60 338#define ECC_BLK_RECC0_OFST 0x64 339#define ECC_BLK_RECC1_OFST 0x68 340#define ECC_BLK_WECC0_OFST 0x6C 341#define ECC_BLK_WECC1_OFST 0x70 342#define ECC_BLK_DBYTECTRL_OFST 0x74 343#define ECC_BLK_ACCCTRL_OFST 0x78 344#define ECC_BLK_STARTACC_OFST 0x7C 345 346#define ECC_XACT_KICK 0x10000 347#define ECC_WORD_WRITE 0xFF 348#define ECC_WRITE_DOVR 0x101 349#define ECC_WRITE_EDOVR 0x103 350#define ECC_READ_EOVR 0x2 351#define ECC_READ_EDOVR 0x3 352 353struct altr_edac_device_dev; 354 355struct edac_device_prv_data { 356 int (*setup)(struct altr_edac_device_dev *device); 357 int ce_clear_mask; 358 int ue_clear_mask; 359 int irq_status_mask; 360 void * (*alloc_mem)(size_t size, void **other); 361 void (*free_mem)(void *p, size_t size, void *other); 362 int ecc_enable_mask; 363 int ecc_en_ofst; 364 int ce_set_mask; 365 int ue_set_mask; 366 int set_err_ofst; 367 irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id); 368 int trig_alloc_sz; 369 const struct file_operations *inject_fops; 370 bool panic; 371}; 372 373struct altr_edac_device_dev { 374 struct list_head next; 375 void __iomem *base; 376 int sb_irq; 377 int db_irq; 378 const struct edac_device_prv_data *data; 379 struct dentry *debugfs_dir; 380 char *edac_dev_name; 381 struct altr_arria10_edac *edac; 382 struct edac_device_ctl_info *edac_dev; 383 struct device ddev; 384 int edac_idx; 385}; 386 387struct altr_arria10_edac { 388 struct device *dev; 389 struct regmap *ecc_mgr_map; 390 int sb_irq; 391 int db_irq; 392 struct irq_domain *domain; 393 struct irq_chip irq_chip; 394 struct list_head a10_ecc_devices; 395 struct notifier_block panic_notifier; 396}; 397 398#endif /* #ifndef _ALTERA_EDAC_H */ 399