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28#ifndef __AMDGPU_OBJECT_H__
29#define __AMDGPU_OBJECT_H__
30
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33#ifdef CONFIG_MMU_NOTIFIER
34#include <linux/mmu_notifier.h>
35#endif
36
37#define AMDGPU_BO_INVALID_OFFSET LONG_MAX
38#define AMDGPU_BO_MAX_PLACEMENTS 3
39
40#define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
41
42struct amdgpu_bo_param {
43 unsigned long size;
44 int byte_align;
45 u32 bo_ptr_size;
46 u32 domain;
47 u32 preferred_domain;
48 u64 flags;
49 enum ttm_bo_type type;
50 bool no_wait_gpu;
51 struct dma_resv *resv;
52};
53
54
55struct amdgpu_bo_va_mapping {
56 struct amdgpu_bo_va *bo_va;
57 struct list_head list;
58 struct rb_node rb;
59 uint64_t start;
60 uint64_t last;
61 uint64_t __subtree_last;
62 uint64_t offset;
63 uint64_t flags;
64};
65
66
67struct amdgpu_bo_va {
68 struct amdgpu_vm_bo_base base;
69
70
71 unsigned ref_count;
72
73
74 struct dma_fence *last_pt_update;
75
76
77 struct list_head invalids;
78 struct list_head valids;
79
80
81 bool cleared;
82
83 bool is_xgmi;
84};
85
86struct amdgpu_bo {
87
88 u32 preferred_domains;
89 u32 allowed_domains;
90 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
91 struct ttm_placement placement;
92 struct ttm_buffer_object tbo;
93 struct ttm_bo_kmap_obj kmap;
94 u64 flags;
95 unsigned prime_shared_count;
96
97 struct amdgpu_vm_bo_base *vm_bo;
98
99 struct amdgpu_bo *parent;
100 struct amdgpu_bo *shadow;
101
102
103
104#ifdef CONFIG_MMU_NOTIFIER
105 struct mmu_interval_notifier notifier;
106#endif
107
108 struct list_head shadow_list;
109
110 struct kgd_mem *kfd_bo;
111};
112
113struct amdgpu_bo_user {
114 struct amdgpu_bo bo;
115 u64 tiling_flags;
116 u64 metadata_flags;
117 void *metadata;
118 u32 metadata_size;
119
120};
121
122static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
123{
124 return container_of(tbo, struct amdgpu_bo, tbo);
125}
126
127
128
129
130
131
132
133static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
134{
135 switch (mem_type) {
136 case TTM_PL_VRAM:
137 return AMDGPU_GEM_DOMAIN_VRAM;
138 case TTM_PL_TT:
139 return AMDGPU_GEM_DOMAIN_GTT;
140 case TTM_PL_SYSTEM:
141 return AMDGPU_GEM_DOMAIN_CPU;
142 case AMDGPU_PL_GDS:
143 return AMDGPU_GEM_DOMAIN_GDS;
144 case AMDGPU_PL_GWS:
145 return AMDGPU_GEM_DOMAIN_GWS;
146 case AMDGPU_PL_OA:
147 return AMDGPU_GEM_DOMAIN_OA;
148 default:
149 break;
150 }
151 return 0;
152}
153
154
155
156
157
158
159
160
161
162
163static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
164{
165 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
166 int r;
167
168 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
169 if (unlikely(r != 0)) {
170 if (r != -ERESTARTSYS)
171 dev_err(adev->dev, "%p reserve failed\n", bo);
172 return r;
173 }
174 return 0;
175}
176
177static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
178{
179 ttm_bo_unreserve(&bo->tbo);
180}
181
182static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
183{
184 return bo->tbo.base.size;
185}
186
187static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
188{
189 return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE;
190}
191
192static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
193{
194 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
195}
196
197
198
199
200
201
202
203static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
204{
205 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
206}
207
208
209
210
211static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
212{
213 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
214 unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
215 struct drm_mm_node *node = bo->tbo.mem.mm_node;
216 unsigned long pages_left;
217
218 if (bo->tbo.mem.mem_type != TTM_PL_VRAM)
219 return false;
220
221 for (pages_left = bo->tbo.mem.num_pages; pages_left;
222 pages_left -= node->size, node++)
223 if (node->start < fpfn)
224 return true;
225
226 return false;
227}
228
229
230
231
232static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
233{
234 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
235}
236
237
238
239
240
241
242
243static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
244{
245 return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
246}
247
248bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
249void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
250
251int amdgpu_bo_create(struct amdgpu_device *adev,
252 struct amdgpu_bo_param *bp,
253 struct amdgpu_bo **bo_ptr);
254int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
255 unsigned long size, int align,
256 u32 domain, struct amdgpu_bo **bo_ptr,
257 u64 *gpu_addr, void **cpu_addr);
258int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
259 unsigned long size, int align,
260 u32 domain, struct amdgpu_bo **bo_ptr,
261 u64 *gpu_addr, void **cpu_addr);
262int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
263 uint64_t offset, uint64_t size, uint32_t domain,
264 struct amdgpu_bo **bo_ptr, void **cpu_addr);
265int amdgpu_bo_create_user(struct amdgpu_device *adev,
266 struct amdgpu_bo_param *bp,
267 struct amdgpu_bo_user **ubo_ptr);
268void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
269 void **cpu_addr);
270int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
271void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
272void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
273struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
274void amdgpu_bo_unref(struct amdgpu_bo **bo);
275int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
276int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
277 u64 min_offset, u64 max_offset);
278void amdgpu_bo_unpin(struct amdgpu_bo *bo);
279int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
280int amdgpu_bo_init(struct amdgpu_device *adev);
281void amdgpu_bo_fini(struct amdgpu_device *adev);
282int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
283void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
284int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
285 uint32_t metadata_size, uint64_t flags);
286int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
287 size_t buffer_size, uint32_t *metadata_size,
288 uint64_t *flags);
289void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
290 bool evict,
291 struct ttm_resource *new_mem);
292void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
293vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
294void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
295 bool shared);
296int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
297 enum amdgpu_sync_mode sync_mode, void *owner,
298 bool intr);
299int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
300u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
301u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
302int amdgpu_bo_validate(struct amdgpu_bo *bo);
303int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
304 struct dma_fence **fence);
305uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
306 uint32_t domain);
307
308
309
310
311
312static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
313{
314 return sa_bo->manager->gpu_addr + sa_bo->soffset;
315}
316
317static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
318{
319 return sa_bo->manager->cpu_ptr + sa_bo->soffset;
320}
321
322int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
323 struct amdgpu_sa_manager *sa_manager,
324 unsigned size, u32 align, u32 domain);
325void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
326 struct amdgpu_sa_manager *sa_manager);
327int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
328 struct amdgpu_sa_manager *sa_manager);
329int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
330 struct amdgpu_sa_bo **sa_bo,
331 unsigned size, unsigned align);
332void amdgpu_sa_bo_free(struct amdgpu_device *adev,
333 struct amdgpu_sa_bo **sa_bo,
334 struct dma_fence *fence);
335#if defined(CONFIG_DEBUG_FS)
336void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
337 struct seq_file *m);
338u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
339#endif
340void amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
341
342bool amdgpu_bo_support_uswc(u64 bo_flags);
343
344
345#endif
346