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24#ifndef __AMDGPU_VM_H__
25#define __AMDGPU_VM_H__
26
27#include <linux/idr.h>
28#include <linux/kfifo.h>
29#include <linux/rbtree.h>
30#include <drm/gpu_scheduler.h>
31#include <drm/drm_file.h>
32#include <drm/ttm/ttm_bo_driver.h>
33#include <linux/sched/mm.h>
34
35#include "amdgpu_sync.h"
36#include "amdgpu_ring.h"
37#include "amdgpu_ids.h"
38
39struct amdgpu_bo_va;
40struct amdgpu_job;
41struct amdgpu_bo_list_entry;
42
43
44
45
46
47
48#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
49
50
51#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
52
53#define AMDGPU_PTE_VALID (1ULL << 0)
54#define AMDGPU_PTE_SYSTEM (1ULL << 1)
55#define AMDGPU_PTE_SNOOPED (1ULL << 2)
56
57
58#define AMDGPU_PTE_TMZ (1ULL << 3)
59
60
61#define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
62
63#define AMDGPU_PTE_READABLE (1ULL << 5)
64#define AMDGPU_PTE_WRITEABLE (1ULL << 6)
65
66#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
67
68
69#define AMDGPU_PTE_PRT (1ULL << 51)
70
71
72#define AMDGPU_PDE_PTE (1ULL << 54)
73
74#define AMDGPU_PTE_LOG (1ULL << 55)
75
76
77#define AMDGPU_PTE_TF (1ULL << 56)
78
79
80#define AMDGPU_PTE_NOALLOC (1ULL << 58)
81
82
83#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
84
85
86
87#define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57)
88#define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL)
89
90#define AMDGPU_MTYPE_NC 0
91#define AMDGPU_MTYPE_CC 2
92
93#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
94 | AMDGPU_PTE_SNOOPED \
95 | AMDGPU_PTE_EXECUTABLE \
96 | AMDGPU_PTE_READABLE \
97 | AMDGPU_PTE_WRITEABLE \
98 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
99
100
101#define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48)
102#define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL)
103
104
105#define AMDGPU_VM_FAULT_STOP_NEVER 0
106#define AMDGPU_VM_FAULT_STOP_FIRST 1
107#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
108
109
110#define AMDGPU_VM_RESERVED_VRAM (8ULL << 20)
111
112
113#define AMDGPU_MAX_VMHUBS 3
114#define AMDGPU_GFXHUB_0 0
115#define AMDGPU_MMHUB_0 1
116#define AMDGPU_MMHUB_1 2
117
118
119#define AMDGPU_VA_RESERVED_SIZE (2ULL << 20)
120
121
122#define AMDGPU_VM_MAX_RESERVED_VMID 1
123
124#define AMDGPU_VM_CONTEXT_GFX 0
125#define AMDGPU_VM_CONTEXT_COMPUTE 1
126
127
128#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
129#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
130
131
132
133
134enum amdgpu_vm_level {
135 AMDGPU_VM_PDB2,
136 AMDGPU_VM_PDB1,
137 AMDGPU_VM_PDB0,
138 AMDGPU_VM_PTB
139};
140
141
142struct amdgpu_vm_bo_base {
143
144 struct amdgpu_vm *vm;
145 struct amdgpu_bo *bo;
146
147
148 struct amdgpu_vm_bo_base *next;
149
150
151 struct list_head vm_status;
152
153
154 bool moved;
155};
156
157struct amdgpu_vm_pt {
158 struct amdgpu_vm_bo_base base;
159
160
161 struct amdgpu_vm_pt *entries;
162};
163
164
165struct amdgpu_vm_pte_funcs {
166
167 unsigned copy_pte_num_dw;
168
169
170 void (*copy_pte)(struct amdgpu_ib *ib,
171 uint64_t pe, uint64_t src,
172 unsigned count);
173
174
175 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
176 uint64_t value, unsigned count,
177 uint32_t incr);
178
179 void (*set_pte_pde)(struct amdgpu_ib *ib,
180 uint64_t pe,
181 uint64_t addr, unsigned count,
182 uint32_t incr, uint64_t flags);
183};
184
185struct amdgpu_task_info {
186 char process_name[TASK_COMM_LEN];
187 char task_name[TASK_COMM_LEN];
188 pid_t pid;
189 pid_t tgid;
190};
191
192
193
194
195
196
197
198
199struct amdgpu_vm_update_params {
200
201
202
203
204 struct amdgpu_device *adev;
205
206
207
208
209 struct amdgpu_vm *vm;
210
211
212
213
214 bool immediate;
215
216
217
218
219 bool unlocked;
220
221
222
223
224
225
226 dma_addr_t *pages_addr;
227
228
229
230
231 struct amdgpu_job *job;
232
233
234
235
236 unsigned int num_dw_left;
237};
238
239struct amdgpu_vm_update_funcs {
240 int (*map_table)(struct amdgpu_bo *bo);
241 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv,
242 enum amdgpu_sync_mode sync_mode);
243 int (*update)(struct amdgpu_vm_update_params *p,
244 struct amdgpu_bo *bo, uint64_t pe, uint64_t addr,
245 unsigned count, uint32_t incr, uint64_t flags);
246 int (*commit)(struct amdgpu_vm_update_params *p,
247 struct dma_fence **fence);
248};
249
250struct amdgpu_vm {
251
252 struct rb_root_cached va;
253
254
255
256
257 struct mutex eviction_lock;
258 bool evicting;
259 unsigned int saved_flags;
260
261
262 struct list_head evicted;
263
264
265 struct list_head relocated;
266
267
268 struct list_head moved;
269
270
271 struct list_head idle;
272
273
274 struct list_head invalidated;
275 spinlock_t invalidated_lock;
276
277
278 struct list_head freed;
279
280
281 struct list_head done;
282
283
284 struct amdgpu_vm_pt root;
285 struct dma_fence *last_update;
286
287
288 struct drm_sched_entity immediate;
289 struct drm_sched_entity delayed;
290
291
292 struct dma_fence *last_unlocked;
293
294 unsigned int pasid;
295
296 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
297
298
299 bool use_cpu_for_update;
300
301
302 const struct amdgpu_vm_update_funcs *update_funcs;
303
304
305 bool pte_support_ats;
306
307
308 DECLARE_KFIFO(faults, u64, 128);
309
310
311 struct amdkfd_process_info *process_info;
312
313
314 struct list_head vm_list_node;
315
316
317 uint64_t pd_phys_addr;
318
319
320 struct amdgpu_task_info task_info;
321
322
323 struct ttm_lru_bulk_move lru_bulk_move;
324
325 bool bulk_moveable;
326
327 bool is_compute_context;
328};
329
330struct amdgpu_vm_manager {
331
332 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
333 unsigned int first_kfd_vmid;
334 bool concurrent_flush;
335
336
337 u64 fence_context;
338 unsigned seqno[AMDGPU_MAX_RINGS];
339
340 uint64_t max_pfn;
341 uint32_t num_level;
342 uint32_t block_size;
343 uint32_t fragment_size;
344 enum amdgpu_vm_level root_level;
345
346 u64 vram_base_offset;
347
348 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
349 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS];
350 unsigned vm_pte_num_scheds;
351 struct amdgpu_ring *page_fault;
352
353
354 spinlock_t prt_lock;
355 atomic_t num_prt_users;
356
357
358
359
360
361 int vm_update_mode;
362
363
364
365
366 struct idr pasid_idr;
367 spinlock_t pasid_lock;
368};
369
370#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
371#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
372#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
373
374extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
375extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
376
377void amdgpu_vm_manager_init(struct amdgpu_device *adev);
378void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
379
380long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
381int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
382 int vm_context, u32 pasid);
383int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid);
384void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
385void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
386void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
387 struct list_head *validated,
388 struct amdgpu_bo_list_entry *entry);
389bool amdgpu_vm_ready(struct amdgpu_vm *vm);
390int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
391 int (*callback)(void *p, struct amdgpu_bo *bo),
392 void *param);
393int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
394int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm, bool immediate);
396int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
397 struct amdgpu_vm *vm,
398 struct dma_fence **fence);
399int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
400 struct amdgpu_vm *vm);
401int amdgpu_vm_bo_update(struct amdgpu_device *adev,
402 struct amdgpu_bo_va *bo_va,
403 bool clear);
404bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
405void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
406 struct amdgpu_bo *bo, bool evicted);
407uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
408struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
409 struct amdgpu_bo *bo);
410struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
411 struct amdgpu_vm *vm,
412 struct amdgpu_bo *bo);
413int amdgpu_vm_bo_map(struct amdgpu_device *adev,
414 struct amdgpu_bo_va *bo_va,
415 uint64_t addr, uint64_t offset,
416 uint64_t size, uint64_t flags);
417int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
418 struct amdgpu_bo_va *bo_va,
419 uint64_t addr, uint64_t offset,
420 uint64_t size, uint64_t flags);
421int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
422 struct amdgpu_bo_va *bo_va,
423 uint64_t addr);
424int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
425 struct amdgpu_vm *vm,
426 uint64_t saddr, uint64_t size);
427struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
428 uint64_t addr);
429void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
430void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
431 struct amdgpu_bo_va *bo_va);
432void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
433 uint32_t fragment_size_default, unsigned max_level,
434 unsigned max_bits);
435int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
436bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
437 struct amdgpu_job *job);
438void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
439
440void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
441 struct amdgpu_task_info *task_info);
442bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
443 uint64_t addr);
444
445void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
446
447void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
448 struct amdgpu_vm *vm);
449void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
450
451#if defined(CONFIG_DEBUG_FS)
452void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
453#endif
454
455#endif
456