LXR linux/drivers/gpu/drm/amd/amdgpu/gfxhub_v1

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#include "amdgpu.h"
  24#include "gfxhub_v1_0.h"
  25#include "gfxhub_v1_1.h"
  26
  27#include "gc/gc_9_0_offset.h"
  28#include "gc/gc_9_0_sh_mask.h"
  29#include "gc/gc_9_0_default.h"
  30#include "vega10_enum.h"
  31
  32#include "soc15_common.h"
  33
  34static u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
  35{
  36        return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
  37}
  38
  39static void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev,
  40                                         uint32_t vmid,
  41                                         uint64_t page_table_base)
  42{
  43        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
  44
  45        WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  46                            hub->ctx_addr_distance * vmid,
  47                            lower_32_bits(page_table_base));
  48
  49        WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  50                            hub->ctx_addr_distance * vmid,
  51                            upper_32_bits(page_table_base));
  52}
  53
  54static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  55{
  56        uint64_t pt_base;
  57
  58        if (adev->gmc.pdb0_bo)
  59                pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
  60        else
  61                pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  62
  63        gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
  64
  65        /* If use GART for FB translation, vmid0 page table covers both
  66         * vram and system memory (gart)
  67         */
  68        if (adev->gmc.pdb0_bo) {
  69                WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  70                                (u32)(adev->gmc.fb_start >> 12));
  71                WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  72                                (u32)(adev->gmc.fb_start >> 44));
  73
  74                WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  75                                (u32)(adev->gmc.gart_end >> 12));
  76                WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  77                                (u32)(adev->gmc.gart_end >> 44));
  78        } else {
  79                WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  80                                (u32)(adev->gmc.gart_start >> 12));
  81                WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  82                                (u32)(adev->gmc.gart_start >> 44));
  83
  84                WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  85                                (u32)(adev->gmc.gart_end >> 12));
  86                WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  87                                (u32)(adev->gmc.gart_end >> 44));
  88        }
  89}
  90
  91static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  92{
  93        uint64_t value;
  94
  95        /* Program the AGP BAR */
  96        WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
  97        WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
  98        WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
  99
 100        if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
 101                /* Program the system aperture low logical page number. */
 102                WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 103                        min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 104
 105                if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 106                        /*
 107                        * Raven2 has a HW issue that it is unable to use the
 108                        * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
 109                        * So here is the workaround that increase system
 110                        * aperture high address (add 1) to get rid of the VM
 111                        * fault and hardware hang.
 112                        */
 113                        WREG32_SOC15_RLC(GC, 0,
 114                                         mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 115                                         max((adev->gmc.fb_end >> 18) + 0x1,
 116                                             adev->gmc.agp_end >> 18));
 117                else
 118                        WREG32_SOC15_RLC(
 119                                GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 120                                max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 121
 122                /* Set default page address. */
 123                value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
 124                WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 125                             (u32)(value >> 12));
 126                WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 127                             (u32)(value >> 44));
 128
 129                /* Program "protection fault". */
 130                WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 131                             (u32)(adev->dummy_page_addr >> 12));
 132                WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 133                             (u32)((u64)adev->dummy_page_addr >> 44));
 134
 135                WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
 136                               ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 137        }
 138
 139        /* In the case squeezing vram into GART aperture, we don't use
 140         * FB aperture and AGP aperture. Disable them.
 141         */
 142        if (adev->gmc.pdb0_bo) {
 143                WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
 144                WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
 145                WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
 146                WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF);
 147                WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
 148                WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
 149        }
 150}
 151
 152static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 153{
 154        uint32_t tmp;
 155
 156        /* Setup TLB control */
 157        tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 158
 159        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 160        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 161        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 162                            ENABLE_ADVANCED_DRIVER_MODEL, 1);
 163        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 164                            SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 165        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 166        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 167                            MTYPE, MTYPE_UC);/* XXX for emulation. */
 168        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 169
 170        WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 171}
 172
 173static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 174{
 175        uint32_t tmp;
 176
 177        /* Setup L2 cache */
 178        tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
 179        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 180        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 181        /* XXX for emulation, Refer to closed source code.*/
 182        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 183                            0);
 184        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 185        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 186        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 187        WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
 188
 189        tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
 190        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 191        tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 192        WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
 193
 194        tmp = mmVM_L2_CNTL3_DEFAULT;
 195        if (adev->gmc.translate_further) {
 196                tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 197                tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 198                                    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 199        } else {
 200                tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 201                tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 202                                    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 203        }
 204        WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
 205
 206        tmp = mmVM_L2_CNTL4_DEFAULT;
 207        if (adev->gmc.xgmi.connected_to_cpu) {
 208                tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
 209                tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
 210        } else {
 211                tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 212                tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 213        }
 214        WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
 215}
 216
 217static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 218{
 219        uint32_t tmp;
 220
 221        tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
 222        tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 223        tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
 224                        adev->gmc.vmid0_page_table_depth);
 225        tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
 226                        adev->gmc.vmid0_page_table_block_size);
 227        tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 228                            RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 229        WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
 230}
 231
 232static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 233{
 234        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 235                     0XFFFFFFFF);
 236        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 237                     0x0000000F);
 238
 239        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 240                     0);
 241        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 242                     0);
 243
 244        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 245        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 246
 247}
 248
 249static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 250{
 251        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 252        unsigned num_level, block_size;
 253        uint32_t tmp;
 254        int i;
 255
 256        num_level = adev->vm_manager.num_level;
 257        block_size = adev->vm_manager.block_size;
 258        if (adev->gmc.translate_further)
 259                num_level -= 1;
 260        else
 261                block_size -= 9;
 262
 263        for (i = 0; i <= 14; i++) {
 264                tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
 265                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 266                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 267                                    num_level);
 268                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 269                                    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 270                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 271                                    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 272                                    1);
 273                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 274                                    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 275                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 276                                    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 277                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 278                                    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 279                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 280                                    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 281                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 282                                    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 283                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 284                                    PAGE_TABLE_BLOCK_SIZE,
 285                                    block_size);
 286                /* Send no-retry XNACK on fault to suppress VM fault storm. */
 287                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 288                                    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 289                                    !adev->gmc.noretry);
 290                WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL,
 291                                    i * hub->ctx_distance, tmp);
 292                WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 293                                    i * hub->ctx_addr_distance, 0);
 294                WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 295                                    i * hub->ctx_addr_distance, 0);
 296                WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 297                                    i * hub->ctx_addr_distance,
 298                                    lower_32_bits(adev->vm_manager.max_pfn - 1));
 299                WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 300                                    i * hub->ctx_addr_distance,
 301                                    upper_32_bits(adev->vm_manager.max_pfn - 1));
 302        }
 303}
 304
 305static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 306{
 307        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 308        unsigned i;
 309
 310        for (i = 0 ; i < 18; ++i) {
 311                WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 312                                    i * hub->eng_addr_distance, 0xffffffff);
 313                WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 314                                    i * hub->eng_addr_distance, 0x1f);
 315        }
 316}
 317
 318static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 319{
 320        if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) {
 321                /*
 322                 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 323                 * VF copy registers so vbios post doesn't program them, for
 324                 * SRIOV driver need to program them
 325                 */
 326                WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
 327                             adev->gmc.vram_start >> 24);
 328                WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
 329                             adev->gmc.vram_end >> 24);
 330        }
 331
 332        /* GART Enable. */
 333        gfxhub_v1_0_init_gart_aperture_regs(adev);
 334        gfxhub_v1_0_init_system_aperture_regs(adev);
 335        gfxhub_v1_0_init_tlb_regs(adev);
 336        if (!amdgpu_sriov_vf(adev))
 337                gfxhub_v1_0_init_cache_regs(adev);
 338
 339        gfxhub_v1_0_enable_system_domain(adev);
 340        if (!amdgpu_sriov_vf(adev))
 341                gfxhub_v1_0_disable_identity_aperture(adev);
 342        gfxhub_v1_0_setup_vmid_config(adev);
 343        gfxhub_v1_0_program_invalidation(adev);
 344
 345        return 0;
 346}
 347
 348static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
 349{
 350        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 351        u32 tmp;
 352        u32 i;
 353
 354        /* Disable all tables */
 355        for (i = 0; i < 16; i++)
 356                WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
 357                                    i * hub->ctx_distance, 0);
 358
 359        /* Setup TLB control */
 360        tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 361        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 362        tmp = REG_SET_FIELD(tmp,
 363                                MC_VM_MX_L1_TLB_CNTL,
 364                                ENABLE_ADVANCED_DRIVER_MODEL,
 365                                0);
 366        WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 367
 368        /* Setup L2 cache */
 369        WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 370        WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
 371}
 372
 373/**
 374 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 375 *
 376 * @adev: amdgpu_device pointer
 377 * @value: true redirects VM faults to the default page
 378 */
 379static void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 380                                                 bool value)
 381{
 382        u32 tmp;
 383        tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 384        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 385                        RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 386        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 387                        PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 388        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 389                        PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 390        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 391                        PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 392        tmp = REG_SET_FIELD(tmp,
 393                        VM_L2_PROTECTION_FAULT_CNTL,
 394                        TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 395                        value);
 396        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 397                        NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 398        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 399                        DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 400        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 401                        VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 402        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 403                        READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 404        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 405                        WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 406        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 407                        EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 408        if (!value) {
 409                tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 410                                CRASH_ON_NO_RETRY_FAULT, 1);
 411                tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 412                                CRASH_ON_RETRY_FAULT, 1);
 413        }
 414        WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 415}
 416
 417static void gfxhub_v1_0_init(struct amdgpu_device *adev)
 418{
 419        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 420
 421        hub->ctx0_ptb_addr_lo32 =
 422                SOC15_REG_OFFSET(GC, 0,
 423                                 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 424        hub->ctx0_ptb_addr_hi32 =
 425                SOC15_REG_OFFSET(GC, 0,
 426                                 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 427        hub->vm_inv_eng0_sem =
 428                SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
 429        hub->vm_inv_eng0_req =
 430                SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
 431        hub->vm_inv_eng0_ack =
 432                SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
 433        hub->vm_context0_cntl =
 434                SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
 435        hub->vm_l2_pro_fault_status =
 436                SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 437        hub->vm_l2_pro_fault_cntl =
 438                SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 439
 440        hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL;
 441        hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 442                mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 443        hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ;
 444        hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 445                mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 446}
 447
 448
 449const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = {
 450        .get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset,
 451        .setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs,
 452        .gart_enable = gfxhub_v1_0_gart_enable,
 453        .gart_disable = gfxhub_v1_0_gart_disable,
 454        .set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,
 455        .init = gfxhub_v1_0_init,
 456        .get_xgmi_info = gfxhub_v1_1_get_xgmi_info,
 457};
 458