LXR linux/drivers/gpu/drm/amd/amdgpu/hdp_v4

   1/*
   2 * Copyright 2020 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#include "amdgpu.h"
  24#include "amdgpu_atombios.h"
  25#include "hdp_v4_0.h"
  26#include "amdgpu_ras.h"
  27
  28#include "hdp/hdp_4_0_offset.h"
  29#include "hdp/hdp_4_0_sh_mask.h"
  30#include <uapi/linux/kfd_ioctl.h>
  31
  32/* for Vega20 register name change */
  33#define mmHDP_MEM_POWER_CTRL    0x00d4
  34#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  35#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  36#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  37#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK     0x00020000L
  38#define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  39
  40static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
  41                                struct amdgpu_ring *ring)
  42{
  43        if (!ring || !ring->funcs->emit_wreg)
  44                WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  45        else
  46                amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  47}
  48
  49static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
  50                                    struct amdgpu_ring *ring)
  51{
  52        if (adev->asic_type == CHIP_ALDEBARAN)
  53                return;
  54
  55        if (!ring || !ring->funcs->emit_wreg)
  56                WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
  57        else
  58                amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
  59                        HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
  60}
  61
  62static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
  63{
  64        if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
  65                return;
  66        /*read back hdp ras counter to reset it to 0 */
  67        RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
  68}
  69
  70static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
  71                                         bool enable)
  72{
  73        uint32_t def, data;
  74
  75        if (adev->asic_type == CHIP_VEGA10 ||
  76            adev->asic_type == CHIP_VEGA12 ||
  77            adev->asic_type == CHIP_RAVEN) {
  78                def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
  79
  80                if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
  81                        data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
  82                else
  83                        data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
  84
  85                if (def != data)
  86                        WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
  87        } else {
  88                def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
  89
  90                if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
  91                        data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
  92                                HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
  93                                HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
  94                                HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
  95                else
  96                        data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
  97                                  HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
  98                                  HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
  99                                  HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
 100
 101                if (def != data)
 102                        WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
 103        }
 104}
 105
 106static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
 107                                            u32 *flags)
 108{
 109        int data;
 110
 111        /* AMD_CG_SUPPORT_HDP_LS */
 112        data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 113        if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
 114                *flags |= AMD_CG_SUPPORT_HDP_LS;
 115}
 116
 117static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
 118{
 119        switch (adev->asic_type) {
 120        case CHIP_ARCTURUS:
 121                WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
 122                break;
 123        default:
 124                break;
 125        }
 126
 127        WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
 128
 129        WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
 130        WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
 131}
 132
 133const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
 134        .flush_hdp = hdp_v4_0_flush_hdp,
 135        .invalidate_hdp = hdp_v4_0_invalidate_hdp,
 136        .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
 137        .update_clock_gating = hdp_v4_0_update_clock_gating,
 138        .get_clock_gating_state = hdp_v4_0_get_clockgating_state,
 139        .init_registers = hdp_v4_0_init_registers,
 140};
 141