LXR linux/drivers/gpu/drm/amd/amdgpu/uvd_v5

   1/*
   2 * Copyright 2014 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Christian König <christian.koenig@amd.com>
  23 */
  24
  25#include <linux/delay.h>
  26#include <linux/firmware.h>
  27
  28#include "amdgpu.h"
  29#include "amdgpu_uvd.h"
  30#include "vid.h"
  31#include "uvd/uvd_5_0_d.h"
  32#include "uvd/uvd_5_0_sh_mask.h"
  33#include "oss/oss_2_0_d.h"
  34#include "oss/oss_2_0_sh_mask.h"
  35#include "bif/bif_5_0_d.h"
  36#include "vi.h"
  37#include "smu/smu_7_1_2_d.h"
  38#include "smu/smu_7_1_2_sh_mask.h"
  39#include "ivsrcid/ivsrcid_vislands30.h"
  40
  41static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  42static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  43static int uvd_v5_0_start(struct amdgpu_device *adev);
  44static void uvd_v5_0_stop(struct amdgpu_device *adev);
  45static int uvd_v5_0_set_clockgating_state(void *handle,
  46                                          enum amd_clockgating_state state);
  47static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
  48                                 bool enable);
  49/**
  50 * uvd_v5_0_ring_get_rptr - get read pointer
  51 *
  52 * @ring: amdgpu_ring pointer
  53 *
  54 * Returns the current hardware read pointer
  55 */
  56static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
  57{
  58        struct amdgpu_device *adev = ring->adev;
  59
  60        return RREG32(mmUVD_RBC_RB_RPTR);
  61}
  62
  63/**
  64 * uvd_v5_0_ring_get_wptr - get write pointer
  65 *
  66 * @ring: amdgpu_ring pointer
  67 *
  68 * Returns the current hardware write pointer
  69 */
  70static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
  71{
  72        struct amdgpu_device *adev = ring->adev;
  73
  74        return RREG32(mmUVD_RBC_RB_WPTR);
  75}
  76
  77/**
  78 * uvd_v5_0_ring_set_wptr - set write pointer
  79 *
  80 * @ring: amdgpu_ring pointer
  81 *
  82 * Commits the write pointer to the hardware
  83 */
  84static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
  85{
  86        struct amdgpu_device *adev = ring->adev;
  87
  88        WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
  89}
  90
  91static int uvd_v5_0_early_init(void *handle)
  92{
  93        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  94        adev->uvd.num_uvd_inst = 1;
  95
  96        uvd_v5_0_set_ring_funcs(adev);
  97        uvd_v5_0_set_irq_funcs(adev);
  98
  99        return 0;
 100}
 101
 102static int uvd_v5_0_sw_init(void *handle)
 103{
 104        struct amdgpu_ring *ring;
 105        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 106        int r;
 107
 108        /* UVD TRAP */
 109        r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
 110        if (r)
 111                return r;
 112
 113        r = amdgpu_uvd_sw_init(adev);
 114        if (r)
 115                return r;
 116
 117        ring = &adev->uvd.inst->ring;
 118        sprintf(ring->name, "uvd");
 119        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
 120                             AMDGPU_RING_PRIO_DEFAULT, NULL);
 121        if (r)
 122                return r;
 123
 124        r = amdgpu_uvd_resume(adev);
 125        if (r)
 126                return r;
 127
 128        r = amdgpu_uvd_entity_init(adev);
 129
 130        return r;
 131}
 132
 133static int uvd_v5_0_sw_fini(void *handle)
 134{
 135        int r;
 136        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 137
 138        r = amdgpu_uvd_suspend(adev);
 139        if (r)
 140                return r;
 141
 142        return amdgpu_uvd_sw_fini(adev);
 143}
 144
 145/**
 146 * uvd_v5_0_hw_init - start and test UVD block
 147 *
 148 * @handle: handle used to pass amdgpu_device pointer
 149 *
 150 * Initialize the hardware, boot up the VCPU and do some testing
 151 */
 152static int uvd_v5_0_hw_init(void *handle)
 153{
 154        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 155        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 156        uint32_t tmp;
 157        int r;
 158
 159        amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 160        uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
 161        uvd_v5_0_enable_mgcg(adev, true);
 162
 163        r = amdgpu_ring_test_helper(ring);
 164        if (r)
 165                goto done;
 166
 167        r = amdgpu_ring_alloc(ring, 10);
 168        if (r) {
 169                DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 170                goto done;
 171        }
 172
 173        tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 174        amdgpu_ring_write(ring, tmp);
 175        amdgpu_ring_write(ring, 0xFFFFF);
 176
 177        tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 178        amdgpu_ring_write(ring, tmp);
 179        amdgpu_ring_write(ring, 0xFFFFF);
 180
 181        tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 182        amdgpu_ring_write(ring, tmp);
 183        amdgpu_ring_write(ring, 0xFFFFF);
 184
 185        /* Clear timeout status bits */
 186        amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 187        amdgpu_ring_write(ring, 0x8);
 188
 189        amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 190        amdgpu_ring_write(ring, 3);
 191
 192        amdgpu_ring_commit(ring);
 193
 194done:
 195        if (!r)
 196                DRM_INFO("UVD initialized successfully.\n");
 197
 198        return r;
 199
 200}
 201
 202/**
 203 * uvd_v5_0_hw_fini - stop the hardware block
 204 *
 205 * @handle: handle used to pass amdgpu_device pointer
 206 *
 207 * Stop the UVD block, mark ring as not ready any more
 208 */
 209static int uvd_v5_0_hw_fini(void *handle)
 210{
 211        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 212
 213        if (RREG32(mmUVD_STATUS) != 0)
 214                uvd_v5_0_stop(adev);
 215
 216        return 0;
 217}
 218
 219static int uvd_v5_0_suspend(void *handle)
 220{
 221        int r;
 222        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 223
 224        r = uvd_v5_0_hw_fini(adev);
 225        if (r)
 226                return r;
 227        uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
 228
 229        return amdgpu_uvd_suspend(adev);
 230}
 231
 232static int uvd_v5_0_resume(void *handle)
 233{
 234        int r;
 235        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 236
 237        r = amdgpu_uvd_resume(adev);
 238        if (r)
 239                return r;
 240
 241        return uvd_v5_0_hw_init(adev);
 242}
 243
 244/**
 245 * uvd_v5_0_mc_resume - memory controller programming
 246 *
 247 * @adev: amdgpu_device pointer
 248 *
 249 * Let the UVD memory controller know it's offsets
 250 */
 251static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
 252{
 253        uint64_t offset;
 254        uint32_t size;
 255
 256        /* program memory controller bits 0-27 */
 257        WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 258                        lower_32_bits(adev->uvd.inst->gpu_addr));
 259        WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 260                        upper_32_bits(adev->uvd.inst->gpu_addr));
 261
 262        offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 263        size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 264        WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 265        WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 266
 267        offset += size;
 268        size = AMDGPU_UVD_HEAP_SIZE;
 269        WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 270        WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 271
 272        offset += size;
 273        size = AMDGPU_UVD_STACK_SIZE +
 274               (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 275        WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 276        WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 277
 278        WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 279        WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 280        WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 281}
 282
 283/**
 284 * uvd_v5_0_start - start UVD block
 285 *
 286 * @adev: amdgpu_device pointer
 287 *
 288 * Setup and start the UVD block
 289 */
 290static int uvd_v5_0_start(struct amdgpu_device *adev)
 291{
 292        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 293        uint32_t rb_bufsz, tmp;
 294        uint32_t lmi_swap_cntl;
 295        uint32_t mp_swap_cntl;
 296        int i, j, r;
 297
 298        /*disable DPG */
 299        WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
 300
 301        /* disable byte swapping */
 302        lmi_swap_cntl = 0;
 303        mp_swap_cntl = 0;
 304
 305        uvd_v5_0_mc_resume(adev);
 306
 307        /* disable interupt */
 308        WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
 309
 310        /* stall UMC and register bus before resetting VCPU */
 311        WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 312        mdelay(1);
 313
 314        /* put LMI, VCPU, RBC etc... into reset */
 315        WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 316                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 317                UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 318                UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 319                UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 320        mdelay(5);
 321
 322        /* take UVD block out of reset */
 323        WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 324        mdelay(5);
 325
 326        /* initialize UVD memory controller */
 327        WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
 328                             (1 << 21) | (1 << 9) | (1 << 20));
 329
 330#ifdef __BIG_ENDIAN
 331        /* swap (8 in 32) RB and IB */
 332        lmi_swap_cntl = 0xa;
 333        mp_swap_cntl = 0;
 334#endif
 335        WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 336        WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 337
 338        WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 339        WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 340        WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 341        WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 342        WREG32(mmUVD_MPC_SET_ALU, 0);
 343        WREG32(mmUVD_MPC_SET_MUX, 0x88);
 344
 345        /* take all subblocks out of reset, except VCPU */
 346        WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 347        mdelay(5);
 348
 349        /* enable VCPU clock */
 350        WREG32(mmUVD_VCPU_CNTL,  1 << 9);
 351
 352        /* enable UMC */
 353        WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 354
 355        /* boot up the VCPU */
 356        WREG32(mmUVD_SOFT_RESET, 0);
 357        mdelay(10);
 358
 359        for (i = 0; i < 10; ++i) {
 360                uint32_t status;
 361                for (j = 0; j < 100; ++j) {
 362                        status = RREG32(mmUVD_STATUS);
 363                        if (status & 2)
 364                                break;
 365                        mdelay(10);
 366                }
 367                r = 0;
 368                if (status & 2)
 369                        break;
 370
 371                DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 372                WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 373                                ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 374                mdelay(10);
 375                WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 376                mdelay(10);
 377                r = -1;
 378        }
 379
 380        if (r) {
 381                DRM_ERROR("UVD not responding, giving up!!!\n");
 382                return r;
 383        }
 384        /* enable master interrupt */
 385        WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
 386
 387        /* clear the bit 4 of UVD_STATUS */
 388        WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
 389
 390        rb_bufsz = order_base_2(ring->ring_size);
 391        tmp = 0;
 392        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 393        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 394        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 395        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 396        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 397        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 398        /* force RBC into idle state */
 399        WREG32(mmUVD_RBC_RB_CNTL, tmp);
 400
 401        /* set the write pointer delay */
 402        WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 403
 404        /* set the wb address */
 405        WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 406
 407        /* program the RB_BASE for ring buffer */
 408        WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 409                        lower_32_bits(ring->gpu_addr));
 410        WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 411                        upper_32_bits(ring->gpu_addr));
 412
 413        /* Initialize the ring buffer's read and write pointers */
 414        WREG32(mmUVD_RBC_RB_RPTR, 0);
 415
 416        ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 417        WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 418
 419        WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 420
 421        return 0;
 422}
 423
 424/**
 425 * uvd_v5_0_stop - stop UVD block
 426 *
 427 * @adev: amdgpu_device pointer
 428 *
 429 * stop the UVD block
 430 */
 431static void uvd_v5_0_stop(struct amdgpu_device *adev)
 432{
 433        /* force RBC into idle state */
 434        WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 435
 436        /* Stall UMC and register bus before resetting VCPU */
 437        WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 438        mdelay(1);
 439
 440        /* put VCPU into reset */
 441        WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 442        mdelay(5);
 443
 444        /* disable VCPU clock */
 445        WREG32(mmUVD_VCPU_CNTL, 0x0);
 446
 447        /* Unstall UMC and register bus */
 448        WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 449
 450        WREG32(mmUVD_STATUS, 0);
 451}
 452
 453/**
 454 * uvd_v5_0_ring_emit_fence - emit an fence & trap command
 455 *
 456 * @ring: amdgpu_ring pointer
 457 * @addr: address
 458 * @seq: sequence number
 459 * @flags: fence related flags
 460 *
 461 * Write a fence and a trap command to the ring.
 462 */
 463static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 464                                     unsigned flags)
 465{
 466        WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 467
 468        amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 469        amdgpu_ring_write(ring, seq);
 470        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 471        amdgpu_ring_write(ring, addr & 0xffffffff);
 472        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 473        amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 474        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 475        amdgpu_ring_write(ring, 0);
 476
 477        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 478        amdgpu_ring_write(ring, 0);
 479        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 480        amdgpu_ring_write(ring, 0);
 481        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 482        amdgpu_ring_write(ring, 2);
 483}
 484
 485/**
 486 * uvd_v5_0_ring_test_ring - register write test
 487 *
 488 * @ring: amdgpu_ring pointer
 489 *
 490 * Test if we can successfully write to the context register
 491 */
 492static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 493{
 494        struct amdgpu_device *adev = ring->adev;
 495        uint32_t tmp = 0;
 496        unsigned i;
 497        int r;
 498
 499        WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 500        r = amdgpu_ring_alloc(ring, 3);
 501        if (r)
 502                return r;
 503        amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 504        amdgpu_ring_write(ring, 0xDEADBEEF);
 505        amdgpu_ring_commit(ring);
 506        for (i = 0; i < adev->usec_timeout; i++) {
 507                tmp = RREG32(mmUVD_CONTEXT_ID);
 508                if (tmp == 0xDEADBEEF)
 509                        break;
 510                udelay(1);
 511        }
 512
 513        if (i >= adev->usec_timeout)
 514                r = -ETIMEDOUT;
 515
 516        return r;
 517}
 518
 519/**
 520 * uvd_v5_0_ring_emit_ib - execute indirect buffer
 521 *
 522 * @ring: amdgpu_ring pointer
 523 * @job: job to retrieve vmid from
 524 * @ib: indirect buffer to execute
 525 * @flags: unused
 526 *
 527 * Write ring commands to execute the indirect buffer
 528 */
 529static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 530                                  struct amdgpu_job *job,
 531                                  struct amdgpu_ib *ib,
 532                                  uint32_t flags)
 533{
 534        amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 535        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 536        amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 537        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 538        amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 539        amdgpu_ring_write(ring, ib->length_dw);
 540}
 541
 542static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 543{
 544        int i;
 545
 546        WARN_ON(ring->wptr % 2 || count % 2);
 547
 548        for (i = 0; i < count / 2; i++) {
 549                amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
 550                amdgpu_ring_write(ring, 0);
 551        }
 552}
 553
 554static bool uvd_v5_0_is_idle(void *handle)
 555{
 556        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 557
 558        return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 559}
 560
 561static int uvd_v5_0_wait_for_idle(void *handle)
 562{
 563        unsigned i;
 564        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 565
 566        for (i = 0; i < adev->usec_timeout; i++) {
 567                if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
 568                        return 0;
 569        }
 570        return -ETIMEDOUT;
 571}
 572
 573static int uvd_v5_0_soft_reset(void *handle)
 574{
 575        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 576
 577        uvd_v5_0_stop(adev);
 578
 579        WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
 580                        ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 581        mdelay(5);
 582
 583        return uvd_v5_0_start(adev);
 584}
 585
 586static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
 587                                        struct amdgpu_irq_src *source,
 588                                        unsigned type,
 589                                        enum amdgpu_interrupt_state state)
 590{
 591        // TODO
 592        return 0;
 593}
 594
 595static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
 596                                      struct amdgpu_irq_src *source,
 597                                      struct amdgpu_iv_entry *entry)
 598{
 599        DRM_DEBUG("IH: UVD TRAP\n");
 600        amdgpu_fence_process(&adev->uvd.inst->ring);
 601        return 0;
 602}
 603
 604static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
 605{
 606        uint32_t data1, data3, suvd_flags;
 607
 608        data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 609        data3 = RREG32(mmUVD_CGC_GATE);
 610
 611        suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 612                     UVD_SUVD_CGC_GATE__SIT_MASK |
 613                     UVD_SUVD_CGC_GATE__SMP_MASK |
 614                     UVD_SUVD_CGC_GATE__SCM_MASK |
 615                     UVD_SUVD_CGC_GATE__SDB_MASK;
 616
 617        if (enable) {
 618                data3 |= (UVD_CGC_GATE__SYS_MASK     |
 619                        UVD_CGC_GATE__UDEC_MASK      |
 620                        UVD_CGC_GATE__MPEG2_MASK     |
 621                        UVD_CGC_GATE__RBC_MASK       |
 622                        UVD_CGC_GATE__LMI_MC_MASK    |
 623                        UVD_CGC_GATE__IDCT_MASK      |
 624                        UVD_CGC_GATE__MPRD_MASK      |
 625                        UVD_CGC_GATE__MPC_MASK       |
 626                        UVD_CGC_GATE__LBSI_MASK      |
 627                        UVD_CGC_GATE__LRBBM_MASK     |
 628                        UVD_CGC_GATE__UDEC_RE_MASK   |
 629                        UVD_CGC_GATE__UDEC_CM_MASK   |
 630                        UVD_CGC_GATE__UDEC_IT_MASK   |
 631                        UVD_CGC_GATE__UDEC_DB_MASK   |
 632                        UVD_CGC_GATE__UDEC_MP_MASK   |
 633                        UVD_CGC_GATE__WCB_MASK       |
 634                        UVD_CGC_GATE__JPEG_MASK      |
 635                        UVD_CGC_GATE__SCPU_MASK);
 636                /* only in pg enabled, we can gate clock to vcpu*/
 637                if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 638                        data3 |= UVD_CGC_GATE__VCPU_MASK;
 639                data3 &= ~UVD_CGC_GATE__REGS_MASK;
 640                data1 |= suvd_flags;
 641        } else {
 642                data3 = 0;
 643                data1 = 0;
 644        }
 645
 646        WREG32(mmUVD_SUVD_CGC_GATE, data1);
 647        WREG32(mmUVD_CGC_GATE, data3);
 648}
 649
 650static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
 651{
 652        uint32_t data, data2;
 653
 654        data = RREG32(mmUVD_CGC_CTRL);
 655        data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
 656
 657
 658        data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
 659                  UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 660
 661
 662        data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 663                (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
 664                (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
 665
 666        data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 667                        UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 668                        UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 669                        UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 670                        UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 671                        UVD_CGC_CTRL__SYS_MODE_MASK |
 672                        UVD_CGC_CTRL__UDEC_MODE_MASK |
 673                        UVD_CGC_CTRL__MPEG2_MODE_MASK |
 674                        UVD_CGC_CTRL__REGS_MODE_MASK |
 675                        UVD_CGC_CTRL__RBC_MODE_MASK |
 676                        UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 677                        UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 678                        UVD_CGC_CTRL__IDCT_MODE_MASK |
 679                        UVD_CGC_CTRL__MPRD_MODE_MASK |
 680                        UVD_CGC_CTRL__MPC_MODE_MASK |
 681                        UVD_CGC_CTRL__LBSI_MODE_MASK |
 682                        UVD_CGC_CTRL__LRBBM_MODE_MASK |
 683                        UVD_CGC_CTRL__WCB_MODE_MASK |
 684                        UVD_CGC_CTRL__VCPU_MODE_MASK |
 685                        UVD_CGC_CTRL__JPEG_MODE_MASK |
 686                        UVD_CGC_CTRL__SCPU_MODE_MASK);
 687        data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
 688                        UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
 689                        UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
 690                        UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
 691                        UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
 692
 693        WREG32(mmUVD_CGC_CTRL, data);
 694        WREG32(mmUVD_SUVD_CGC_CTRL, data2);
 695}
 696
 697#if 0
 698static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
 699{
 700        uint32_t data, data1, cgc_flags, suvd_flags;
 701
 702        data = RREG32(mmUVD_CGC_GATE);
 703        data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 704
 705        cgc_flags = UVD_CGC_GATE__SYS_MASK |
 706                                UVD_CGC_GATE__UDEC_MASK |
 707                                UVD_CGC_GATE__MPEG2_MASK |
 708                                UVD_CGC_GATE__RBC_MASK |
 709                                UVD_CGC_GATE__LMI_MC_MASK |
 710                                UVD_CGC_GATE__IDCT_MASK |
 711                                UVD_CGC_GATE__MPRD_MASK |
 712                                UVD_CGC_GATE__MPC_MASK |
 713                                UVD_CGC_GATE__LBSI_MASK |
 714                                UVD_CGC_GATE__LRBBM_MASK |
 715                                UVD_CGC_GATE__UDEC_RE_MASK |
 716                                UVD_CGC_GATE__UDEC_CM_MASK |
 717                                UVD_CGC_GATE__UDEC_IT_MASK |
 718                                UVD_CGC_GATE__UDEC_DB_MASK |
 719                                UVD_CGC_GATE__UDEC_MP_MASK |
 720                                UVD_CGC_GATE__WCB_MASK |
 721                                UVD_CGC_GATE__VCPU_MASK |
 722                                UVD_CGC_GATE__SCPU_MASK;
 723
 724        suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 725                                UVD_SUVD_CGC_GATE__SIT_MASK |
 726                                UVD_SUVD_CGC_GATE__SMP_MASK |
 727                                UVD_SUVD_CGC_GATE__SCM_MASK |
 728                                UVD_SUVD_CGC_GATE__SDB_MASK;
 729
 730        data |= cgc_flags;
 731        data1 |= suvd_flags;
 732
 733        WREG32(mmUVD_CGC_GATE, data);
 734        WREG32(mmUVD_SUVD_CGC_GATE, data1);
 735}
 736#endif
 737
 738static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
 739                                 bool enable)
 740{
 741        u32 orig, data;
 742
 743        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
 744                data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 745                data |= 0xfff;
 746                WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 747
 748                orig = data = RREG32(mmUVD_CGC_CTRL);
 749                data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 750                if (orig != data)
 751                        WREG32(mmUVD_CGC_CTRL, data);
 752        } else {
 753                data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 754                data &= ~0xfff;
 755                WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 756
 757                orig = data = RREG32(mmUVD_CGC_CTRL);
 758                data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 759                if (orig != data)
 760                        WREG32(mmUVD_CGC_CTRL, data);
 761        }
 762}
 763
 764static int uvd_v5_0_set_clockgating_state(void *handle,
 765                                          enum amd_clockgating_state state)
 766{
 767        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 768        bool enable = (state == AMD_CG_STATE_GATE);
 769
 770        if (enable) {
 771                /* wait for STATUS to clear */
 772                if (uvd_v5_0_wait_for_idle(handle))
 773                        return -EBUSY;
 774                uvd_v5_0_enable_clock_gating(adev, true);
 775
 776                /* enable HW gates because UVD is idle */
 777/*              uvd_v5_0_set_hw_clock_gating(adev); */
 778        } else {
 779                uvd_v5_0_enable_clock_gating(adev, false);
 780        }
 781
 782        uvd_v5_0_set_sw_clock_gating(adev);
 783        return 0;
 784}
 785
 786static int uvd_v5_0_set_powergating_state(void *handle,
 787                                          enum amd_powergating_state state)
 788{
 789        /* This doesn't actually powergate the UVD block.
 790         * That's done in the dpm code via the SMC.  This
 791         * just re-inits the block as necessary.  The actual
 792         * gating still happens in the dpm code.  We should
 793         * revisit this when there is a cleaner line between
 794         * the smc and the hw blocks
 795         */
 796        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 797        int ret = 0;
 798
 799        if (state == AMD_PG_STATE_GATE) {
 800                uvd_v5_0_stop(adev);
 801        } else {
 802                ret = uvd_v5_0_start(adev);
 803                if (ret)
 804                        goto out;
 805        }
 806
 807out:
 808        return ret;
 809}
 810
 811static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
 812{
 813        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 814        int data;
 815
 816        mutex_lock(&adev->pm.mutex);
 817
 818        if (RREG32_SMC(ixCURRENT_PG_STATUS) &
 819                                CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
 820                DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
 821                goto out;
 822        }
 823
 824        /* AMD_CG_SUPPORT_UVD_MGCG */
 825        data = RREG32(mmUVD_CGC_CTRL);
 826        if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
 827                *flags |= AMD_CG_SUPPORT_UVD_MGCG;
 828
 829out:
 830        mutex_unlock(&adev->pm.mutex);
 831}
 832
 833static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
 834        .name = "uvd_v5_0",
 835        .early_init = uvd_v5_0_early_init,
 836        .late_init = NULL,
 837        .sw_init = uvd_v5_0_sw_init,
 838        .sw_fini = uvd_v5_0_sw_fini,
 839        .hw_init = uvd_v5_0_hw_init,
 840        .hw_fini = uvd_v5_0_hw_fini,
 841        .suspend = uvd_v5_0_suspend,
 842        .resume = uvd_v5_0_resume,
 843        .is_idle = uvd_v5_0_is_idle,
 844        .wait_for_idle = uvd_v5_0_wait_for_idle,
 845        .soft_reset = uvd_v5_0_soft_reset,
 846        .set_clockgating_state = uvd_v5_0_set_clockgating_state,
 847        .set_powergating_state = uvd_v5_0_set_powergating_state,
 848        .get_clockgating_state = uvd_v5_0_get_clockgating_state,
 849};
 850
 851static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
 852        .type = AMDGPU_RING_TYPE_UVD,
 853        .align_mask = 0xf,
 854        .support_64bit_ptrs = false,
 855        .no_user_fence = true,
 856        .get_rptr = uvd_v5_0_ring_get_rptr,
 857        .get_wptr = uvd_v5_0_ring_get_wptr,
 858        .set_wptr = uvd_v5_0_ring_set_wptr,
 859        .parse_cs = amdgpu_uvd_ring_parse_cs,
 860        .emit_frame_size =
 861                14, /* uvd_v5_0_ring_emit_fence  x1 no user fence */
 862        .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */
 863        .emit_ib = uvd_v5_0_ring_emit_ib,
 864        .emit_fence = uvd_v5_0_ring_emit_fence,
 865        .test_ring = uvd_v5_0_ring_test_ring,
 866        .test_ib = amdgpu_uvd_ring_test_ib,
 867        .insert_nop = uvd_v5_0_ring_insert_nop,
 868        .pad_ib = amdgpu_ring_generic_pad_ib,
 869        .begin_use = amdgpu_uvd_ring_begin_use,
 870        .end_use = amdgpu_uvd_ring_end_use,
 871};
 872
 873static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
 874{
 875        adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs;
 876}
 877
 878static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
 879        .set = uvd_v5_0_set_interrupt_state,
 880        .process = uvd_v5_0_process_interrupt,
 881};
 882
 883static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
 884{
 885        adev->uvd.inst->irq.num_types = 1;
 886        adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs;
 887}
 888
 889const struct amdgpu_ip_block_version uvd_v5_0_ip_block =
 890{
 891                .type = AMD_IP_BLOCK_TYPE_UVD,
 892                .major = 5,
 893                .minor = 0,
 894                .rev = 0,
 895                .funcs = &uvd_v5_0_ip_funcs,
 896};
 897