1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _gc_9_4_2_OFFSET_HEADER 24#define _gc_9_4_2_OFFSET_HEADER 25 26 27 28// addressBlock: didtind 29// base address: 0x0 30#define ixDIDT_SQ_CTRL0 0x0000 31#define ixDIDT_SQ_CTRL2 0x0002 32#define ixDIDT_SQ_STALL_CTRL 0x0004 33#define ixDIDT_SQ_TUNING_CTRL 0x0005 34#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006 35#define ixDIDT_SQ_CTRL3 0x0007 36#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008 37#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009 38#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a 39#define ixDIDT_SQ_STALL_PATTERN_7 0x000b 40#define ixDIDT_SQ_MPD_SCALE_FACTOR 0x000c 41#define ixDIDT_SQ_THROTTLE_CNTL0 0x000d 42#define ixDIDT_SQ_THROTTLE_CNTL1 0x000e 43#define ixDIDT_SQ_THROTTLE_CNTL_STATUS 0x000f 44#define ixDIDT_SQ_WEIGHT0_3 0x0010 45#define ixDIDT_SQ_WEIGHT4_7 0x0011 46#define ixDIDT_SQ_WEIGHT8_11 0x0012 47#define ixDIDT_SQ_EDC_CTRL 0x0013 48#define ixDIDT_SQ_THROTTLE_CTRL 0x0014 49#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 50#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 51#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 52#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 53#define ixDIDT_SQ_EDC_STATUS 0x0019 54#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001a 55#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001b 56#define ixDIDT_SQ_EDC_STALL_DELAY_3 0x001c 57#define ixDIDT_SQ_EDC_STALL_DELAY_4 0x001d 58#define ixDIDT_SQ_EDC_OVERFLOW 0x001e 59#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0x001f 60#define ixDIDT_DB_CTRL0 0x0020 61#define ixDIDT_DB_CTRL2 0x0022 62#define ixDIDT_DB_STALL_CTRL 0x0024 63#define ixDIDT_DB_TUNING_CTRL 0x0025 64#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0026 65#define ixDIDT_DB_CTRL3 0x0027 66#define ixDIDT_DB_STALL_PATTERN_1_2 0x0028 67#define ixDIDT_DB_STALL_PATTERN_3_4 0x0029 68#define ixDIDT_DB_STALL_PATTERN_5_6 0x002a 69#define ixDIDT_DB_STALL_PATTERN_7 0x002b 70#define ixDIDT_DB_MPD_SCALE_FACTOR 0x002c 71#define ixDIDT_DB_THROTTLE_CNTL0 0x002d 72#define ixDIDT_DB_THROTTLE_CNTL1 0x002e 73#define ixDIDT_DB_THROTTLE_CNTL_STATUS 0x002f 74#define ixDIDT_DB_WEIGHT0_3 0x0030 75#define ixDIDT_DB_WEIGHT4_7 0x0031 76#define ixDIDT_DB_WEIGHT8_11 0x0032 77#define ixDIDT_DB_EDC_CTRL 0x0033 78#define ixDIDT_DB_THROTTLE_CTRL 0x0034 79#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035 80#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036 81#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037 82#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038 83#define ixDIDT_DB_EDC_STATUS 0x0039 84#define ixDIDT_DB_EDC_STALL_DELAY_1 0x003a 85#define ixDIDT_DB_EDC_OVERFLOW 0x003e 86#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0x003f 87#define ixDIDT_TD_CTRL0 0x0040 88#define ixDIDT_TD_CTRL2 0x0042 89#define ixDIDT_TD_STALL_CTRL 0x0044 90#define ixDIDT_TD_TUNING_CTRL 0x0045 91#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0046 92#define ixDIDT_TD_CTRL3 0x0047 93#define ixDIDT_TD_STALL_PATTERN_1_2 0x0048 94#define ixDIDT_TD_STALL_PATTERN_3_4 0x0049 95#define ixDIDT_TD_STALL_PATTERN_5_6 0x004a 96#define ixDIDT_TD_STALL_PATTERN_7 0x004b 97#define ixDIDT_TD_MPD_SCALE_FACTOR 0x004c 98#define ixDIDT_TD_THROTTLE_CNTL0 0x004d 99#define ixDIDT_TD_THROTTLE_CNTL1 0x004e 100#define ixDIDT_TD_THROTTLE_CNTL_STATUS 0x004f 101#define ixDIDT_TD_WEIGHT0_3 0x0050 102#define ixDIDT_TD_WEIGHT4_7 0x0051 103#define ixDIDT_TD_WEIGHT8_11 0x0052 104#define ixDIDT_TD_EDC_CTRL 0x0053 105#define ixDIDT_TD_THROTTLE_CTRL 0x0054 106#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055 107#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056 108#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057 109#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058 110#define ixDIDT_TD_EDC_STATUS 0x0059 111#define ixDIDT_TD_EDC_STALL_DELAY_1 0x005a 112#define ixDIDT_TD_EDC_STALL_DELAY_2 0x005b 113#define ixDIDT_TD_EDC_STALL_DELAY_3 0x005c 114#define ixDIDT_TD_EDC_STALL_DELAY_4 0x005d 115#define ixDIDT_TD_EDC_OVERFLOW 0x005e 116#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA 0x005f 117#define ixDIDT_TCP_CTRL0 0x0060 118#define ixDIDT_TCP_CTRL2 0x0062 119#define ixDIDT_TCP_STALL_CTRL 0x0064 120#define ixDIDT_TCP_TUNING_CTRL 0x0065 121#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0066 122#define ixDIDT_TCP_CTRL3 0x0067 123#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0068 124#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0069 125#define ixDIDT_TCP_STALL_PATTERN_5_6 0x006a 126#define ixDIDT_TCP_STALL_PATTERN_7 0x006b 127#define ixDIDT_TCP_MPD_SCALE_FACTOR 0x006c 128#define ixDIDT_TCP_THROTTLE_CNTL0 0x006d 129#define ixDIDT_TCP_THROTTLE_CNTL1 0x006e 130#define ixDIDT_TCP_THROTTLE_CNTL_STATUS 0x006f 131#define ixDIDT_TCP_WEIGHT0_3 0x0070 132#define ixDIDT_TCP_WEIGHT4_7 0x0071 133#define ixDIDT_TCP_WEIGHT8_11 0x0072 134#define ixDIDT_TCP_EDC_CTRL 0x0073 135#define ixDIDT_TCP_THROTTLE_CTRL 0x0074 136#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075 137#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076 138#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077 139#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078 140#define ixDIDT_TCP_EDC_STATUS 0x0079 141#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x007a 142#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x007b 143#define ixDIDT_TCP_EDC_STALL_DELAY_3 0x007c 144#define ixDIDT_TCP_EDC_STALL_DELAY_4 0x007d 145#define ixDIDT_TCP_EDC_OVERFLOW 0x007e 146#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 0x007f 147#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00a0 148#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00a1 149#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00a2 150#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00a3 151#define ixDIDT_DBR_STALL_EVENT_COUNTER 0x00a4 152#define ixDIDT_SQ_EDC_PCC_PERF_COUNTER 0x00a5 153#define ixDIDT_TD_EDC_PCC_PERF_COUNTER 0x00a6 154#define ixDIDT_TCP_EDC_PCC_PERF_COUNTER 0x00a7 155#define ixDIDT_DB_EDC_PCC_PERF_COUNTER 0x00a8 156#define ixDIDT_DBR_EDC_PCC_PERF_COUNTER 0x00a9 157#define ixDIDT_SQ_CTRL1 0x00b0 158#define ixDIDT_SQ_EDC_THRESHOLD 0x00b1 159#define ixDIDT_DB_CTRL1 0x00b2 160#define ixDIDT_DB_EDC_THRESHOLD 0x00b3 161#define ixDIDT_TD_CTRL1 0x00b4 162#define ixDIDT_TD_EDC_THRESHOLD 0x00b5 163#define ixDIDT_TCP_CTRL1 0x00b6 164#define ixDIDT_TCP_EDC_THRESHOLD 0x00b7 165 166 167// addressBlock: gc_cpdec 168// base address: 0x8200 169#define regCP_CPC_STATUS 0x0084 170#define regCP_CPC_STATUS_BASE_IDX 0 171#define regCP_CPC_BUSY_STAT 0x0085 172#define regCP_CPC_BUSY_STAT_BASE_IDX 0 173#define regCP_CPC_STALLED_STAT1 0x0086 174#define regCP_CPC_STALLED_STAT1_BASE_IDX 0 175#define regCP_CPF_STATUS 0x0087 176#define regCP_CPF_STATUS_BASE_IDX 0 177#define regCP_CPF_BUSY_STAT 0x0088 178#define regCP_CPF_BUSY_STAT_BASE_IDX 0 179#define regCP_CPF_STALLED_STAT1 0x0089 180#define regCP_CPF_STALLED_STAT1_BASE_IDX 0 181#define regCP_CPC_GRBM_FREE_COUNT 0x008b 182#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 183#define regCP_CPC_PRIV_VIOLATION_ADDR 0x008c 184#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 185#define regCP_MEC_CNTL 0x008d 186#define regCP_MEC_CNTL_BASE_IDX 0 187#define regCP_MEC_ME1_HEADER_DUMP 0x008e 188#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 189#define regCP_MEC_ME2_HEADER_DUMP 0x008f 190#define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 191#define regCP_CPC_SCRATCH_INDEX 0x0090 192#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 193#define regCP_CPC_SCRATCH_DATA 0x0091 194#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 195#define regCP_CPF_GRBM_FREE_COUNT 0x0092 196#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 197#define regCP_CPC_HALT_HYST_COUNT 0x00a7 198#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 199#define regCP_CE_COMPARE_COUNT 0x00c0 200#define regCP_CE_COMPARE_COUNT_BASE_IDX 0 201#define regCP_CE_DE_COUNT 0x00c1 202#define regCP_CE_DE_COUNT_BASE_IDX 0 203#define regCP_DE_CE_COUNT 0x00c2 204#define regCP_DE_CE_COUNT_BASE_IDX 0 205#define regCP_DE_LAST_INVAL_COUNT 0x00c3 206#define regCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 207#define regCP_DE_DE_COUNT 0x00c4 208#define regCP_DE_DE_COUNT_BASE_IDX 0 209#define regCP_STALLED_STAT3 0x019c 210#define regCP_STALLED_STAT3_BASE_IDX 0 211#define regCP_STALLED_STAT1 0x019d 212#define regCP_STALLED_STAT1_BASE_IDX 0 213#define regCP_STALLED_STAT2 0x019e 214#define regCP_STALLED_STAT2_BASE_IDX 0 215#define regCP_BUSY_STAT 0x019f 216#define regCP_BUSY_STAT_BASE_IDX 0 217#define regCP_STAT 0x01a0 218#define regCP_STAT_BASE_IDX 0 219#define regCP_ME_HEADER_DUMP 0x01a1 220#define regCP_ME_HEADER_DUMP_BASE_IDX 0 221#define regCP_PFP_HEADER_DUMP 0x01a2 222#define regCP_PFP_HEADER_DUMP_BASE_IDX 0 223#define regCP_GRBM_FREE_COUNT 0x01a3 224#define regCP_GRBM_FREE_COUNT_BASE_IDX 0 225#define regCP_CE_HEADER_DUMP 0x01a4 226#define regCP_CE_HEADER_DUMP_BASE_IDX 0 227#define regCP_PFP_INSTR_PNTR 0x01a5 228#define regCP_PFP_INSTR_PNTR_BASE_IDX 0 229#define regCP_ME_INSTR_PNTR 0x01a6 230#define regCP_ME_INSTR_PNTR_BASE_IDX 0 231#define regCP_CE_INSTR_PNTR 0x01a7 232#define regCP_CE_INSTR_PNTR_BASE_IDX 0 233#define regCP_MEC1_INSTR_PNTR 0x01a8 234#define regCP_MEC1_INSTR_PNTR_BASE_IDX 0 235#define regCP_MEC2_INSTR_PNTR 0x01a9 236#define regCP_MEC2_INSTR_PNTR_BASE_IDX 0 237#define regCP_CSF_STAT 0x01b4 238#define regCP_CSF_STAT_BASE_IDX 0 239#define regCP_ME_CNTL 0x01b6 240#define regCP_ME_CNTL_BASE_IDX 0 241#define regCP_CNTX_STAT 0x01b8 242#define regCP_CNTX_STAT_BASE_IDX 0 243#define regCP_ME_PREEMPTION 0x01b9 244#define regCP_ME_PREEMPTION_BASE_IDX 0 245#define regCP_ROQ_THRESHOLDS 0x01bc 246#define regCP_ROQ_THRESHOLDS_BASE_IDX 0 247#define regCP_MEQ_STQ_THRESHOLD 0x01bd 248#define regCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 249#define regCP_RB2_RPTR 0x01be 250#define regCP_RB2_RPTR_BASE_IDX 0 251#define regCP_RB1_RPTR 0x01bf 252#define regCP_RB1_RPTR_BASE_IDX 0 253#define regCP_RB0_RPTR 0x01c0 254#define regCP_RB0_RPTR_BASE_IDX 0 255#define regCP_RB_RPTR 0x01c0 256#define regCP_RB_RPTR_BASE_IDX 0 257#define regCP_RB_WPTR_DELAY 0x01c1 258#define regCP_RB_WPTR_DELAY_BASE_IDX 0 259#define regCP_RB_WPTR_POLL_CNTL 0x01c2 260#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 261#define regCP_ROQ1_THRESHOLDS 0x01d5 262#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 263#define regCP_ROQ2_THRESHOLDS 0x01d6 264#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 265#define regCP_STQ_THRESHOLDS 0x01d7 266#define regCP_STQ_THRESHOLDS_BASE_IDX 0 267#define regCP_QUEUE_THRESHOLDS 0x01d8 268#define regCP_QUEUE_THRESHOLDS_BASE_IDX 0 269#define regCP_MEQ_THRESHOLDS 0x01d9 270#define regCP_MEQ_THRESHOLDS_BASE_IDX 0 271#define regCP_ROQ_AVAIL 0x01da 272#define regCP_ROQ_AVAIL_BASE_IDX 0 273#define regCP_STQ_AVAIL 0x01db 274#define regCP_STQ_AVAIL_BASE_IDX 0 275#define regCP_ROQ2_AVAIL 0x01dc 276#define regCP_ROQ2_AVAIL_BASE_IDX 0 277#define regCP_MEQ_AVAIL 0x01dd 278#define regCP_MEQ_AVAIL_BASE_IDX 0 279#define regCP_CMD_INDEX 0x01de 280#define regCP_CMD_INDEX_BASE_IDX 0 281#define regCP_CMD_DATA 0x01df 282#define regCP_CMD_DATA_BASE_IDX 0 283#define regCP_ROQ_RB_STAT 0x01e0 284#define regCP_ROQ_RB_STAT_BASE_IDX 0 285#define regCP_ROQ_IB1_STAT 0x01e1 286#define regCP_ROQ_IB1_STAT_BASE_IDX 0 287#define regCP_ROQ_IB2_STAT 0x01e2 288#define regCP_ROQ_IB2_STAT_BASE_IDX 0 289#define regCP_STQ_STAT 0x01e3 290#define regCP_STQ_STAT_BASE_IDX 0 291#define regCP_STQ_WR_STAT 0x01e4 292#define regCP_STQ_WR_STAT_BASE_IDX 0 293#define regCP_MEQ_STAT 0x01e5 294#define regCP_MEQ_STAT_BASE_IDX 0 295#define regCP_CEQ1_AVAIL 0x01e6 296#define regCP_CEQ1_AVAIL_BASE_IDX 0 297#define regCP_CEQ2_AVAIL 0x01e7 298#define regCP_CEQ2_AVAIL_BASE_IDX 0 299#define regCP_CE_ROQ_RB_STAT 0x01e8 300#define regCP_CE_ROQ_RB_STAT_BASE_IDX 0 301#define regCP_CE_ROQ_IB1_STAT 0x01e9 302#define regCP_CE_ROQ_IB1_STAT_BASE_IDX 0 303#define regCP_CE_ROQ_IB2_STAT 0x01ea 304#define regCP_CE_ROQ_IB2_STAT_BASE_IDX 0 305#define regCP_PRIV_VIOLATION_ADDR 0x01fa 306#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 307 308 309// addressBlock: gc_cppdec 310// base address: 0xc080 311#define regCP_EOPQ_WAIT_TIME 0x1035 312#define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 313#define regCP_CPC_MGCG_SYNC_CNTL 0x1036 314#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 315#define regCPC_INT_INFO 0x1037 316#define regCPC_INT_INFO_BASE_IDX 0 317#define regCP_VIRT_STATUS 0x1038 318#define regCP_VIRT_STATUS_BASE_IDX 0 319#define regCPC_INT_ADDR 0x1039 320#define regCPC_INT_ADDR_BASE_IDX 0 321#define regCPC_INT_PASID 0x103a 322#define regCPC_INT_PASID_BASE_IDX 0 323#define regCP_GFX_ERROR 0x103b 324#define regCP_GFX_ERROR_BASE_IDX 0 325#define regCPG_UTCL1_CNTL 0x103c 326#define regCPG_UTCL1_CNTL_BASE_IDX 0 327#define regCPC_UTCL1_CNTL 0x103d 328#define regCPC_UTCL1_CNTL_BASE_IDX 0 329#define regCPF_UTCL1_CNTL 0x103e 330#define regCPF_UTCL1_CNTL_BASE_IDX 0 331#define regCP_AQL_SMM_STATUS 0x103f 332#define regCP_AQL_SMM_STATUS_BASE_IDX 0 333#define regCP_RB0_BASE 0x1040 334#define regCP_RB0_BASE_BASE_IDX 0 335#define regCP_RB_BASE 0x1040 336#define regCP_RB_BASE_BASE_IDX 0 337#define regCP_RB0_CNTL 0x1041 338#define regCP_RB0_CNTL_BASE_IDX 0 339#define regCP_RB_CNTL 0x1041 340#define regCP_RB_CNTL_BASE_IDX 0 341#define regCP_RB_RPTR_WR 0x1042 342#define regCP_RB_RPTR_WR_BASE_IDX 0 343#define regCP_RB0_RPTR_ADDR 0x1043 344#define regCP_RB0_RPTR_ADDR_BASE_IDX 0 345#define regCP_RB_RPTR_ADDR 0x1043 346#define regCP_RB_RPTR_ADDR_BASE_IDX 0 347#define regCP_RB0_RPTR_ADDR_HI 0x1044 348#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 349#define regCP_RB_RPTR_ADDR_HI 0x1044 350#define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 351#define regCP_RB0_BUFSZ_MASK 0x1045 352#define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 353#define regCP_RB_BUFSZ_MASK 0x1045 354#define regCP_RB_BUFSZ_MASK_BASE_IDX 0 355#define regCP_RB_WPTR_POLL_ADDR_LO 0x1046 356#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 357#define regCP_RB_WPTR_POLL_ADDR_HI 0x1047 358#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 359#define regCP_INT_CNTL 0x1049 360#define regCP_INT_CNTL_BASE_IDX 0 361#define regCP_INT_STATUS 0x104a 362#define regCP_INT_STATUS_BASE_IDX 0 363#define regCP_DEVICE_ID 0x104b 364#define regCP_DEVICE_ID_BASE_IDX 0 365#define regCP_ME0_PIPE_PRIORITY_CNTS 0x104c 366#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 367#define regCP_RING_PRIORITY_CNTS 0x104c 368#define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 369#define regCP_ME0_PIPE0_PRIORITY 0x104d 370#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 371#define regCP_RING0_PRIORITY 0x104d 372#define regCP_RING0_PRIORITY_BASE_IDX 0 373#define regCP_ME0_PIPE1_PRIORITY 0x104e 374#define regCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 375#define regCP_RING1_PRIORITY 0x104e 376#define regCP_RING1_PRIORITY_BASE_IDX 0 377#define regCP_ME0_PIPE2_PRIORITY 0x104f 378#define regCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 379#define regCP_RING2_PRIORITY 0x104f 380#define regCP_RING2_PRIORITY_BASE_IDX 0 381#define regCP_FATAL_ERROR 0x1050 382#define regCP_FATAL_ERROR_BASE_IDX 0 383#define regCP_RB_VMID 0x1051 384#define regCP_RB_VMID_BASE_IDX 0 385#define regCP_ME0_PIPE0_VMID 0x1052 386#define regCP_ME0_PIPE0_VMID_BASE_IDX 0 387#define regCP_ME0_PIPE1_VMID 0x1053 388#define regCP_ME0_PIPE1_VMID_BASE_IDX 0 389#define regCP_RB0_WPTR 0x1054 390#define regCP_RB0_WPTR_BASE_IDX 0 391#define regCP_RB_WPTR 0x1054 392#define regCP_RB_WPTR_BASE_IDX 0 393#define regCP_RB0_WPTR_HI 0x1055 394#define regCP_RB0_WPTR_HI_BASE_IDX 0 395#define regCP_RB_WPTR_HI 0x1055 396#define regCP_RB_WPTR_HI_BASE_IDX 0 397#define regCP_RB1_WPTR 0x1056 398#define regCP_RB1_WPTR_BASE_IDX 0 399#define regCP_RB1_WPTR_HI 0x1057 400#define regCP_RB1_WPTR_HI_BASE_IDX 0 401#define regCP_RB2_WPTR 0x1058 402#define regCP_RB2_WPTR_BASE_IDX 0 403#define regCP_RB_DOORBELL_CONTROL 0x1059 404#define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 405#define regCP_RB_DOORBELL_RANGE_LOWER 0x105a 406#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 407#define regCP_RB_DOORBELL_RANGE_UPPER 0x105b 408#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 409#define regCP_MEC_DOORBELL_RANGE_LOWER 0x105c 410#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 411#define regCP_MEC_DOORBELL_RANGE_UPPER 0x105d 412#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 413#define regCPG_UTCL1_ERROR 0x105e 414#define regCPG_UTCL1_ERROR_BASE_IDX 0 415#define regCPC_UTCL1_ERROR 0x105f 416#define regCPC_UTCL1_ERROR_BASE_IDX 0 417#define regCP_RB1_BASE 0x1060 418#define regCP_RB1_BASE_BASE_IDX 0 419#define regCP_RB1_CNTL 0x1061 420#define regCP_RB1_CNTL_BASE_IDX 0 421#define regCP_RB1_RPTR_ADDR 0x1062 422#define regCP_RB1_RPTR_ADDR_BASE_IDX 0 423#define regCP_RB1_RPTR_ADDR_HI 0x1063 424#define regCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 425#define regCP_RB2_BASE 0x1065 426#define regCP_RB2_BASE_BASE_IDX 0 427#define regCP_RB2_CNTL 0x1066 428#define regCP_RB2_CNTL_BASE_IDX 0 429#define regCP_RB2_RPTR_ADDR 0x1067 430#define regCP_RB2_RPTR_ADDR_BASE_IDX 0 431#define regCP_RB2_RPTR_ADDR_HI 0x1068 432#define regCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 433#define regCP_RB0_ACTIVE 0x1069 434#define regCP_RB0_ACTIVE_BASE_IDX 0 435#define regCP_RB_ACTIVE 0x1069 436#define regCP_RB_ACTIVE_BASE_IDX 0 437#define regCP_INT_CNTL_RING0 0x106a 438#define regCP_INT_CNTL_RING0_BASE_IDX 0 439#define regCP_INT_CNTL_RING1 0x106b 440#define regCP_INT_CNTL_RING1_BASE_IDX 0 441#define regCP_INT_CNTL_RING2 0x106c 442#define regCP_INT_CNTL_RING2_BASE_IDX 0 443#define regCP_INT_STATUS_RING0 0x106d 444#define regCP_INT_STATUS_RING0_BASE_IDX 0 445#define regCP_INT_STATUS_RING1 0x106e 446#define regCP_INT_STATUS_RING1_BASE_IDX 0 447#define regCP_INT_STATUS_RING2 0x106f 448#define regCP_INT_STATUS_RING2_BASE_IDX 0 449#define regCP_ME_F32_INTERRUPT 0x1073 450#define regCP_ME_F32_INTERRUPT_BASE_IDX 0 451#define regCP_PFP_F32_INTERRUPT 0x1074 452#define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 453#define regCP_CE_F32_INTERRUPT 0x1075 454#define regCP_CE_F32_INTERRUPT_BASE_IDX 0 455#define regCP_MEC1_F32_INTERRUPT 0x1076 456#define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 457#define regCP_MEC2_F32_INTERRUPT 0x1077 458#define regCP_MEC2_F32_INTERRUPT_BASE_IDX 0 459#define regCP_PWR_CNTL 0x1078 460#define regCP_PWR_CNTL_BASE_IDX 0 461#define regCP_MEM_SLP_CNTL 0x1079 462#define regCP_MEM_SLP_CNTL_BASE_IDX 0 463#define regCP_ECC_DMA_FIRST_OCCURRENCE 0x107a 464#define regCP_ECC_DMA_FIRST_OCCURRENCE_BASE_IDX 0 465#define regCP_ECC_FIRSTOCCURRENCE 0x107a 466#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 467#define regCP_ECC_FIRSTOCCURRENCE_RING0 0x107b 468#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 469#define regCP_ECC_FIRSTOCCURRENCE_RING1 0x107c 470#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 471#define regCP_ECC_FIRSTOCCURRENCE_RING2 0x107d 472#define regCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 473#define regGB_EDC_MODE 0x107e 474#define regGB_EDC_MODE_BASE_IDX 0 475#define regCP_PQ_WPTR_POLL_CNTL 0x1083 476#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 477#define regCP_PQ_WPTR_POLL_CNTL1 0x1084 478#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 479#define regCP_ME1_PIPE0_INT_CNTL 0x1085 480#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 481#define regCP_ME1_PIPE1_INT_CNTL 0x1086 482#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 483#define regCP_ME1_PIPE2_INT_CNTL 0x1087 484#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 485#define regCP_ME1_PIPE3_INT_CNTL 0x1088 486#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 487#define regCP_ME2_PIPE0_INT_CNTL 0x1089 488#define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 489#define regCP_ME2_PIPE1_INT_CNTL 0x108a 490#define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 491#define regCP_ME2_PIPE2_INT_CNTL 0x108b 492#define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 493#define regCP_ME2_PIPE3_INT_CNTL 0x108c 494#define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 495#define regCP_ME1_PIPE0_INT_STATUS 0x108d 496#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 497#define regCP_ME1_PIPE1_INT_STATUS 0x108e 498#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 499#define regCP_ME1_PIPE2_INT_STATUS 0x108f 500#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 501#define regCP_ME1_PIPE3_INT_STATUS 0x1090 502#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 503#define regCP_ME2_PIPE0_INT_STATUS 0x1091 504#define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 505#define regCP_ME2_PIPE1_INT_STATUS 0x1092 506#define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 507#define regCP_ME2_PIPE2_INT_STATUS 0x1093 508#define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 509#define regCP_ME2_PIPE3_INT_STATUS 0x1094 510#define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 511#define regCC_GC_EDC_CONFIG 0x1098 512#define regCC_GC_EDC_CONFIG_BASE_IDX 0 513#define regCP_ME1_PIPE_PRIORITY_CNTS 0x1099 514#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 515#define regCP_ME1_PIPE0_PRIORITY 0x109a 516#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 517#define regCP_ME1_PIPE1_PRIORITY 0x109b 518#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 519#define regCP_ME1_PIPE2_PRIORITY 0x109c 520#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 521#define regCP_ME1_PIPE3_PRIORITY 0x109d 522#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 523#define regCP_ME2_PIPE_PRIORITY_CNTS 0x109e 524#define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 525#define regCP_ME2_PIPE0_PRIORITY 0x109f 526#define regCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 527#define regCP_ME2_PIPE1_PRIORITY 0x10a0 528#define regCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 529#define regCP_ME2_PIPE2_PRIORITY 0x10a1 530#define regCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 531#define regCP_ME2_PIPE3_PRIORITY 0x10a2 532#define regCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 533#define regCP_CE_PRGRM_CNTR_START 0x10a3 534#define regCP_CE_PRGRM_CNTR_START_BASE_IDX 0 535#define regCP_PFP_PRGRM_CNTR_START 0x10a4 536#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 537#define regCP_ME_PRGRM_CNTR_START 0x10a5 538#define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 539#define regCP_MEC1_PRGRM_CNTR_START 0x10a6 540#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 541#define regCP_MEC2_PRGRM_CNTR_START 0x10a7 542#define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 543#define regCP_CE_INTR_ROUTINE_START 0x10a8 544#define regCP_CE_INTR_ROUTINE_START_BASE_IDX 0 545#define regCP_PFP_INTR_ROUTINE_START 0x10a9 546#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 547#define regCP_ME_INTR_ROUTINE_START 0x10aa 548#define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 549#define regCP_MEC1_INTR_ROUTINE_START 0x10ab 550#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 551#define regCP_MEC2_INTR_ROUTINE_START 0x10ac 552#define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 553#define regCP_CONTEXT_CNTL 0x10ad 554#define regCP_CONTEXT_CNTL_BASE_IDX 0 555#define regCP_MAX_CONTEXT 0x10ae 556#define regCP_MAX_CONTEXT_BASE_IDX 0 557#define regCP_IQ_WAIT_TIME1 0x10af 558#define regCP_IQ_WAIT_TIME1_BASE_IDX 0 559#define regCP_IQ_WAIT_TIME2 0x10b0 560#define regCP_IQ_WAIT_TIME2_BASE_IDX 0 561#define regCP_RB0_BASE_HI 0x10b1 562#define regCP_RB0_BASE_HI_BASE_IDX 0 563#define regCP_RB1_BASE_HI 0x10b2 564#define regCP_RB1_BASE_HI_BASE_IDX 0 565#define regCP_VMID_RESET 0x10b3 566#define regCP_VMID_RESET_BASE_IDX 0 567#define regCPC_INT_CNTL 0x10b4 568#define regCPC_INT_CNTL_BASE_IDX 0 569#define regCPC_INT_STATUS 0x10b5 570#define regCPC_INT_STATUS_BASE_IDX 0 571#define regCP_VMID_PREEMPT 0x10b6 572#define regCP_VMID_PREEMPT_BASE_IDX 0 573#define regCPC_INT_CNTX_ID 0x10b7 574#define regCPC_INT_CNTX_ID_BASE_IDX 0 575#define regCP_PQ_STATUS 0x10b8 576#define regCP_PQ_STATUS_BASE_IDX 0 577#define regCP_CPC_IC_BASE_LO 0x10b9 578#define regCP_CPC_IC_BASE_LO_BASE_IDX 0 579#define regCP_CPC_IC_BASE_HI 0x10ba 580#define regCP_CPC_IC_BASE_HI_BASE_IDX 0 581#define regCP_CPC_IC_BASE_CNTL 0x10bb 582#define regCP_CPC_IC_BASE_CNTL_BASE_IDX 0 583#define regCP_CPC_IC_OP_CNTL 0x10bc 584#define regCP_CPC_IC_OP_CNTL_BASE_IDX 0 585#define regCP_MEC1_F32_INT_DIS 0x10bd 586#define regCP_MEC1_F32_INT_DIS_BASE_IDX 0 587#define regCP_MEC2_F32_INT_DIS 0x10be 588#define regCP_MEC2_F32_INT_DIS_BASE_IDX 0 589#define regCP_VMID_STATUS 0x10bf 590#define regCP_VMID_STATUS_BASE_IDX 0 591 592 593// addressBlock: gc_cppdec2 594// base address: 0xc600 595#define regCP_RB_DOORBELL_CONTROL_SCH_0 0x1180 596#define regCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0 597#define regCP_RB_DOORBELL_CONTROL_SCH_1 0x1181 598#define regCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0 599#define regCP_RB_DOORBELL_CONTROL_SCH_2 0x1182 600#define regCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0 601#define regCP_RB_DOORBELL_CONTROL_SCH_3 0x1183 602#define regCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0 603#define regCP_RB_DOORBELL_CONTROL_SCH_4 0x1184 604#define regCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0 605#define regCP_RB_DOORBELL_CONTROL_SCH_5 0x1185 606#define regCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0 607#define regCP_RB_DOORBELL_CONTROL_SCH_6 0x1186 608#define regCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0 609#define regCP_RB_DOORBELL_CONTROL_SCH_7 0x1187 610#define regCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0 611#define regCP_RB_DOORBELL_CLEAR 0x1188 612#define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 613#define regCPF_EDC_TAG_CNT 0x1189 614#define regCPF_EDC_TAG_CNT_BASE_IDX 0 615#define regCPF_EDC_ROQ_CNT 0x118a 616#define regCPF_EDC_ROQ_CNT_BASE_IDX 0 617#define regCPG_EDC_TAG_CNT 0x118b 618#define regCPG_EDC_TAG_CNT_BASE_IDX 0 619#define regCPG_EDC_DMA_CNT 0x118d 620#define regCPG_EDC_DMA_CNT_BASE_IDX 0 621#define regCPC_EDC_SCRATCH_CNT 0x118e 622#define regCPC_EDC_SCRATCH_CNT_BASE_IDX 0 623#define regCPC_EDC_UCODE_CNT 0x118f 624#define regCPC_EDC_UCODE_CNT_BASE_IDX 0 625#define regDC_EDC_STATE_CNT 0x1191 626#define regDC_EDC_STATE_CNT_BASE_IDX 0 627#define regDC_EDC_CSINVOC_CNT 0x1192 628#define regDC_EDC_CSINVOC_CNT_BASE_IDX 0 629#define regDC_EDC_RESTORE_CNT 0x1193 630#define regDC_EDC_RESTORE_CNT_BASE_IDX 0 631#define regCP_CPF_DSM_CNTL 0x1194 632#define regCP_CPF_DSM_CNTL_BASE_IDX 0 633#define regCP_CPG_DSM_CNTL 0x1195 634#define regCP_CPG_DSM_CNTL_BASE_IDX 0 635#define regCP_CPC_DSM_CNTL 0x1196 636#define regCP_CPC_DSM_CNTL_BASE_IDX 0 637#define regCP_CPF_DSM_CNTL2 0x1197 638#define regCP_CPF_DSM_CNTL2_BASE_IDX 0 639#define regCP_CPG_DSM_CNTL2 0x1198 640#define regCP_CPG_DSM_CNTL2_BASE_IDX 0 641#define regCP_CPC_DSM_CNTL2 0x1199 642#define regCP_CPC_DSM_CNTL2_BASE_IDX 0 643#define regCP_CPF_DSM_CNTL2A 0x119a 644#define regCP_CPF_DSM_CNTL2A_BASE_IDX 0 645#define regCP_CPG_DSM_CNTL2A 0x119b 646#define regCP_CPG_DSM_CNTL2A_BASE_IDX 0 647#define regCP_CPC_DSM_CNTL2A 0x119c 648#define regCP_CPC_DSM_CNTL2A_BASE_IDX 0 649#define regCP_EDC_FUE_CNTL 0x119d 650#define regCP_EDC_FUE_CNTL_BASE_IDX 0 651#define regCP_GFX_MQD_CONTROL 0x11a0 652#define regCP_GFX_MQD_CONTROL_BASE_IDX 0 653#define regCP_GFX_MQD_BASE_ADDR 0x11a1 654#define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 655#define regCP_GFX_MQD_BASE_ADDR_HI 0x11a2 656#define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 657#define regCP_RB_STATUS 0x11a3 658#define regCP_RB_STATUS_BASE_IDX 0 659#define regCPG_UTCL1_STATUS 0x11b4 660#define regCPG_UTCL1_STATUS_BASE_IDX 0 661#define regCPC_UTCL1_STATUS 0x11b5 662#define regCPC_UTCL1_STATUS_BASE_IDX 0 663#define regCPF_UTCL1_STATUS 0x11b6 664#define regCPF_UTCL1_STATUS_BASE_IDX 0 665#define regCP_SD_CNTL 0x11b7 666#define regCP_SD_CNTL_BASE_IDX 0 667#define regCP_SOFT_RESET_CNTL 0x11b9 668#define regCP_SOFT_RESET_CNTL_BASE_IDX 0 669#define regCP_CPC_GFX_CNTL 0x11ba 670#define regCP_CPC_GFX_CNTL_BASE_IDX 0 671 672 673// addressBlock: gc_cpphqddec 674// base address: 0xc800 675#define regCP_HQD_GFX_CONTROL 0x123e 676#define regCP_HQD_GFX_CONTROL_BASE_IDX 0 677#define regCP_HQD_GFX_STATUS 0x123f 678#define regCP_HQD_GFX_STATUS_BASE_IDX 0 679#define regCP_HPD_ROQ_OFFSETS 0x1240 680#define regCP_HPD_ROQ_OFFSETS_BASE_IDX 0 681#define regCP_HPD_STATUS0 0x1241 682#define regCP_HPD_STATUS0_BASE_IDX 0 683#define regCP_HPD_UTCL1_CNTL 0x1242 684#define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 685#define regCP_HPD_UTCL1_ERROR 0x1243 686#define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 687#define regCP_HPD_UTCL1_ERROR_ADDR 0x1244 688#define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 689#define regCP_MQD_BASE_ADDR 0x1245 690#define regCP_MQD_BASE_ADDR_BASE_IDX 0 691#define regCP_MQD_BASE_ADDR_HI 0x1246 692#define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 693#define regCP_HQD_ACTIVE 0x1247 694#define regCP_HQD_ACTIVE_BASE_IDX 0 695#define regCP_HQD_VMID 0x1248 696#define regCP_HQD_VMID_BASE_IDX 0 697#define regCP_HQD_PERSISTENT_STATE 0x1249 698#define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 699#define regCP_HQD_PIPE_PRIORITY 0x124a 700#define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 701#define regCP_HQD_QUEUE_PRIORITY 0x124b 702#define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 703#define regCP_HQD_QUANTUM 0x124c 704#define regCP_HQD_QUANTUM_BASE_IDX 0 705#define regCP_HQD_PQ_BASE 0x124d 706#define regCP_HQD_PQ_BASE_BASE_IDX 0 707#define regCP_HQD_PQ_BASE_HI 0x124e 708#define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 709#define regCP_HQD_PQ_RPTR 0x124f 710#define regCP_HQD_PQ_RPTR_BASE_IDX 0 711#define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 712#define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 713#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 714#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 715#define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 716#define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 717#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 718#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 719#define regCP_HQD_PQ_DOORBELL_CONTROL 0x1254 720#define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 721#define regCP_HQD_PQ_CONTROL 0x1256 722#define regCP_HQD_PQ_CONTROL_BASE_IDX 0 723#define regCP_HQD_IB_BASE_ADDR 0x1257 724#define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 725#define regCP_HQD_IB_BASE_ADDR_HI 0x1258 726#define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 727#define regCP_HQD_IB_RPTR 0x1259 728#define regCP_HQD_IB_RPTR_BASE_IDX 0 729#define regCP_HQD_IB_CONTROL 0x125a 730#define regCP_HQD_IB_CONTROL_BASE_IDX 0 731#define regCP_HQD_IQ_TIMER 0x125b 732#define regCP_HQD_IQ_TIMER_BASE_IDX 0 733#define regCP_HQD_IQ_RPTR 0x125c 734#define regCP_HQD_IQ_RPTR_BASE_IDX 0 735#define regCP_HQD_DEQUEUE_REQUEST 0x125d 736#define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 737#define regCP_HQD_DMA_OFFLOAD 0x125e 738#define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 739#define regCP_HQD_OFFLOAD 0x125e 740#define regCP_HQD_OFFLOAD_BASE_IDX 0 741#define regCP_HQD_SEMA_CMD 0x125f 742#define regCP_HQD_SEMA_CMD_BASE_IDX 0 743#define regCP_HQD_MSG_TYPE 0x1260 744#define regCP_HQD_MSG_TYPE_BASE_IDX 0 745#define regCP_HQD_ATOMIC0_PREOP_LO 0x1261 746#define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 747#define regCP_HQD_ATOMIC0_PREOP_HI 0x1262 748#define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 749#define regCP_HQD_ATOMIC1_PREOP_LO 0x1263 750#define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 751#define regCP_HQD_ATOMIC1_PREOP_HI 0x1264 752#define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 753#define regCP_HQD_HQ_SCHEDULER0 0x1265 754#define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 755#define regCP_HQD_HQ_STATUS0 0x1265 756#define regCP_HQD_HQ_STATUS0_BASE_IDX 0 757#define regCP_HQD_HQ_CONTROL0 0x1266 758#define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 759#define regCP_HQD_HQ_SCHEDULER1 0x1266 760#define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 761#define regCP_MQD_CONTROL 0x1267 762#define regCP_MQD_CONTROL_BASE_IDX 0 763#define regCP_HQD_HQ_STATUS1 0x1268 764#define regCP_HQD_HQ_STATUS1_BASE_IDX 0 765#define regCP_HQD_HQ_CONTROL1 0x1269 766#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 767#define regCP_HQD_EOP_BASE_ADDR 0x126a 768#define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 769#define regCP_HQD_EOP_BASE_ADDR_HI 0x126b 770#define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 771#define regCP_HQD_EOP_CONTROL 0x126c 772#define regCP_HQD_EOP_CONTROL_BASE_IDX 0 773#define regCP_HQD_EOP_RPTR 0x126d 774#define regCP_HQD_EOP_RPTR_BASE_IDX 0 775#define regCP_HQD_EOP_WPTR 0x126e 776#define regCP_HQD_EOP_WPTR_BASE_IDX 0 777#define regCP_HQD_EOP_EVENTS 0x126f 778#define regCP_HQD_EOP_EVENTS_BASE_IDX 0 779#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270 780#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 781#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271 782#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 783#define regCP_HQD_CTX_SAVE_CONTROL 0x1272 784#define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 785#define regCP_HQD_CNTL_STACK_OFFSET 0x1273 786#define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 787#define regCP_HQD_CNTL_STACK_SIZE 0x1274 788#define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 789#define regCP_HQD_WG_STATE_OFFSET 0x1275 790#define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 791#define regCP_HQD_CTX_SAVE_SIZE 0x1276 792#define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 793#define regCP_HQD_GDS_RESOURCE_STATE 0x1277 794#define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 795#define regCP_HQD_ERROR 0x1278 796#define regCP_HQD_ERROR_BASE_IDX 0 797#define regCP_HQD_EOP_WPTR_MEM 0x1279 798#define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 799#define regCP_HQD_AQL_CONTROL 0x127a 800#define regCP_HQD_AQL_CONTROL_BASE_IDX 0 801#define regCP_HQD_PQ_WPTR_LO 0x127b 802#define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 803#define regCP_HQD_PQ_WPTR_HI 0x127c 804#define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 805 806 807// addressBlock: gc_didtdec 808// base address: 0xca00 809#define regDIDT_IND_INDEX 0x1280 810#define regDIDT_IND_INDEX_BASE_IDX 0 811#define regDIDT_IND_DATA 0x1281 812#define regDIDT_IND_DATA_BASE_IDX 0 813#define regDIDT_INDEX_AUTO_INCR_EN 0x1282 814#define regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 0 815 816 817// addressBlock: gc_ea_gceadec 818// base address: 0xa800 819#define regGCEA_DRAM_RD_CLI2GRP_MAP0 0x0a00 820#define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 821#define regGCEA_DRAM_RD_CLI2GRP_MAP1 0x0a01 822#define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 823#define regGCEA_DRAM_WR_CLI2GRP_MAP0 0x0a02 824#define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 825#define regGCEA_DRAM_WR_CLI2GRP_MAP1 0x0a03 826#define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 827#define regGCEA_DRAM_RD_GRP2VC_MAP 0x0a04 828#define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 829#define regGCEA_DRAM_WR_GRP2VC_MAP 0x0a05 830#define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 831#define regGCEA_DRAM_RD_LAZY 0x0a06 832#define regGCEA_DRAM_RD_LAZY_BASE_IDX 0 833#define regGCEA_DRAM_WR_LAZY 0x0a07 834#define regGCEA_DRAM_WR_LAZY_BASE_IDX 0 835#define regGCEA_DRAM_RD_CAM_CNTL 0x0a08 836#define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 837#define regGCEA_DRAM_WR_CAM_CNTL 0x0a09 838#define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 839#define regGCEA_DRAM_PAGE_BURST 0x0a0a 840#define regGCEA_DRAM_PAGE_BURST_BASE_IDX 0 841#define regGCEA_DRAM_RD_PRI_AGE 0x0a0b 842#define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 843#define regGCEA_DRAM_WR_PRI_AGE 0x0a0c 844#define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 845#define regGCEA_DRAM_RD_PRI_QUEUING 0x0a0d 846#define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 847#define regGCEA_DRAM_WR_PRI_QUEUING 0x0a0e 848#define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 849#define regGCEA_DRAM_RD_PRI_FIXED 0x0a0f 850#define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 851#define regGCEA_DRAM_WR_PRI_FIXED 0x0a10 852#define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 853#define regGCEA_DRAM_RD_PRI_URGENCY 0x0a11 854#define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 855#define regGCEA_DRAM_WR_PRI_URGENCY 0x0a12 856#define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 857#define regGCEA_DRAM_RD_PRI_QUANT_PRI1 0x0a13 858#define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 859#define regGCEA_DRAM_RD_PRI_QUANT_PRI2 0x0a14 860#define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 861#define regGCEA_DRAM_RD_PRI_QUANT_PRI3 0x0a15 862#define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 863#define regGCEA_DRAM_WR_PRI_QUANT_PRI1 0x0a16 864#define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 865#define regGCEA_DRAM_WR_PRI_QUANT_PRI2 0x0a17 866#define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 867#define regGCEA_DRAM_WR_PRI_QUANT_PRI3 0x0a18 868#define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 869#define regGCEA_ADDRNORM_BASE_ADDR0 0x0a34 870#define regGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX 0 871#define regGCEA_ADDRNORM_LIMIT_ADDR0 0x0a35 872#define regGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 873#define regGCEA_ADDRNORM_BASE_ADDR1 0x0a36 874#define regGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX 0 875#define regGCEA_ADDRNORM_LIMIT_ADDR1 0x0a37 876#define regGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 877#define regGCEA_ADDRNORM_OFFSET_ADDR1 0x0a38 878#define regGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 879#define regGCEA_ADDRNORM_BASE_ADDR2 0x0a39 880#define regGCEA_ADDRNORM_BASE_ADDR2_BASE_IDX 0 881#define regGCEA_ADDRNORM_LIMIT_ADDR2 0x0a3a 882#define regGCEA_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 883#define regGCEA_ADDRNORM_BASE_ADDR3 0x0a3b 884#define regGCEA_ADDRNORM_BASE_ADDR3_BASE_IDX 0 885#define regGCEA_ADDRNORM_LIMIT_ADDR3 0x0a3c 886#define regGCEA_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 887#define regGCEA_ADDRNORM_OFFSET_ADDR3 0x0a3d 888#define regGCEA_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 889#define regGCEA_ADDRNORM_MEGABASE_ADDR0 0x0a3e 890#define regGCEA_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 891#define regGCEA_ADDRNORM_MEGALIMIT_ADDR0 0x0a3f 892#define regGCEA_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 893#define regGCEA_ADDRNORM_MEGABASE_ADDR1 0x0a40 894#define regGCEA_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 895#define regGCEA_ADDRNORM_MEGALIMIT_ADDR1 0x0a41 896#define regGCEA_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 897#define regGCEA_ADDRNORMDRAM_HOLE_CNTL 0x0a43 898#define regGCEA_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 899#define regGCEA_ADDRNORMGMI_HOLE_CNTL 0x0a44 900#define regGCEA_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 901#define regGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0a45 902#define regGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 903#define regGCEA_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0a46 904#define regGCEA_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 905#define regGCEA_ADDRDEC_BANK_CFG 0x0a47 906#define regGCEA_ADDRDEC_BANK_CFG_BASE_IDX 0 907#define regGCEA_ADDRDEC_MISC_CFG 0x0a48 908#define regGCEA_ADDRDEC_MISC_CFG_BASE_IDX 0 909#define regGCEA_ADDRDECDRAM_HARVEST_ENABLE 0x0a53 910#define regGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 911#define regGCEA_ADDRDECGMI_HARVEST_ENABLE 0x0a5e 912#define regGCEA_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 913#define regGCEA_ADDRDEC0_BASE_ADDR_CS0 0x0a5f 914#define regGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 915#define regGCEA_ADDRDEC0_BASE_ADDR_CS1 0x0a60 916#define regGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 917#define regGCEA_ADDRDEC0_BASE_ADDR_CS2 0x0a61 918#define regGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 919#define regGCEA_ADDRDEC0_BASE_ADDR_CS3 0x0a62 920#define regGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 921#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0x0a63 922#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 923#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0x0a64 924#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 925#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0x0a65 926#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 927#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0x0a66 928#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 929#define regGCEA_ADDRDEC0_ADDR_MASK_CS01 0x0a67 930#define regGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 931#define regGCEA_ADDRDEC0_ADDR_MASK_CS23 0x0a68 932#define regGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 933#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0x0a69 934#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 935#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0x0a6a 936#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 937#define regGCEA_ADDRDEC0_ADDR_CFG_CS01 0x0a6b 938#define regGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 939#define regGCEA_ADDRDEC0_ADDR_CFG_CS23 0x0a6c 940#define regGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 941#define regGCEA_ADDRDEC0_ADDR_SEL_CS01 0x0a6d 942#define regGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 943#define regGCEA_ADDRDEC0_ADDR_SEL_CS23 0x0a6e 944#define regGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 945#define regGCEA_ADDRDEC0_ADDR_SEL2_CS01 0x0a6f 946#define regGCEA_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 947#define regGCEA_ADDRDEC0_ADDR_SEL2_CS23 0x0a70 948#define regGCEA_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 949#define regGCEA_ADDRDEC0_COL_SEL_LO_CS01 0x0a71 950#define regGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 951#define regGCEA_ADDRDEC0_COL_SEL_LO_CS23 0x0a72 952#define regGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 953#define regGCEA_ADDRDEC0_COL_SEL_HI_CS01 0x0a73 954#define regGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 955#define regGCEA_ADDRDEC0_COL_SEL_HI_CS23 0x0a74 956#define regGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 957#define regGCEA_ADDRDEC0_RM_SEL_CS01 0x0a75 958#define regGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 959#define regGCEA_ADDRDEC0_RM_SEL_CS23 0x0a76 960#define regGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 961#define regGCEA_ADDRDEC0_RM_SEL_SECCS01 0x0a77 962#define regGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 963#define regGCEA_ADDRDEC0_RM_SEL_SECCS23 0x0a78 964#define regGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 965#define regGCEA_ADDRDEC1_BASE_ADDR_CS0 0x0a79 966#define regGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 967#define regGCEA_ADDRDEC1_BASE_ADDR_CS1 0x0a7a 968#define regGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 969#define regGCEA_ADDRDEC1_BASE_ADDR_CS2 0x0a7b 970#define regGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 971#define regGCEA_ADDRDEC1_BASE_ADDR_CS3 0x0a7c 972#define regGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 973#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0x0a7d 974#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 975#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0x0a7e 976#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 977#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0x0a7f 978#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 979#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0x0a80 980#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 981#define regGCEA_ADDRDEC1_ADDR_MASK_CS01 0x0a81 982#define regGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 983#define regGCEA_ADDRDEC1_ADDR_MASK_CS23 0x0a82 984#define regGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 985#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0x0a83 986#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 987#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0x0a84 988#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 989#define regGCEA_ADDRDEC1_ADDR_CFG_CS01 0x0a85 990#define regGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 991#define regGCEA_ADDRDEC1_ADDR_CFG_CS23 0x0a86 992#define regGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 993#define regGCEA_ADDRDEC1_ADDR_SEL_CS01 0x0a87 994#define regGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 995#define regGCEA_ADDRDEC1_ADDR_SEL_CS23 0x0a88 996#define regGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 997#define regGCEA_ADDRDEC1_ADDR_SEL2_CS01 0x0a89 998#define regGCEA_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 999#define regGCEA_ADDRDEC1_ADDR_SEL2_CS23 0x0a8a 1000#define regGCEA_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
1001#define regGCEA_ADDRDEC1_COL_SEL_LO_CS01 0x0a8b 1002#define regGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 1003#define regGCEA_ADDRDEC1_COL_SEL_LO_CS23 0x0a8c 1004#define regGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 1005#define regGCEA_ADDRDEC1_COL_SEL_HI_CS01 0x0a8d 1006#define regGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 1007#define regGCEA_ADDRDEC1_COL_SEL_HI_CS23 0x0a8e 1008#define regGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 1009#define regGCEA_ADDRDEC1_RM_SEL_CS01 0x0a8f 1010#define regGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 1011#define regGCEA_ADDRDEC1_RM_SEL_CS23 0x0a90 1012#define regGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 1013#define regGCEA_ADDRDEC1_RM_SEL_SECCS01 0x0a91 1014#define regGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 1015#define regGCEA_ADDRDEC1_RM_SEL_SECCS23 0x0a92 1016#define regGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 1017#define regGCEA_ADDRDEC2_BASE_ADDR_CS0 0x0a93 1018#define regGCEA_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 1019#define regGCEA_ADDRDEC2_BASE_ADDR_CS1 0x0a94 1020#define regGCEA_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 1021#define regGCEA_ADDRDEC2_BASE_ADDR_CS2 0x0a95 1022#define regGCEA_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 1023#define regGCEA_ADDRDEC2_BASE_ADDR_CS3 0x0a96 1024#define regGCEA_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 1025#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS0 0x0a97 1026#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 1027#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS1 0x0a98 1028#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 1029#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS2 0x0a99 1030#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 1031#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS3 0x0a9a 1032#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 1033#define regGCEA_ADDRDEC2_ADDR_MASK_CS01 0x0a9b 1034#define regGCEA_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 1035#define regGCEA_ADDRDEC2_ADDR_MASK_CS23 0x0a9c 1036#define regGCEA_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 1037#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS01 0x0a9d 1038#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 1039#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS23 0x0a9e 1040#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 1041#define regGCEA_ADDRDEC2_ADDR_CFG_CS01 0x0a9f 1042#define regGCEA_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 1043#define regGCEA_ADDRDEC2_ADDR_CFG_CS23 0x0aa0 1044#define regGCEA_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 1045#define regGCEA_ADDRDEC2_ADDR_SEL_CS01 0x0aa1 1046#define regGCEA_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 1047#define regGCEA_ADDRDEC2_ADDR_SEL_CS23 0x0aa2 1048#define regGCEA_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 1049#define regGCEA_ADDRDEC2_ADDR_SEL2_CS01 0x0aa3 1050#define regGCEA_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 1051#define regGCEA_ADDRDEC2_ADDR_SEL2_CS23 0x0aa4 1052#define regGCEA_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 1053#define regGCEA_ADDRDEC2_COL_SEL_LO_CS01 0x0aa5 1054#define regGCEA_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 1055#define regGCEA_ADDRDEC2_COL_SEL_LO_CS23 0x0aa6 1056#define regGCEA_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 1057#define regGCEA_ADDRDEC2_COL_SEL_HI_CS01 0x0aa7 1058#define regGCEA_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 1059#define regGCEA_ADDRDEC2_COL_SEL_HI_CS23 0x0aa8 1060#define regGCEA_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 1061#define regGCEA_ADDRDEC2_RM_SEL_CS01 0x0aa9 1062#define regGCEA_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 1063#define regGCEA_ADDRDEC2_RM_SEL_CS23 0x0aaa 1064#define regGCEA_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 1065#define regGCEA_ADDRDEC2_RM_SEL_SECCS01 0x0aab 1066#define regGCEA_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 1067#define regGCEA_ADDRDEC2_RM_SEL_SECCS23 0x0aac 1068#define regGCEA_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 1069#define regGCEA_ADDRNORMDRAM_GLOBAL_CNTL 0x0aad 1070#define regGCEA_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 1071#define regGCEA_ADDRNORMGMI_GLOBAL_CNTL 0x0aae 1072#define regGCEA_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 1073#define regGCEA_ADDRNORM_MEGACONTROL_ADDR0 0x0ad1 1074#define regGCEA_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 1075#define regGCEA_ADDRNORM_MEGACONTROL_ADDR1 0x0ad2 1076#define regGCEA_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 1077#define regGCEA_ADDRNORMDRAM_MASKING 0x0ad3 1078#define regGCEA_ADDRNORMDRAM_MASKING_BASE_IDX 0 1079#define regGCEA_ADDRNORMGMI_MASKING 0x0ad4 1080#define regGCEA_ADDRNORMGMI_MASKING_BASE_IDX 0 1081#define regGCEA_IO_RD_CLI2GRP_MAP0 0x0ad5 1082#define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 1083#define regGCEA_IO_RD_CLI2GRP_MAP1 0x0ad6 1084#define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 1085#define regGCEA_IO_WR_CLI2GRP_MAP0 0x0ad7 1086#define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 1087#define regGCEA_IO_WR_CLI2GRP_MAP1 0x0ad8 1088#define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 1089#define regGCEA_IO_RD_COMBINE_FLUSH 0x0ad9 1090#define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 1091#define regGCEA_IO_WR_COMBINE_FLUSH 0x0ada 1092#define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 1093#define regGCEA_IO_GROUP_BURST 0x0adb 1094#define regGCEA_IO_GROUP_BURST_BASE_IDX 0 1095#define regGCEA_IO_RD_PRI_AGE 0x0adc 1096#define regGCEA_IO_RD_PRI_AGE_BASE_IDX 0 1097#define regGCEA_IO_WR_PRI_AGE 0x0add 1098#define regGCEA_IO_WR_PRI_AGE_BASE_IDX 0 1099#define regGCEA_IO_RD_PRI_QUEUING 0x0ade 1100#define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 1101#define regGCEA_IO_WR_PRI_QUEUING 0x0adf 1102#define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 1103#define regGCEA_IO_RD_PRI_FIXED 0x0ae0 1104#define regGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 1105#define regGCEA_IO_WR_PRI_FIXED 0x0ae1 1106#define regGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 1107#define regGCEA_IO_RD_PRI_URGENCY 0x0ae2 1108#define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 1109#define regGCEA_IO_WR_PRI_URGENCY 0x0ae3 1110#define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 1111#define regGCEA_IO_RD_PRI_URGENCY_MASKING 0x0ae4 1112#define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 1113#define regGCEA_IO_WR_PRI_URGENCY_MASKING 0x0ae5 1114#define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 1115#define regGCEA_IO_RD_PRI_QUANT_PRI1 0x0ae6 1116#define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 1117#define regGCEA_IO_RD_PRI_QUANT_PRI2 0x0ae7 1118#define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 1119#define regGCEA_IO_RD_PRI_QUANT_PRI3 0x0ae8 1120#define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 1121#define regGCEA_IO_WR_PRI_QUANT_PRI1 0x0ae9 1122#define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 1123#define regGCEA_IO_WR_PRI_QUANT_PRI2 0x0aea 1124#define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 1125#define regGCEA_IO_WR_PRI_QUANT_PRI3 0x0aeb 1126#define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 1127#define regGCEA_MISC 0x0afa 1128#define regGCEA_MISC_BASE_IDX 0 1129#define regGCEA_LATENCY_SAMPLING 0x0afb 1130#define regGCEA_LATENCY_SAMPLING_BASE_IDX 0 1131#define regGCEA_PERFCOUNTER_LO 0x0afc 1132#define regGCEA_PERFCOUNTER_LO_BASE_IDX 0 1133#define regGCEA_PERFCOUNTER_HI 0x0afd 1134#define regGCEA_PERFCOUNTER_HI_BASE_IDX 0 1135#define regGCEA_PERFCOUNTER0_CFG 0x0afe 1136#define regGCEA_PERFCOUNTER0_CFG_BASE_IDX 0 1137#define regGCEA_PERFCOUNTER1_CFG 0x0aff 1138#define regGCEA_PERFCOUNTER1_CFG_BASE_IDX 0 1139 1140 1141// addressBlock: gc_ea_gceadec2 1142// base address: 0x9c00 1143#define regGCEA_PERFCOUNTER_RSLT_CNTL 0x0700 1144#define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1145#define regGCEA_EDC_CNT 0x0706 1146#define regGCEA_EDC_CNT_BASE_IDX 0 1147#define regGCEA_EDC_CNT2 0x0707 1148#define regGCEA_EDC_CNT2_BASE_IDX 0 1149#define regGCEA_DSM_CNTL 0x0708 1150#define regGCEA_DSM_CNTL_BASE_IDX 0 1151#define regGCEA_DSM_CNTLA 0x0709 1152#define regGCEA_DSM_CNTLA_BASE_IDX 0 1153#define regGCEA_DSM_CNTLB 0x070a 1154#define regGCEA_DSM_CNTLB_BASE_IDX 0 1155#define regGCEA_DSM_CNTL2 0x070b 1156#define regGCEA_DSM_CNTL2_BASE_IDX 0 1157#define regGCEA_DSM_CNTL2A 0x070c 1158#define regGCEA_DSM_CNTL2A_BASE_IDX 0 1159#define regGCEA_DSM_CNTL2B 0x070d 1160#define regGCEA_DSM_CNTL2B_BASE_IDX 0 1161#define regGCEA_TCC_XBR_CREDITS 0x070e 1162#define regGCEA_TCC_XBR_CREDITS_BASE_IDX 0 1163#define regGCEA_TCC_XBR_MAXBURST 0x070f 1164#define regGCEA_TCC_XBR_MAXBURST_BASE_IDX 0 1165#define regGCEA_PROBE_CNTL 0x0710 1166#define regGCEA_PROBE_CNTL_BASE_IDX 0 1167#define regGCEA_PROBE_MAP 0x0711 1168#define regGCEA_PROBE_MAP_BASE_IDX 0 1169#define regGCEA_ERR_STATUS 0x0712 1170#define regGCEA_ERR_STATUS_BASE_IDX 0 1171#define regGCEA_MISC2 0x0713 1172#define regGCEA_MISC2_BASE_IDX 0 1173#define regGCEA_DRAM_BANK_ARB 0x0714 1174#define regGCEA_DRAM_BANK_ARB_BASE_IDX 0 1175#define regGCEA_ADDRDEC_SELECT 0x071a 1176#define regGCEA_ADDRDEC_SELECT_BASE_IDX 0 1177#define regGCEA_EDC_CNT3 0x071b 1178#define regGCEA_EDC_CNT3_BASE_IDX 0 1179 1180// addressBlock: gc_ea_pwrdec 1181// base address: 0x3c000 1182#define regGCEA_CGTT_CLK_CTRL 0x50c4 1183#define regGCEA_CGTT_CLK_CTRL_BASE_IDX 1 1184 1185 1186// addressBlock: gc_gccacdec 1187// base address: 0xca10 1188#define regGC_CAC_CTRL_1 0x1284 1189#define regGC_CAC_CTRL_1_BASE_IDX 0 1190#define regGC_CAC_CTRL_2 0x1285 1191#define regGC_CAC_CTRL_2_BASE_IDX 0 1192#define regGC_CAC_INDEX_AUTO_INCR_EN 0x1286 1193#define regGC_CAC_INDEX_AUTO_INCR_EN_BASE_IDX 0 1194#define regGC_CAC_AGGR_LOWER 0x1287 1195#define regGC_CAC_AGGR_LOWER_BASE_IDX 0 1196#define regGC_CAC_AGGR_UPPER 0x1288 1197#define regGC_CAC_AGGR_UPPER_BASE_IDX 0 1198#define regGC_EDC_PERF_COUNTER 0x1289 1199#define regGC_EDC_PERF_COUNTER_BASE_IDX 0 1200#define regPCC_PERF_COUNTER 0x128a 1201#define regPCC_PERF_COUNTER_BASE_IDX 0 1202#define regGC_CAC_SOFT_CTRL 0x128d 1203#define regGC_CAC_SOFT_CTRL_BASE_IDX 0 1204#define regGC_DIDT_CTRL0 0x128e 1205#define regGC_DIDT_CTRL0_BASE_IDX 0 1206#define regGC_DIDT_CTRL1 0x128f 1207#define regGC_DIDT_CTRL1_BASE_IDX 0 1208#define regGC_DIDT_CTRL2 0x1290 1209#define regGC_DIDT_CTRL2_BASE_IDX 0 1210#define regGC_DIDT_WEIGHT 0x1291 1211#define regGC_DIDT_WEIGHT_BASE_IDX 0 1212#define regGC_THROTTLE_CTRL1 0x1292 1213#define regGC_THROTTLE_CTRL1_BASE_IDX 0 1214#define regGC_EDC_CTRL 0x1293 1215#define regGC_EDC_CTRL_BASE_IDX 0 1216#define regGC_EDC_THRESHOLD 0x1294 1217#define regGC_EDC_THRESHOLD_BASE_IDX 0 1218#define regGC_EDC_STATUS 0x1295 1219#define regGC_EDC_STATUS_BASE_IDX 0 1220#define regGC_EDC_OVERFLOW 0x1296 1221#define regGC_EDC_OVERFLOW_BASE_IDX 0 1222#define regGC_EDC_ROLLING_POWER_DELTA 0x1297 1223#define regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0 1224#define regGC_EDC_CTRL1 0x1298 1225#define regGC_EDC_CTRL1_BASE_IDX 0 1226#define regGC_THROTTLE_CTRL2 0x1299 1227#define regGC_THROTTLE_CTRL2_BASE_IDX 0 1228#define regPWRBRK_PERF_COUNTER 0x129a 1229#define regPWRBRK_PERF_COUNTER_BASE_IDX 0 1230#define regGC_THROTTLE_CTRL 0x129b 1231#define regGC_THROTTLE_CTRL_BASE_IDX 0 1232#define regGC_CAC_IND_INDEX 0x129c 1233#define regGC_CAC_IND_INDEX_BASE_IDX 0 1234#define regGC_CAC_IND_DATA 0x129d 1235#define regGC_CAC_IND_DATA_BASE_IDX 0 1236#define regSE_CAC_IND_INDEX 0x129e 1237#define regSE_CAC_IND_INDEX_BASE_IDX 0 1238#define regSE_CAC_IND_DATA 0x129f 1239#define regSE_CAC_IND_DATA_BASE_IDX 0 1240 1241 1242// addressBlock: gc_gdsdec 1243// base address: 0x9700 1244#define regGDS_CONFIG 0x05c0 1245#define regGDS_CONFIG_BASE_IDX 0 1246#define regGDS_CNTL_STATUS 0x05c1 1247#define regGDS_CNTL_STATUS_BASE_IDX 0 1248#define regGDS_ENHANCE2 0x05c2 1249#define regGDS_ENHANCE2_BASE_IDX 0 1250#define regGDS_PROTECTION_FAULT 0x05c3 1251#define regGDS_PROTECTION_FAULT_BASE_IDX 0 1252#define regGDS_VM_PROTECTION_FAULT 0x05c4 1253#define regGDS_VM_PROTECTION_FAULT_BASE_IDX 0 1254#define regGDS_EDC_CNT 0x05c5 1255#define regGDS_EDC_CNT_BASE_IDX 0 1256#define regGDS_EDC_GRBM_CNT 0x05c6 1257#define regGDS_EDC_GRBM_CNT_BASE_IDX 0 1258#define regGDS_EDC_OA_DED 0x05c7 1259#define regGDS_EDC_OA_DED_BASE_IDX 0 1260#define regGDS_DSM_CNTL 0x05ca 1261#define regGDS_DSM_CNTL_BASE_IDX 0 1262#define regGDS_EDC_OA_PHY_CNT 0x05cb 1263#define regGDS_EDC_OA_PHY_CNT_BASE_IDX 0 1264#define regGDS_EDC_OA_PIPE_CNT 0x05cc 1265#define regGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 1266#define regGDS_DSM_CNTL2 0x05cd 1267#define regGDS_DSM_CNTL2_BASE_IDX 0 1268#define regGDS_WD_GDS_CSB 0x05ce 1269#define regGDS_WD_GDS_CSB_BASE_IDX 0 1270 1271 1272// addressBlock: gc_gdspdec 1273// base address: 0xcc00 1274#define regGDS_VMID0_BASE 0x1300 1275#define regGDS_VMID0_BASE_BASE_IDX 0 1276#define regGDS_VMID0_SIZE 0x1301 1277#define regGDS_VMID0_SIZE_BASE_IDX 0 1278#define regGDS_VMID1_BASE 0x1302 1279#define regGDS_VMID1_BASE_BASE_IDX 0 1280#define regGDS_VMID1_SIZE 0x1303 1281#define regGDS_VMID1_SIZE_BASE_IDX 0 1282#define regGDS_VMID2_BASE 0x1304 1283#define regGDS_VMID2_BASE_BASE_IDX 0 1284#define regGDS_VMID2_SIZE 0x1305 1285#define regGDS_VMID2_SIZE_BASE_IDX 0 1286#define regGDS_VMID3_BASE 0x1306 1287#define regGDS_VMID3_BASE_BASE_IDX 0 1288#define regGDS_VMID3_SIZE 0x1307 1289#define regGDS_VMID3_SIZE_BASE_IDX 0 1290#define regGDS_VMID4_BASE 0x1308 1291#define regGDS_VMID4_BASE_BASE_IDX 0 1292#define regGDS_VMID4_SIZE 0x1309 1293#define regGDS_VMID4_SIZE_BASE_IDX 0 1294#define regGDS_VMID5_BASE 0x130a 1295#define regGDS_VMID5_BASE_BASE_IDX 0 1296#define regGDS_VMID5_SIZE 0x130b 1297#define regGDS_VMID5_SIZE_BASE_IDX 0 1298#define regGDS_VMID6_BASE 0x130c 1299#define regGDS_VMID6_BASE_BASE_IDX 0 1300#define regGDS_VMID6_SIZE 0x130d 1301#define regGDS_VMID6_SIZE_BASE_IDX 0 1302#define regGDS_VMID7_BASE 0x130e 1303#define regGDS_VMID7_BASE_BASE_IDX 0 1304#define regGDS_VMID7_SIZE 0x130f 1305#define regGDS_VMID7_SIZE_BASE_IDX 0 1306#define regGDS_VMID8_BASE 0x1310 1307#define regGDS_VMID8_BASE_BASE_IDX 0 1308#define regGDS_VMID8_SIZE 0x1311 1309#define regGDS_VMID8_SIZE_BASE_IDX 0 1310#define regGDS_VMID9_BASE 0x1312 1311#define regGDS_VMID9_BASE_BASE_IDX 0 1312#define regGDS_VMID9_SIZE 0x1313 1313#define regGDS_VMID9_SIZE_BASE_IDX 0 1314#define regGDS_VMID10_BASE 0x1314 1315#define regGDS_VMID10_BASE_BASE_IDX 0 1316#define regGDS_VMID10_SIZE 0x1315 1317#define regGDS_VMID10_SIZE_BASE_IDX 0 1318#define regGDS_VMID11_BASE 0x1316 1319#define regGDS_VMID11_BASE_BASE_IDX 0 1320#define regGDS_VMID11_SIZE 0x1317 1321#define regGDS_VMID11_SIZE_BASE_IDX 0 1322#define regGDS_VMID12_BASE 0x1318 1323#define regGDS_VMID12_BASE_BASE_IDX 0 1324#define regGDS_VMID12_SIZE 0x1319 1325#define regGDS_VMID12_SIZE_BASE_IDX 0 1326#define regGDS_VMID13_BASE 0x131a 1327#define regGDS_VMID13_BASE_BASE_IDX 0 1328#define regGDS_VMID13_SIZE 0x131b 1329#define regGDS_VMID13_SIZE_BASE_IDX 0 1330#define regGDS_VMID14_BASE 0x131c 1331#define regGDS_VMID14_BASE_BASE_IDX 0 1332#define regGDS_VMID14_SIZE 0x131d 1333#define regGDS_VMID14_SIZE_BASE_IDX 0 1334#define regGDS_VMID15_BASE 0x131e 1335#define regGDS_VMID15_BASE_BASE_IDX 0 1336#define regGDS_VMID15_SIZE 0x131f 1337#define regGDS_VMID15_SIZE_BASE_IDX 0 1338#define regGDS_GWS_VMID0 0x1320 1339#define regGDS_GWS_VMID0_BASE_IDX 0 1340#define regGDS_GWS_VMID1 0x1321 1341#define regGDS_GWS_VMID1_BASE_IDX 0 1342#define regGDS_GWS_VMID2 0x1322 1343#define regGDS_GWS_VMID2_BASE_IDX 0 1344#define regGDS_GWS_VMID3 0x1323 1345#define regGDS_GWS_VMID3_BASE_IDX 0 1346#define regGDS_GWS_VMID4 0x1324 1347#define regGDS_GWS_VMID4_BASE_IDX 0 1348#define regGDS_GWS_VMID5 0x1325 1349#define regGDS_GWS_VMID5_BASE_IDX 0 1350#define regGDS_GWS_VMID6 0x1326 1351#define regGDS_GWS_VMID6_BASE_IDX 0 1352#define regGDS_GWS_VMID7 0x1327 1353#define regGDS_GWS_VMID7_BASE_IDX 0 1354#define regGDS_GWS_VMID8 0x1328 1355#define regGDS_GWS_VMID8_BASE_IDX 0 1356#define regGDS_GWS_VMID9 0x1329 1357#define regGDS_GWS_VMID9_BASE_IDX 0 1358#define regGDS_GWS_VMID10 0x132a 1359#define regGDS_GWS_VMID10_BASE_IDX 0 1360#define regGDS_GWS_VMID11 0x132b 1361#define regGDS_GWS_VMID11_BASE_IDX 0 1362#define regGDS_GWS_VMID12 0x132c 1363#define regGDS_GWS_VMID12_BASE_IDX 0 1364#define regGDS_GWS_VMID13 0x132d 1365#define regGDS_GWS_VMID13_BASE_IDX 0 1366#define regGDS_GWS_VMID14 0x132e 1367#define regGDS_GWS_VMID14_BASE_IDX 0 1368#define regGDS_GWS_VMID15 0x132f 1369#define regGDS_GWS_VMID15_BASE_IDX 0 1370#define regGDS_OA_VMID0 0x1330 1371#define regGDS_OA_VMID0_BASE_IDX 0 1372#define regGDS_OA_VMID1 0x1331 1373#define regGDS_OA_VMID1_BASE_IDX 0 1374#define regGDS_OA_VMID2 0x1332 1375#define regGDS_OA_VMID2_BASE_IDX 0 1376#define regGDS_OA_VMID3 0x1333 1377#define regGDS_OA_VMID3_BASE_IDX 0 1378#define regGDS_OA_VMID4 0x1334 1379#define regGDS_OA_VMID4_BASE_IDX 0 1380#define regGDS_OA_VMID5 0x1335 1381#define regGDS_OA_VMID5_BASE_IDX 0 1382#define regGDS_OA_VMID6 0x1336 1383#define regGDS_OA_VMID6_BASE_IDX 0 1384#define regGDS_OA_VMID7 0x1337 1385#define regGDS_OA_VMID7_BASE_IDX 0 1386#define regGDS_OA_VMID8 0x1338 1387#define regGDS_OA_VMID8_BASE_IDX 0 1388#define regGDS_OA_VMID9 0x1339 1389#define regGDS_OA_VMID9_BASE_IDX 0 1390#define regGDS_OA_VMID10 0x133a 1391#define regGDS_OA_VMID10_BASE_IDX 0 1392#define regGDS_OA_VMID11 0x133b 1393#define regGDS_OA_VMID11_BASE_IDX 0 1394#define regGDS_OA_VMID12 0x133c 1395#define regGDS_OA_VMID12_BASE_IDX 0 1396#define regGDS_OA_VMID13 0x133d 1397#define regGDS_OA_VMID13_BASE_IDX 0 1398#define regGDS_OA_VMID14 0x133e 1399#define regGDS_OA_VMID14_BASE_IDX 0 1400#define regGDS_OA_VMID15 0x133f 1401#define regGDS_OA_VMID15_BASE_IDX 0 1402#define regGDS_GWS_RESET0 0x1344 1403#define regGDS_GWS_RESET0_BASE_IDX 0 1404#define regGDS_GWS_RESET1 0x1345 1405#define regGDS_GWS_RESET1_BASE_IDX 0 1406#define regGDS_GWS_RESOURCE_RESET 0x1346 1407#define regGDS_GWS_RESOURCE_RESET_BASE_IDX 0 1408#define regGDS_COMPUTE_MAX_WAVE_ID 0x1348 1409#define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 1410#define regGDS_OA_RESET_MASK 0x1349 1411#define regGDS_OA_RESET_MASK_BASE_IDX 0 1412#define regGDS_OA_RESET 0x134a 1413#define regGDS_OA_RESET_BASE_IDX 0 1414#define regGDS_ENHANCE 0x134b 1415#define regGDS_ENHANCE_BASE_IDX 0 1416#define regGDS_OA_CGPG_RESTORE 0x134c 1417#define regGDS_OA_CGPG_RESTORE_BASE_IDX 0 1418#define regGDS_CS_CTXSW_STATUS 0x134d 1419#define regGDS_CS_CTXSW_STATUS_BASE_IDX 0 1420#define regGDS_CS_CTXSW_CNT0 0x134e 1421#define regGDS_CS_CTXSW_CNT0_BASE_IDX 0 1422#define regGDS_CS_CTXSW_CNT1 0x134f 1423#define regGDS_CS_CTXSW_CNT1_BASE_IDX 0 1424#define regGDS_CS_CTXSW_CNT2 0x1350 1425#define regGDS_CS_CTXSW_CNT2_BASE_IDX 0 1426#define regGDS_CS_CTXSW_CNT3 0x1351 1427#define regGDS_CS_CTXSW_CNT3_BASE_IDX 0 1428#define regGDS_GFX_CTXSW_STATUS 0x1352 1429#define regGDS_GFX_CTXSW_STATUS_BASE_IDX 0 1430#define regGDS_VS_CTXSW_CNT0 0x1353 1431#define regGDS_VS_CTXSW_CNT0_BASE_IDX 0 1432#define regGDS_VS_CTXSW_CNT1 0x1354 1433#define regGDS_VS_CTXSW_CNT1_BASE_IDX 0 1434#define regGDS_VS_CTXSW_CNT2 0x1355 1435#define regGDS_VS_CTXSW_CNT2_BASE_IDX 0 1436#define regGDS_VS_CTXSW_CNT3 0x1356 1437#define regGDS_VS_CTXSW_CNT3_BASE_IDX 0 1438#define regGDS_PS0_CTXSW_CNT0 0x1357 1439#define regGDS_PS0_CTXSW_CNT0_BASE_IDX 0 1440#define regGDS_PS0_CTXSW_CNT1 0x1358 1441#define regGDS_PS0_CTXSW_CNT1_BASE_IDX 0 1442#define regGDS_PS0_CTXSW_CNT2 0x1359 1443#define regGDS_PS0_CTXSW_CNT2_BASE_IDX 0 1444#define regGDS_PS0_CTXSW_CNT3 0x135a 1445#define regGDS_PS0_CTXSW_CNT3_BASE_IDX 0 1446#define regGDS_PS1_CTXSW_CNT0 0x135b 1447#define regGDS_PS1_CTXSW_CNT0_BASE_IDX 0 1448#define regGDS_PS1_CTXSW_CNT1 0x135c 1449#define regGDS_PS1_CTXSW_CNT1_BASE_IDX 0 1450#define regGDS_PS1_CTXSW_CNT2 0x135d 1451#define regGDS_PS1_CTXSW_CNT2_BASE_IDX 0 1452#define regGDS_PS1_CTXSW_CNT3 0x135e 1453#define regGDS_PS1_CTXSW_CNT3_BASE_IDX 0 1454#define regGDS_PS2_CTXSW_CNT0 0x135f 1455#define regGDS_PS2_CTXSW_CNT0_BASE_IDX 0 1456#define regGDS_PS2_CTXSW_CNT1 0x1360 1457#define regGDS_PS2_CTXSW_CNT1_BASE_IDX 0 1458#define regGDS_PS2_CTXSW_CNT2 0x1361 1459#define regGDS_PS2_CTXSW_CNT2_BASE_IDX 0 1460#define regGDS_PS2_CTXSW_CNT3 0x1362 1461#define regGDS_PS2_CTXSW_CNT3_BASE_IDX 0 1462#define regGDS_PS3_CTXSW_CNT0 0x1363 1463#define regGDS_PS3_CTXSW_CNT0_BASE_IDX 0 1464#define regGDS_PS3_CTXSW_CNT1 0x1364 1465#define regGDS_PS3_CTXSW_CNT1_BASE_IDX 0 1466#define regGDS_PS3_CTXSW_CNT2 0x1365 1467#define regGDS_PS3_CTXSW_CNT2_BASE_IDX 0 1468#define regGDS_PS3_CTXSW_CNT3 0x1366 1469#define regGDS_PS3_CTXSW_CNT3_BASE_IDX 0 1470#define regGDS_PS4_CTXSW_CNT0 0x1367 1471#define regGDS_PS4_CTXSW_CNT0_BASE_IDX 0 1472#define regGDS_PS4_CTXSW_CNT1 0x1368 1473#define regGDS_PS4_CTXSW_CNT1_BASE_IDX 0 1474#define regGDS_PS4_CTXSW_CNT2 0x1369 1475#define regGDS_PS4_CTXSW_CNT2_BASE_IDX 0 1476#define regGDS_PS4_CTXSW_CNT3 0x136a 1477#define regGDS_PS4_CTXSW_CNT3_BASE_IDX 0 1478#define regGDS_PS5_CTXSW_CNT0 0x136b 1479#define regGDS_PS5_CTXSW_CNT0_BASE_IDX 0 1480#define regGDS_PS5_CTXSW_CNT1 0x136c 1481#define regGDS_PS5_CTXSW_CNT1_BASE_IDX 0 1482#define regGDS_PS5_CTXSW_CNT2 0x136d 1483#define regGDS_PS5_CTXSW_CNT2_BASE_IDX 0 1484#define regGDS_PS5_CTXSW_CNT3 0x136e 1485#define regGDS_PS5_CTXSW_CNT3_BASE_IDX 0 1486#define regGDS_PS6_CTXSW_CNT0 0x136f 1487#define regGDS_PS6_CTXSW_CNT0_BASE_IDX 0 1488#define regGDS_PS6_CTXSW_CNT1 0x1370 1489#define regGDS_PS6_CTXSW_CNT1_BASE_IDX 0 1490#define regGDS_PS6_CTXSW_CNT2 0x1371 1491#define regGDS_PS6_CTXSW_CNT2_BASE_IDX 0 1492#define regGDS_PS6_CTXSW_CNT3 0x1372 1493#define regGDS_PS6_CTXSW_CNT3_BASE_IDX 0 1494#define regGDS_PS7_CTXSW_CNT0 0x1373 1495#define regGDS_PS7_CTXSW_CNT0_BASE_IDX 0 1496#define regGDS_PS7_CTXSW_CNT1 0x1374 1497#define regGDS_PS7_CTXSW_CNT1_BASE_IDX 0 1498#define regGDS_PS7_CTXSW_CNT2 0x1375 1499#define regGDS_PS7_CTXSW_CNT2_BASE_IDX 0 1500#define regGDS_PS7_CTXSW_CNT3 0x1376 1501#define regGDS_PS7_CTXSW_CNT3_BASE_IDX 0 1502#define regGDS_GS_CTXSW_CNT0 0x1377 1503#define regGDS_GS_CTXSW_CNT0_BASE_IDX 0 1504#define regGDS_GS_CTXSW_CNT1 0x1378 1505#define regGDS_GS_CTXSW_CNT1_BASE_IDX 0 1506#define regGDS_GS_CTXSW_CNT2 0x1379 1507#define regGDS_GS_CTXSW_CNT2_BASE_IDX 0 1508#define regGDS_GS_CTXSW_CNT3 0x137a 1509#define regGDS_GS_CTXSW_CNT3_BASE_IDX 0 1510 1511 1512// addressBlock: gc_gfxdec0 1513// base address: 0x28000 1514#define regDB_RENDER_CONTROL 0x0000 1515#define regDB_RENDER_CONTROL_BASE_IDX 1 1516#define regDB_COUNT_CONTROL 0x0001 1517#define regDB_COUNT_CONTROL_BASE_IDX 1 1518#define regDB_DEPTH_VIEW 0x0002 1519#define regDB_DEPTH_VIEW_BASE_IDX 1 1520#define regDB_RENDER_OVERRIDE 0x0003 1521#define regDB_RENDER_OVERRIDE_BASE_IDX 1 1522#define regDB_RENDER_OVERRIDE2 0x0004 1523#define regDB_RENDER_OVERRIDE2_BASE_IDX 1 1524#define regDB_HTILE_DATA_BASE 0x0005 1525#define regDB_HTILE_DATA_BASE_BASE_IDX 1 1526#define regDB_HTILE_DATA_BASE_HI 0x0006 1527#define regDB_HTILE_DATA_BASE_HI_BASE_IDX 1 1528#define regDB_DEPTH_SIZE 0x0007 1529#define regDB_DEPTH_SIZE_BASE_IDX 1 1530#define regDB_DEPTH_BOUNDS_MIN 0x0008 1531#define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 1532#define regDB_DEPTH_BOUNDS_MAX 0x0009 1533#define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 1534#define regDB_STENCIL_CLEAR 0x000a 1535#define regDB_STENCIL_CLEAR_BASE_IDX 1 1536#define regDB_DEPTH_CLEAR 0x000b 1537#define regDB_DEPTH_CLEAR_BASE_IDX 1 1538#define regPA_SC_SCREEN_SCISSOR_TL 0x000c 1539#define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 1540#define regPA_SC_SCREEN_SCISSOR_BR 0x000d 1541#define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 1542#define regDB_Z_INFO 0x000e 1543#define regDB_Z_INFO_BASE_IDX 1 1544#define regDB_STENCIL_INFO 0x000f 1545#define regDB_STENCIL_INFO_BASE_IDX 1 1546#define regDB_Z_READ_BASE 0x0010 1547#define regDB_Z_READ_BASE_BASE_IDX 1 1548#define regDB_Z_READ_BASE_HI 0x0011 1549#define regDB_Z_READ_BASE_HI_BASE_IDX 1 1550#define regDB_STENCIL_READ_BASE 0x0012 1551#define regDB_STENCIL_READ_BASE_BASE_IDX 1 1552#define regDB_STENCIL_READ_BASE_HI 0x0013 1553#define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 1554#define regDB_Z_WRITE_BASE 0x0014 1555#define regDB_Z_WRITE_BASE_BASE_IDX 1 1556#define regDB_Z_WRITE_BASE_HI 0x0015 1557#define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 1558#define regDB_STENCIL_WRITE_BASE 0x0016 1559#define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 1560#define regDB_STENCIL_WRITE_BASE_HI 0x0017 1561#define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 1562#define regDB_DFSM_CONTROL 0x0018 1563#define regDB_DFSM_CONTROL_BASE_IDX 1 1564#define regDB_Z_INFO2 0x001a 1565#define regDB_Z_INFO2_BASE_IDX 1 1566#define regDB_STENCIL_INFO2 0x001b 1567#define regDB_STENCIL_INFO2_BASE_IDX 1 1568#define regCOHER_DEST_BASE_HI_0 0x007a 1569#define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 1570#define regCOHER_DEST_BASE_HI_1 0x007b 1571#define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 1572#define regCOHER_DEST_BASE_HI_2 0x007c 1573#define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 1574#define regCOHER_DEST_BASE_HI_3 0x007d 1575#define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 1576#define regCOHER_DEST_BASE_2 0x007e 1577#define regCOHER_DEST_BASE_2_BASE_IDX 1 1578#define regCOHER_DEST_BASE_3 0x007f 1579#define regCOHER_DEST_BASE_3_BASE_IDX 1 1580#define regPA_SC_WINDOW_OFFSET 0x0080 1581#define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 1582#define regPA_SC_WINDOW_SCISSOR_TL 0x0081 1583#define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 1584#define regPA_SC_WINDOW_SCISSOR_BR 0x0082 1585#define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 1586#define regPA_SC_CLIPRECT_RULE 0x0083 1587#define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 1588#define regPA_SC_CLIPRECT_0_TL 0x0084 1589#define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 1590#define regPA_SC_CLIPRECT_0_BR 0x0085 1591#define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 1592#define regPA_SC_CLIPRECT_1_TL 0x0086 1593#define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 1594#define regPA_SC_CLIPRECT_1_BR 0x0087 1595#define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 1596#define regPA_SC_CLIPRECT_2_TL 0x0088 1597#define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 1598#define regPA_SC_CLIPRECT_2_BR 0x0089 1599#define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 1600#define regPA_SC_CLIPRECT_3_TL 0x008a 1601#define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 1602#define regPA_SC_CLIPRECT_3_BR 0x008b 1603#define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 1604#define regPA_SC_EDGERULE 0x008c 1605#define regPA_SC_EDGERULE_BASE_IDX 1 1606#define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d 1607#define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 1608#define regCB_TARGET_MASK 0x008e 1609#define regCB_TARGET_MASK_BASE_IDX 1 1610#define regCB_SHADER_MASK 0x008f 1611#define regCB_SHADER_MASK_BASE_IDX 1 1612#define regPA_SC_GENERIC_SCISSOR_TL 0x0090 1613#define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 1614#define regPA_SC_GENERIC_SCISSOR_BR 0x0091 1615#define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 1616#define regCOHER_DEST_BASE_0 0x0092 1617#define regCOHER_DEST_BASE_0_BASE_IDX 1 1618#define regCOHER_DEST_BASE_1 0x0093 1619#define regCOHER_DEST_BASE_1_BASE_IDX 1 1620#define regPA_SC_VPORT_SCISSOR_0_TL 0x0094 1621#define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 1622#define regPA_SC_VPORT_SCISSOR_0_BR 0x0095 1623#define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 1624#define regPA_SC_VPORT_SCISSOR_1_TL 0x0096 1625#define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 1626#define regPA_SC_VPORT_SCISSOR_1_BR 0x0097 1627#define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 1628#define regPA_SC_VPORT_SCISSOR_2_TL 0x0098 1629#define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 1630#define regPA_SC_VPORT_SCISSOR_2_BR 0x0099 1631#define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 1632#define regPA_SC_VPORT_SCISSOR_3_TL 0x009a 1633#define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 1634#define regPA_SC_VPORT_SCISSOR_3_BR 0x009b 1635#define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 1636#define regPA_SC_VPORT_SCISSOR_4_TL 0x009c 1637#define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 1638#define regPA_SC_VPORT_SCISSOR_4_BR 0x009d 1639#define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 1640#define regPA_SC_VPORT_SCISSOR_5_TL 0x009e 1641#define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 1642#define regPA_SC_VPORT_SCISSOR_5_BR 0x009f 1643#define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 1644#define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0 1645#define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 1646#define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1 1647#define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 1648#define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2 1649#define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 1650#define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3 1651#define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 1652#define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4 1653#define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 1654#define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5 1655#define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 1656#define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6 1657#define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 1658#define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7 1659#define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 1660#define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8 1661#define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 1662#define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9 1663#define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 1664#define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa 1665#define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 1666#define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab 1667#define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 1668#define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac 1669#define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 1670#define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad 1671#define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 1672#define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae 1673#define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 1674#define regPA_SC_VPORT_SCISSOR_13_BR 0x00af 1675#define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 1676#define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0 1677#define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 1678#define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1 1679#define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 1680#define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2 1681#define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 1682#define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3 1683#define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 1684#define regPA_SC_VPORT_ZMIN_0 0x00b4 1685#define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 1686#define regPA_SC_VPORT_ZMAX_0 0x00b5 1687#define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 1688#define regPA_SC_VPORT_ZMIN_1 0x00b6 1689#define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 1690#define regPA_SC_VPORT_ZMAX_1 0x00b7 1691#define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 1692#define regPA_SC_VPORT_ZMIN_2 0x00b8 1693#define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 1694#define regPA_SC_VPORT_ZMAX_2 0x00b9 1695#define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 1696#define regPA_SC_VPORT_ZMIN_3 0x00ba 1697#define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 1698#define regPA_SC_VPORT_ZMAX_3 0x00bb 1699#define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 1700#define regPA_SC_VPORT_ZMIN_4 0x00bc 1701#define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 1702#define regPA_SC_VPORT_ZMAX_4 0x00bd 1703#define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 1704#define regPA_SC_VPORT_ZMIN_5 0x00be 1705#define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 1706#define regPA_SC_VPORT_ZMAX_5 0x00bf 1707#define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 1708#define regPA_SC_VPORT_ZMIN_6 0x00c0 1709#define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 1710#define regPA_SC_VPORT_ZMAX_6 0x00c1 1711#define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 1712#define regPA_SC_VPORT_ZMIN_7 0x00c2 1713#define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 1714#define regPA_SC_VPORT_ZMAX_7 0x00c3 1715#define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 1716#define regPA_SC_VPORT_ZMIN_8 0x00c4 1717#define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 1718#define regPA_SC_VPORT_ZMAX_8 0x00c5 1719#define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 1720#define regPA_SC_VPORT_ZMIN_9 0x00c6 1721#define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 1722#define regPA_SC_VPORT_ZMAX_9 0x00c7 1723#define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 1724#define regPA_SC_VPORT_ZMIN_10 0x00c8 1725#define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 1726#define regPA_SC_VPORT_ZMAX_10 0x00c9 1727#define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 1728#define regPA_SC_VPORT_ZMIN_11 0x00ca 1729#define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 1730#define regPA_SC_VPORT_ZMAX_11 0x00cb 1731#define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 1732#define regPA_SC_VPORT_ZMIN_12 0x00cc 1733#define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 1734#define regPA_SC_VPORT_ZMAX_12 0x00cd 1735#define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 1736#define regPA_SC_VPORT_ZMIN_13 0x00ce 1737#define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 1738#define regPA_SC_VPORT_ZMAX_13 0x00cf 1739#define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 1740#define regPA_SC_VPORT_ZMIN_14 0x00d0 1741#define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 1742#define regPA_SC_VPORT_ZMAX_14 0x00d1 1743#define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 1744#define regPA_SC_VPORT_ZMIN_15 0x00d2 1745#define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 1746#define regPA_SC_VPORT_ZMAX_15 0x00d3 1747#define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 1748#define regPA_SC_RASTER_CONFIG 0x00d4 1749#define regPA_SC_RASTER_CONFIG_BASE_IDX 1 1750#define regPA_SC_RASTER_CONFIG_1 0x00d5 1751#define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 1752#define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 1753#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 1754#define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7 1755#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 1756#define regCP_PERFMON_CNTX_CNTL 0x00d8 1757#define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 1758#define regCP_PIPEID 0x00d9 1759#define regCP_PIPEID_BASE_IDX 1 1760#define regCP_RINGID 0x00d9 1761#define regCP_RINGID_BASE_IDX 1 1762#define regCP_VMID 0x00da 1763#define regCP_VMID_BASE_IDX 1 1764#define regPA_SC_RIGHT_VERT_GRID 0x00e8 1765#define regPA_SC_RIGHT_VERT_GRID_BASE_IDX 1 1766#define regPA_SC_LEFT_VERT_GRID 0x00e9 1767#define regPA_SC_LEFT_VERT_GRID_BASE_IDX 1 1768#define regPA_SC_HORIZ_GRID 0x00ea 1769#define regPA_SC_HORIZ_GRID_BASE_IDX 1 1770#define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 1771#define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 1772#define regCB_BLEND_RED 0x0105 1773#define regCB_BLEND_RED_BASE_IDX 1 1774#define regCB_BLEND_GREEN 0x0106 1775#define regCB_BLEND_GREEN_BASE_IDX 1 1776#define regCB_BLEND_BLUE 0x0107 1777#define regCB_BLEND_BLUE_BASE_IDX 1 1778#define regCB_BLEND_ALPHA 0x0108 1779#define regCB_BLEND_ALPHA_BASE_IDX 1 1780#define regCB_DCC_CONTROL 0x0109 1781#define regCB_DCC_CONTROL_BASE_IDX 1 1782#define regDB_STENCIL_CONTROL 0x010b 1783#define regDB_STENCIL_CONTROL_BASE_IDX 1 1784#define regDB_STENCILREFMASK 0x010c 1785#define regDB_STENCILREFMASK_BASE_IDX 1 1786#define regDB_STENCILREFMASK_BF 0x010d 1787#define regDB_STENCILREFMASK_BF_BASE_IDX 1 1788#define regPA_CL_VPORT_XSCALE 0x010f 1789#define regPA_CL_VPORT_XSCALE_BASE_IDX 1 1790#define regPA_CL_VPORT_XOFFSET 0x0110 1791#define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 1792#define regPA_CL_VPORT_YSCALE 0x0111 1793#define regPA_CL_VPORT_YSCALE_BASE_IDX 1 1794#define regPA_CL_VPORT_YOFFSET 0x0112 1795#define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 1796#define regPA_CL_VPORT_ZSCALE 0x0113 1797#define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 1798#define regPA_CL_VPORT_ZOFFSET 0x0114 1799#define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 1800#define regPA_CL_VPORT_XSCALE_1 0x0115 1801#define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 1802#define regPA_CL_VPORT_XOFFSET_1 0x0116 1803#define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 1804#define regPA_CL_VPORT_YSCALE_1 0x0117 1805#define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 1806#define regPA_CL_VPORT_YOFFSET_1 0x0118 1807#define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 1808#define regPA_CL_VPORT_ZSCALE_1 0x0119 1809#define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 1810#define regPA_CL_VPORT_ZOFFSET_1 0x011a 1811#define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 1812#define regPA_CL_VPORT_XSCALE_2 0x011b 1813#define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 1814#define regPA_CL_VPORT_XOFFSET_2 0x011c 1815#define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 1816#define regPA_CL_VPORT_YSCALE_2 0x011d 1817#define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 1818#define regPA_CL_VPORT_YOFFSET_2 0x011e 1819#define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 1820#define regPA_CL_VPORT_ZSCALE_2 0x011f 1821#define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 1822#define regPA_CL_VPORT_ZOFFSET_2 0x0120 1823#define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 1824#define regPA_CL_VPORT_XSCALE_3 0x0121 1825#define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 1826#define regPA_CL_VPORT_XOFFSET_3 0x0122 1827#define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 1828#define regPA_CL_VPORT_YSCALE_3 0x0123 1829#define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 1830#define regPA_CL_VPORT_YOFFSET_3 0x0124 1831#define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 1832#define regPA_CL_VPORT_ZSCALE_3 0x0125 1833#define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 1834#define regPA_CL_VPORT_ZOFFSET_3 0x0126 1835#define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 1836#define regPA_CL_VPORT_XSCALE_4 0x0127 1837#define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 1838#define regPA_CL_VPORT_XOFFSET_4 0x0128 1839#define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 1840#define regPA_CL_VPORT_YSCALE_4 0x0129 1841#define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 1842#define regPA_CL_VPORT_YOFFSET_4 0x012a 1843#define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 1844#define regPA_CL_VPORT_ZSCALE_4 0x012b 1845#define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 1846#define regPA_CL_VPORT_ZOFFSET_4 0x012c 1847#define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 1848#define regPA_CL_VPORT_XSCALE_5 0x012d 1849#define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 1850#define regPA_CL_VPORT_XOFFSET_5 0x012e 1851#define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 1852#define regPA_CL_VPORT_YSCALE_5 0x012f 1853#define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 1854#define regPA_CL_VPORT_YOFFSET_5 0x0130 1855#define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 1856#define regPA_CL_VPORT_ZSCALE_5 0x0131 1857#define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 1858#define regPA_CL_VPORT_ZOFFSET_5 0x0132 1859#define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 1860#define regPA_CL_VPORT_XSCALE_6 0x0133 1861#define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 1862#define regPA_CL_VPORT_XOFFSET_6 0x0134 1863#define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 1864#define regPA_CL_VPORT_YSCALE_6 0x0135 1865#define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 1866#define regPA_CL_VPORT_YOFFSET_6 0x0136 1867#define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 1868#define regPA_CL_VPORT_ZSCALE_6 0x0137 1869#define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 1870#define regPA_CL_VPORT_ZOFFSET_6 0x0138 1871#define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 1872#define regPA_CL_VPORT_XSCALE_7 0x0139 1873#define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 1874#define regPA_CL_VPORT_XOFFSET_7 0x013a 1875#define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 1876#define regPA_CL_VPORT_YSCALE_7 0x013b 1877#define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 1878#define regPA_CL_VPORT_YOFFSET_7 0x013c 1879#define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 1880#define regPA_CL_VPORT_ZSCALE_7 0x013d 1881#define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 1882#define regPA_CL_VPORT_ZOFFSET_7 0x013e 1883#define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 1884#define regPA_CL_VPORT_XSCALE_8 0x013f 1885#define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 1886#define regPA_CL_VPORT_XOFFSET_8 0x0140 1887#define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 1888#define regPA_CL_VPORT_YSCALE_8 0x0141 1889#define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 1890#define regPA_CL_VPORT_YOFFSET_8 0x0142 1891#define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 1892#define regPA_CL_VPORT_ZSCALE_8 0x0143 1893#define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 1894#define regPA_CL_VPORT_ZOFFSET_8 0x0144 1895#define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 1896#define regPA_CL_VPORT_XSCALE_9 0x0145 1897#define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 1898#define regPA_CL_VPORT_XOFFSET_9 0x0146 1899#define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 1900#define regPA_CL_VPORT_YSCALE_9 0x0147 1901#define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 1902#define regPA_CL_VPORT_YOFFSET_9 0x0148 1903#define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 1904#define regPA_CL_VPORT_ZSCALE_9 0x0149 1905#define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 1906#define regPA_CL_VPORT_ZOFFSET_9 0x014a 1907#define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 1908#define regPA_CL_VPORT_XSCALE_10 0x014b 1909#define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 1910#define regPA_CL_VPORT_XOFFSET_10 0x014c 1911#define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 1912#define regPA_CL_VPORT_YSCALE_10 0x014d 1913#define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 1914#define regPA_CL_VPORT_YOFFSET_10 0x014e 1915#define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 1916#define regPA_CL_VPORT_ZSCALE_10 0x014f 1917#define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 1918#define regPA_CL_VPORT_ZOFFSET_10 0x0150 1919#define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 1920#define regPA_CL_VPORT_XSCALE_11 0x0151 1921#define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 1922#define regPA_CL_VPORT_XOFFSET_11 0x0152 1923#define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 1924#define regPA_CL_VPORT_YSCALE_11 0x0153 1925#define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 1926#define regPA_CL_VPORT_YOFFSET_11 0x0154 1927#define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 1928#define regPA_CL_VPORT_ZSCALE_11 0x0155 1929#define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 1930#define regPA_CL_VPORT_ZOFFSET_11 0x0156 1931#define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 1932#define regPA_CL_VPORT_XSCALE_12 0x0157 1933#define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 1934#define regPA_CL_VPORT_XOFFSET_12 0x0158 1935#define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 1936#define regPA_CL_VPORT_YSCALE_12 0x0159 1937#define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 1938#define regPA_CL_VPORT_YOFFSET_12 0x015a 1939#define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 1940#define regPA_CL_VPORT_ZSCALE_12 0x015b 1941#define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 1942#define regPA_CL_VPORT_ZOFFSET_12 0x015c 1943#define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 1944#define regPA_CL_VPORT_XSCALE_13 0x015d 1945#define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 1946#define regPA_CL_VPORT_XOFFSET_13 0x015e 1947#define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 1948#define regPA_CL_VPORT_YSCALE_13 0x015f 1949#define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 1950#define regPA_CL_VPORT_YOFFSET_13 0x0160 1951#define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 1952#define regPA_CL_VPORT_ZSCALE_13 0x0161 1953#define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 1954#define regPA_CL_VPORT_ZOFFSET_13 0x0162 1955#define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 1956#define regPA_CL_VPORT_XSCALE_14 0x0163 1957#define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 1958#define regPA_CL_VPORT_XOFFSET_14 0x0164 1959#define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 1960#define regPA_CL_VPORT_YSCALE_14 0x0165 1961#define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 1962#define regPA_CL_VPORT_YOFFSET_14 0x0166 1963#define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 1964#define regPA_CL_VPORT_ZSCALE_14 0x0167 1965#define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 1966#define regPA_CL_VPORT_ZOFFSET_14 0x0168 1967#define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 1968#define regPA_CL_VPORT_XSCALE_15 0x0169 1969#define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 1970#define regPA_CL_VPORT_XOFFSET_15 0x016a 1971#define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 1972#define regPA_CL_VPORT_YSCALE_15 0x016b 1973#define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 1974#define regPA_CL_VPORT_YOFFSET_15 0x016c 1975#define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 1976#define regPA_CL_VPORT_ZSCALE_15 0x016d 1977#define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 1978#define regPA_CL_VPORT_ZOFFSET_15 0x016e 1979#define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 1980#define regPA_CL_UCP_0_X 0x016f 1981#define regPA_CL_UCP_0_X_BASE_IDX 1 1982#define regPA_CL_UCP_0_Y 0x0170 1983#define regPA_CL_UCP_0_Y_BASE_IDX 1 1984#define regPA_CL_UCP_0_Z 0x0171 1985#define regPA_CL_UCP_0_Z_BASE_IDX 1 1986#define regPA_CL_UCP_0_W 0x0172 1987#define regPA_CL_UCP_0_W_BASE_IDX 1 1988#define regPA_CL_UCP_1_X 0x0173 1989#define regPA_CL_UCP_1_X_BASE_IDX 1 1990#define regPA_CL_UCP_1_Y 0x0174 1991#define regPA_CL_UCP_1_Y_BASE_IDX 1 1992#define regPA_CL_UCP_1_Z 0x0175 1993#define regPA_CL_UCP_1_Z_BASE_IDX 1 1994#define regPA_CL_UCP_1_W 0x0176 1995#define regPA_CL_UCP_1_W_BASE_IDX 1 1996#define regPA_CL_UCP_2_X 0x0177 1997#define regPA_CL_UCP_2_X_BASE_IDX 1 1998#define regPA_CL_UCP_2_Y 0x0178 1999#define regPA_CL_UCP_2_Y_BASE_IDX 1 2000#define regPA_CL_UCP_2_Z 0x0179
2001#define regPA_CL_UCP_2_Z_BASE_IDX 1 2002#define regPA_CL_UCP_2_W 0x017a 2003#define regPA_CL_UCP_2_W_BASE_IDX 1 2004#define regPA_CL_UCP_3_X 0x017b 2005#define regPA_CL_UCP_3_X_BASE_IDX 1 2006#define regPA_CL_UCP_3_Y 0x017c 2007#define regPA_CL_UCP_3_Y_BASE_IDX 1 2008#define regPA_CL_UCP_3_Z 0x017d 2009#define regPA_CL_UCP_3_Z_BASE_IDX 1 2010#define regPA_CL_UCP_3_W 0x017e 2011#define regPA_CL_UCP_3_W_BASE_IDX 1 2012#define regPA_CL_UCP_4_X 0x017f 2013#define regPA_CL_UCP_4_X_BASE_IDX 1 2014#define regPA_CL_UCP_4_Y 0x0180 2015#define regPA_CL_UCP_4_Y_BASE_IDX 1 2016#define regPA_CL_UCP_4_Z 0x0181 2017#define regPA_CL_UCP_4_Z_BASE_IDX 1 2018#define regPA_CL_UCP_4_W 0x0182 2019#define regPA_CL_UCP_4_W_BASE_IDX 1 2020#define regPA_CL_UCP_5_X 0x0183 2021#define regPA_CL_UCP_5_X_BASE_IDX 1 2022#define regPA_CL_UCP_5_Y 0x0184 2023#define regPA_CL_UCP_5_Y_BASE_IDX 1 2024#define regPA_CL_UCP_5_Z 0x0185 2025#define regPA_CL_UCP_5_Z_BASE_IDX 1 2026#define regPA_CL_UCP_5_W 0x0186 2027#define regPA_CL_UCP_5_W_BASE_IDX 1 2028#define regPA_CL_PROG_NEAR_CLIP_Z 0x0187 2029#define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 2030#define regSPI_PS_INPUT_CNTL_0 0x0191 2031#define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 2032#define regSPI_PS_INPUT_CNTL_1 0x0192 2033#define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 2034#define regSPI_PS_INPUT_CNTL_2 0x0193 2035#define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 2036#define regSPI_PS_INPUT_CNTL_3 0x0194 2037#define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 2038#define regSPI_PS_INPUT_CNTL_4 0x0195 2039#define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 2040#define regSPI_PS_INPUT_CNTL_5 0x0196 2041#define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 2042#define regSPI_PS_INPUT_CNTL_6 0x0197 2043#define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 2044#define regSPI_PS_INPUT_CNTL_7 0x0198 2045#define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 2046#define regSPI_PS_INPUT_CNTL_8 0x0199 2047#define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 2048#define regSPI_PS_INPUT_CNTL_9 0x019a 2049#define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 2050#define regSPI_PS_INPUT_CNTL_10 0x019b 2051#define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 2052#define regSPI_PS_INPUT_CNTL_11 0x019c 2053#define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 2054#define regSPI_PS_INPUT_CNTL_12 0x019d 2055#define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 2056#define regSPI_PS_INPUT_CNTL_13 0x019e 2057#define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 2058#define regSPI_PS_INPUT_CNTL_14 0x019f 2059#define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 2060#define regSPI_PS_INPUT_CNTL_15 0x01a0 2061#define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 2062#define regSPI_PS_INPUT_CNTL_16 0x01a1 2063#define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 2064#define regSPI_PS_INPUT_CNTL_17 0x01a2 2065#define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 2066#define regSPI_PS_INPUT_CNTL_18 0x01a3 2067#define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 2068#define regSPI_PS_INPUT_CNTL_19 0x01a4 2069#define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 2070#define regSPI_PS_INPUT_CNTL_20 0x01a5 2071#define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 2072#define regSPI_PS_INPUT_CNTL_21 0x01a6 2073#define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 2074#define regSPI_PS_INPUT_CNTL_22 0x01a7 2075#define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 2076#define regSPI_PS_INPUT_CNTL_23 0x01a8 2077#define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 2078#define regSPI_PS_INPUT_CNTL_24 0x01a9 2079#define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 2080#define regSPI_PS_INPUT_CNTL_25 0x01aa 2081#define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 2082#define regSPI_PS_INPUT_CNTL_26 0x01ab 2083#define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 2084#define regSPI_PS_INPUT_CNTL_27 0x01ac 2085#define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 2086#define regSPI_PS_INPUT_CNTL_28 0x01ad 2087#define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 2088#define regSPI_PS_INPUT_CNTL_29 0x01ae 2089#define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 2090#define regSPI_PS_INPUT_CNTL_30 0x01af 2091#define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 2092#define regSPI_PS_INPUT_CNTL_31 0x01b0 2093#define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 2094#define regSPI_VS_OUT_CONFIG 0x01b1 2095#define regSPI_VS_OUT_CONFIG_BASE_IDX 1 2096#define regSPI_PS_INPUT_ENA 0x01b3 2097#define regSPI_PS_INPUT_ENA_BASE_IDX 1 2098#define regSPI_PS_INPUT_ADDR 0x01b4 2099#define regSPI_PS_INPUT_ADDR_BASE_IDX 1 2100#define regSPI_INTERP_CONTROL_0 0x01b5 2101#define regSPI_INTERP_CONTROL_0_BASE_IDX 1 2102#define regSPI_PS_IN_CONTROL 0x01b6 2103#define regSPI_PS_IN_CONTROL_BASE_IDX 1 2104#define regSPI_BARYC_CNTL 0x01b8 2105#define regSPI_BARYC_CNTL_BASE_IDX 1 2106#define regSPI_TMPRING_SIZE 0x01ba 2107#define regSPI_TMPRING_SIZE_BASE_IDX 1 2108#define regSPI_SHADER_POS_FORMAT 0x01c3 2109#define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 2110#define regSPI_SHADER_Z_FORMAT 0x01c4 2111#define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 2112#define regSPI_SHADER_COL_FORMAT 0x01c5 2113#define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 2114#define regSX_PS_DOWNCONVERT 0x01d5 2115#define regSX_PS_DOWNCONVERT_BASE_IDX 1 2116#define regSX_BLEND_OPT_EPSILON 0x01d6 2117#define regSX_BLEND_OPT_EPSILON_BASE_IDX 1 2118#define regSX_BLEND_OPT_CONTROL 0x01d7 2119#define regSX_BLEND_OPT_CONTROL_BASE_IDX 1 2120#define regSX_MRT0_BLEND_OPT 0x01d8 2121#define regSX_MRT0_BLEND_OPT_BASE_IDX 1 2122#define regSX_MRT1_BLEND_OPT 0x01d9 2123#define regSX_MRT1_BLEND_OPT_BASE_IDX 1 2124#define regSX_MRT2_BLEND_OPT 0x01da 2125#define regSX_MRT2_BLEND_OPT_BASE_IDX 1 2126#define regSX_MRT3_BLEND_OPT 0x01db 2127#define regSX_MRT3_BLEND_OPT_BASE_IDX 1 2128#define regSX_MRT4_BLEND_OPT 0x01dc 2129#define regSX_MRT4_BLEND_OPT_BASE_IDX 1 2130#define regSX_MRT5_BLEND_OPT 0x01dd 2131#define regSX_MRT5_BLEND_OPT_BASE_IDX 1 2132#define regSX_MRT6_BLEND_OPT 0x01de 2133#define regSX_MRT6_BLEND_OPT_BASE_IDX 1 2134#define regSX_MRT7_BLEND_OPT 0x01df 2135#define regSX_MRT7_BLEND_OPT_BASE_IDX 1 2136#define regCB_BLEND0_CONTROL 0x01e0 2137#define regCB_BLEND0_CONTROL_BASE_IDX 1 2138#define regCB_BLEND1_CONTROL 0x01e1 2139#define regCB_BLEND1_CONTROL_BASE_IDX 1 2140#define regCB_BLEND2_CONTROL 0x01e2 2141#define regCB_BLEND2_CONTROL_BASE_IDX 1 2142#define regCB_BLEND3_CONTROL 0x01e3 2143#define regCB_BLEND3_CONTROL_BASE_IDX 1 2144#define regCB_BLEND4_CONTROL 0x01e4 2145#define regCB_BLEND4_CONTROL_BASE_IDX 1 2146#define regCB_BLEND5_CONTROL 0x01e5 2147#define regCB_BLEND5_CONTROL_BASE_IDX 1 2148#define regCB_BLEND6_CONTROL 0x01e6 2149#define regCB_BLEND6_CONTROL_BASE_IDX 1 2150#define regCB_BLEND7_CONTROL 0x01e7 2151#define regCB_BLEND7_CONTROL_BASE_IDX 1 2152#define regCB_MRT0_EPITCH 0x01e8 2153#define regCB_MRT0_EPITCH_BASE_IDX 1 2154#define regCB_MRT1_EPITCH 0x01e9 2155#define regCB_MRT1_EPITCH_BASE_IDX 1 2156#define regCB_MRT2_EPITCH 0x01ea 2157#define regCB_MRT2_EPITCH_BASE_IDX 1 2158#define regCB_MRT3_EPITCH 0x01eb 2159#define regCB_MRT3_EPITCH_BASE_IDX 1 2160#define regCB_MRT4_EPITCH 0x01ec 2161#define regCB_MRT4_EPITCH_BASE_IDX 1 2162#define regCB_MRT5_EPITCH 0x01ed 2163#define regCB_MRT5_EPITCH_BASE_IDX 1 2164#define regCB_MRT6_EPITCH 0x01ee 2165#define regCB_MRT6_EPITCH_BASE_IDX 1 2166#define regCB_MRT7_EPITCH 0x01ef 2167#define regCB_MRT7_EPITCH_BASE_IDX 1 2168#define regCS_COPY_STATE 0x01f3 2169#define regCS_COPY_STATE_BASE_IDX 1 2170#define regGFX_COPY_STATE 0x01f4 2171#define regGFX_COPY_STATE_BASE_IDX 1 2172#define regPA_CL_POINT_X_RAD 0x01f5 2173#define regPA_CL_POINT_X_RAD_BASE_IDX 1 2174#define regPA_CL_POINT_Y_RAD 0x01f6 2175#define regPA_CL_POINT_Y_RAD_BASE_IDX 1 2176#define regPA_CL_POINT_SIZE 0x01f7 2177#define regPA_CL_POINT_SIZE_BASE_IDX 1 2178#define regPA_CL_POINT_CULL_RAD 0x01f8 2179#define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 2180#define regVGT_DMA_BASE_HI 0x01f9 2181#define regVGT_DMA_BASE_HI_BASE_IDX 1 2182#define regVGT_DMA_BASE 0x01fa 2183#define regVGT_DMA_BASE_BASE_IDX 1 2184#define regVGT_DRAW_INITIATOR 0x01fc 2185#define regVGT_DRAW_INITIATOR_BASE_IDX 1 2186#define regVGT_IMMED_DATA 0x01fd 2187#define regVGT_IMMED_DATA_BASE_IDX 1 2188#define regVGT_EVENT_ADDRESS_REG 0x01fe 2189#define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 2190#define regDB_DEPTH_CONTROL 0x0200 2191#define regDB_DEPTH_CONTROL_BASE_IDX 1 2192#define regDB_EQAA 0x0201 2193#define regDB_EQAA_BASE_IDX 1 2194#define regCB_COLOR_CONTROL 0x0202 2195#define regCB_COLOR_CONTROL_BASE_IDX 1 2196#define regDB_SHADER_CONTROL 0x0203 2197#define regDB_SHADER_CONTROL_BASE_IDX 1 2198#define regPA_CL_CLIP_CNTL 0x0204 2199#define regPA_CL_CLIP_CNTL_BASE_IDX 1 2200#define regPA_SU_SC_MODE_CNTL 0x0205 2201#define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 2202#define regPA_CL_VTE_CNTL 0x0206 2203#define regPA_CL_VTE_CNTL_BASE_IDX 1 2204#define regPA_CL_VS_OUT_CNTL 0x0207 2205#define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 2206#define regPA_CL_NANINF_CNTL 0x0208 2207#define regPA_CL_NANINF_CNTL_BASE_IDX 1 2208#define regPA_SU_LINE_STIPPLE_CNTL 0x0209 2209#define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 2210#define regPA_SU_LINE_STIPPLE_SCALE 0x020a 2211#define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 2212#define regPA_SU_PRIM_FILTER_CNTL 0x020b 2213#define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 2214#define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c 2215#define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 2216#define regPA_CL_OBJPRIM_ID_CNTL 0x020d 2217#define regPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1 2218#define regPA_CL_NGG_CNTL 0x020e 2219#define regPA_CL_NGG_CNTL_BASE_IDX 1 2220#define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f 2221#define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 2222#define regPA_STEREO_CNTL 0x0210 2223#define regPA_STEREO_CNTL_BASE_IDX 1 2224#define regPA_SU_POINT_SIZE 0x0280 2225#define regPA_SU_POINT_SIZE_BASE_IDX 1 2226#define regPA_SU_POINT_MINMAX 0x0281 2227#define regPA_SU_POINT_MINMAX_BASE_IDX 1 2228#define regPA_SU_LINE_CNTL 0x0282 2229#define regPA_SU_LINE_CNTL_BASE_IDX 1 2230#define regPA_SC_LINE_STIPPLE 0x0283 2231#define regPA_SC_LINE_STIPPLE_BASE_IDX 1 2232#define regVGT_OUTPUT_PATH_CNTL 0x0284 2233#define regVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 2234#define regVGT_HOS_CNTL 0x0285 2235#define regVGT_HOS_CNTL_BASE_IDX 1 2236#define regVGT_HOS_MAX_TESS_LEVEL 0x0286 2237#define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 2238#define regVGT_HOS_MIN_TESS_LEVEL 0x0287 2239#define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 2240#define regVGT_HOS_REUSE_DEPTH 0x0288 2241#define regVGT_HOS_REUSE_DEPTH_BASE_IDX 1 2242#define regVGT_GROUP_PRIM_TYPE 0x0289 2243#define regVGT_GROUP_PRIM_TYPE_BASE_IDX 1 2244#define regVGT_GROUP_FIRST_DECR 0x028a 2245#define regVGT_GROUP_FIRST_DECR_BASE_IDX 1 2246#define regVGT_GROUP_DECR 0x028b 2247#define regVGT_GROUP_DECR_BASE_IDX 1 2248#define regVGT_GROUP_VECT_0_CNTL 0x028c 2249#define regVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 2250#define regVGT_GROUP_VECT_1_CNTL 0x028d 2251#define regVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 2252#define regVGT_GROUP_VECT_0_FMT_CNTL 0x028e 2253#define regVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 2254#define regVGT_GROUP_VECT_1_FMT_CNTL 0x028f 2255#define regVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 2256#define regVGT_GS_MODE 0x0290 2257#define regVGT_GS_MODE_BASE_IDX 1 2258#define regVGT_GS_ONCHIP_CNTL 0x0291 2259#define regVGT_GS_ONCHIP_CNTL_BASE_IDX 1 2260#define regPA_SC_MODE_CNTL_0 0x0292 2261#define regPA_SC_MODE_CNTL_0_BASE_IDX 1 2262#define regPA_SC_MODE_CNTL_1 0x0293 2263#define regPA_SC_MODE_CNTL_1_BASE_IDX 1 2264#define regVGT_ENHANCE 0x0294 2265#define regVGT_ENHANCE_BASE_IDX 1 2266#define regVGT_GS_PER_ES 0x0295 2267#define regVGT_GS_PER_ES_BASE_IDX 1 2268#define regVGT_ES_PER_GS 0x0296 2269#define regVGT_ES_PER_GS_BASE_IDX 1 2270#define regVGT_GS_PER_VS 0x0297 2271#define regVGT_GS_PER_VS_BASE_IDX 1 2272#define regVGT_GSVS_RING_OFFSET_1 0x0298 2273#define regVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 2274#define regVGT_GSVS_RING_OFFSET_2 0x0299 2275#define regVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 2276#define regVGT_GSVS_RING_OFFSET_3 0x029a 2277#define regVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 2278#define regVGT_GS_OUT_PRIM_TYPE 0x029b 2279#define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 2280#define regIA_ENHANCE 0x029c 2281#define regIA_ENHANCE_BASE_IDX 1 2282#define regVGT_DMA_SIZE 0x029d 2283#define regVGT_DMA_SIZE_BASE_IDX 1 2284#define regVGT_DMA_MAX_SIZE 0x029e 2285#define regVGT_DMA_MAX_SIZE_BASE_IDX 1 2286#define regVGT_DMA_INDEX_TYPE 0x029f 2287#define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 2288#define regWD_ENHANCE 0x02a0 2289#define regWD_ENHANCE_BASE_IDX 1 2290#define regVGT_PRIMITIVEID_EN 0x02a1 2291#define regVGT_PRIMITIVEID_EN_BASE_IDX 1 2292#define regVGT_DMA_NUM_INSTANCES 0x02a2 2293#define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 2294#define regVGT_PRIMITIVEID_RESET 0x02a3 2295#define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 2296#define regVGT_EVENT_INITIATOR 0x02a4 2297#define regVGT_EVENT_INITIATOR_BASE_IDX 1 2298#define regVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5 2299#define regVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 2300#define regVGT_DRAW_PAYLOAD_CNTL 0x02a6 2301#define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 2302#define regVGT_INSTANCE_STEP_RATE_0 0x02a8 2303#define regVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 2304#define regVGT_INSTANCE_STEP_RATE_1 0x02a9 2305#define regVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 2306#define regIA_MULTI_VGT_PARAM_BC 0x02aa 2307#define regIA_MULTI_VGT_PARAM_BC_BASE_IDX 1 2308#define regVGT_ESGS_RING_ITEMSIZE 0x02ab 2309#define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 2310#define regVGT_GSVS_RING_ITEMSIZE 0x02ac 2311#define regVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 2312#define regVGT_REUSE_OFF 0x02ad 2313#define regVGT_REUSE_OFF_BASE_IDX 1 2314#define regVGT_VTX_CNT_EN 0x02ae 2315#define regVGT_VTX_CNT_EN_BASE_IDX 1 2316#define regDB_HTILE_SURFACE 0x02af 2317#define regDB_HTILE_SURFACE_BASE_IDX 1 2318#define regDB_SRESULTS_COMPARE_STATE0 0x02b0 2319#define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 2320#define regDB_SRESULTS_COMPARE_STATE1 0x02b1 2321#define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 2322#define regDB_PRELOAD_CONTROL 0x02b2 2323#define regDB_PRELOAD_CONTROL_BASE_IDX 1 2324#define regVGT_STRMOUT_BUFFER_SIZE_0 0x02b4 2325#define regVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 2326#define regVGT_STRMOUT_VTX_STRIDE_0 0x02b5 2327#define regVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 2328#define regVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7 2329#define regVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 2330#define regVGT_STRMOUT_BUFFER_SIZE_1 0x02b8 2331#define regVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 2332#define regVGT_STRMOUT_VTX_STRIDE_1 0x02b9 2333#define regVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 2334#define regVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb 2335#define regVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 2336#define regVGT_STRMOUT_BUFFER_SIZE_2 0x02bc 2337#define regVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 2338#define regVGT_STRMOUT_VTX_STRIDE_2 0x02bd 2339#define regVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 2340#define regVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf 2341#define regVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 2342#define regVGT_STRMOUT_BUFFER_SIZE_3 0x02c0 2343#define regVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 2344#define regVGT_STRMOUT_VTX_STRIDE_3 0x02c1 2345#define regVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 2346#define regVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3 2347#define regVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 2348#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca 2349#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 2350#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb 2351#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 2352#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc 2353#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 2354#define regVGT_GS_MAX_VERT_OUT 0x02ce 2355#define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 2356#define regVGT_TESS_DISTRIBUTION 0x02d4 2357#define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 2358#define regVGT_SHADER_STAGES_EN 0x02d5 2359#define regVGT_SHADER_STAGES_EN_BASE_IDX 1 2360#define regVGT_LS_HS_CONFIG 0x02d6 2361#define regVGT_LS_HS_CONFIG_BASE_IDX 1 2362#define regVGT_GS_VERT_ITEMSIZE 0x02d7 2363#define regVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 2364#define regVGT_GS_VERT_ITEMSIZE_1 0x02d8 2365#define regVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 2366#define regVGT_GS_VERT_ITEMSIZE_2 0x02d9 2367#define regVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 2368#define regVGT_GS_VERT_ITEMSIZE_3 0x02da 2369#define regVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 2370#define regVGT_TF_PARAM 0x02db 2371#define regVGT_TF_PARAM_BASE_IDX 1 2372#define regDB_ALPHA_TO_MASK 0x02dc 2373#define regDB_ALPHA_TO_MASK_BASE_IDX 1 2374#define regVGT_DISPATCH_DRAW_INDEX 0x02dd 2375#define regVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 2376#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de 2377#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 2378#define regPA_SU_POLY_OFFSET_CLAMP 0x02df 2379#define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 2380#define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 2381#define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 2382#define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 2383#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 2384#define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 2385#define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 2386#define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 2387#define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 2388#define regVGT_GS_INSTANCE_CNT 0x02e4 2389#define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 2390#define regVGT_STRMOUT_CONFIG 0x02e5 2391#define regVGT_STRMOUT_CONFIG_BASE_IDX 1 2392#define regVGT_STRMOUT_BUFFER_CONFIG 0x02e6 2393#define regVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 2394#define regVGT_DMA_EVENT_INITIATOR 0x02e7 2395#define regVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 2396#define regPA_SC_CENTROID_PRIORITY_0 0x02f5 2397#define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 2398#define regPA_SC_CENTROID_PRIORITY_1 0x02f6 2399#define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 2400#define regPA_SC_LINE_CNTL 0x02f7 2401#define regPA_SC_LINE_CNTL_BASE_IDX 1 2402#define regPA_SC_AA_CONFIG 0x02f8 2403#define regPA_SC_AA_CONFIG_BASE_IDX 1 2404#define regPA_SU_VTX_CNTL 0x02f9 2405#define regPA_SU_VTX_CNTL_BASE_IDX 1 2406#define regPA_CL_GB_VERT_CLIP_ADJ 0x02fa 2407#define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 2408#define regPA_CL_GB_VERT_DISC_ADJ 0x02fb 2409#define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 2410#define regPA_CL_GB_HORZ_CLIP_ADJ 0x02fc 2411#define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 2412#define regPA_CL_GB_HORZ_DISC_ADJ 0x02fd 2413#define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 2414#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe 2415#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 2416#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff 2417#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 2418#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 2419#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 2420#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 2421#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 2422#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 2423#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 2424#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 2425#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 2426#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 2427#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 2428#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 2429#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 2430#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 2431#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 2432#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 2433#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 2434#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 2435#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 2436#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 2437#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 2438#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a 2439#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 2440#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b 2441#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 2442#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c 2443#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 2444#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d 2445#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 2446#define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e 2447#define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 2448#define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f 2449#define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 2450#define regPA_SC_SHADER_CONTROL 0x0310 2451#define regPA_SC_SHADER_CONTROL_BASE_IDX 1 2452#define regPA_SC_BINNER_CNTL_0 0x0311 2453#define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 2454#define regPA_SC_BINNER_CNTL_1 0x0312 2455#define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 2456#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 2457#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 2458#define regPA_SC_NGG_MODE_CNTL 0x0314 2459#define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 2460#define regVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316 2461#define regVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 2462#define regVGT_OUT_DEALLOC_CNTL 0x0317 2463#define regVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 2464#define regCB_COLOR0_BASE 0x0318 2465#define regCB_COLOR0_BASE_BASE_IDX 1 2466#define regCB_COLOR0_BASE_EXT 0x0319 2467#define regCB_COLOR0_BASE_EXT_BASE_IDX 1 2468#define regCB_COLOR0_ATTRIB2 0x031a 2469#define regCB_COLOR0_ATTRIB2_BASE_IDX 1 2470#define regCB_COLOR0_VIEW 0x031b 2471#define regCB_COLOR0_VIEW_BASE_IDX 1 2472#define regCB_COLOR0_INFO 0x031c 2473#define regCB_COLOR0_INFO_BASE_IDX 1 2474#define regCB_COLOR0_ATTRIB 0x031d 2475#define regCB_COLOR0_ATTRIB_BASE_IDX 1 2476#define regCB_COLOR0_DCC_CONTROL 0x031e 2477#define regCB_COLOR0_DCC_CONTROL_BASE_IDX 1 2478#define regCB_COLOR0_CMASK 0x031f 2479#define regCB_COLOR0_CMASK_BASE_IDX 1 2480#define regCB_COLOR0_CMASK_BASE_EXT 0x0320 2481#define regCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 2482#define regCB_COLOR0_FMASK 0x0321 2483#define regCB_COLOR0_FMASK_BASE_IDX 1 2484#define regCB_COLOR0_FMASK_BASE_EXT 0x0322 2485#define regCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 2486#define regCB_COLOR0_CLEAR_WORD0 0x0323 2487#define regCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 2488#define regCB_COLOR0_CLEAR_WORD1 0x0324 2489#define regCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 2490#define regCB_COLOR0_DCC_BASE 0x0325 2491#define regCB_COLOR0_DCC_BASE_BASE_IDX 1 2492#define regCB_COLOR0_DCC_BASE_EXT 0x0326 2493#define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 2494#define regCB_COLOR1_BASE 0x0327 2495#define regCB_COLOR1_BASE_BASE_IDX 1 2496#define regCB_COLOR1_BASE_EXT 0x0328 2497#define regCB_COLOR1_BASE_EXT_BASE_IDX 1 2498#define regCB_COLOR1_ATTRIB2 0x0329 2499#define regCB_COLOR1_ATTRIB2_BASE_IDX 1 2500#define regCB_COLOR1_VIEW 0x032a 2501#define regCB_COLOR1_VIEW_BASE_IDX 1 2502#define regCB_COLOR1_INFO 0x032b 2503#define regCB_COLOR1_INFO_BASE_IDX 1 2504#define regCB_COLOR1_ATTRIB 0x032c 2505#define regCB_COLOR1_ATTRIB_BASE_IDX 1 2506#define regCB_COLOR1_DCC_CONTROL 0x032d 2507#define regCB_COLOR1_DCC_CONTROL_BASE_IDX 1 2508#define regCB_COLOR1_CMASK 0x032e 2509#define regCB_COLOR1_CMASK_BASE_IDX 1 2510#define regCB_COLOR1_CMASK_BASE_EXT 0x032f 2511#define regCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 2512#define regCB_COLOR1_FMASK 0x0330 2513#define regCB_COLOR1_FMASK_BASE_IDX 1 2514#define regCB_COLOR1_FMASK_BASE_EXT 0x0331 2515#define regCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 2516#define regCB_COLOR1_CLEAR_WORD0 0x0332 2517#define regCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 2518#define regCB_COLOR1_CLEAR_WORD1 0x0333 2519#define regCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 2520#define regCB_COLOR1_DCC_BASE 0x0334 2521#define regCB_COLOR1_DCC_BASE_BASE_IDX 1 2522#define regCB_COLOR1_DCC_BASE_EXT 0x0335 2523#define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 2524#define regCB_COLOR2_BASE 0x0336 2525#define regCB_COLOR2_BASE_BASE_IDX 1 2526#define regCB_COLOR2_BASE_EXT 0x0337 2527#define regCB_COLOR2_BASE_EXT_BASE_IDX 1 2528#define regCB_COLOR2_ATTRIB2 0x0338 2529#define regCB_COLOR2_ATTRIB2_BASE_IDX 1 2530#define regCB_COLOR2_VIEW 0x0339 2531#define regCB_COLOR2_VIEW_BASE_IDX 1 2532#define regCB_COLOR2_INFO 0x033a 2533#define regCB_COLOR2_INFO_BASE_IDX 1 2534#define regCB_COLOR2_ATTRIB 0x033b 2535#define regCB_COLOR2_ATTRIB_BASE_IDX 1 2536#define regCB_COLOR2_DCC_CONTROL 0x033c 2537#define regCB_COLOR2_DCC_CONTROL_BASE_IDX 1 2538#define regCB_COLOR2_CMASK 0x033d 2539#define regCB_COLOR2_CMASK_BASE_IDX 1 2540#define regCB_COLOR2_CMASK_BASE_EXT 0x033e 2541#define regCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 2542#define regCB_COLOR2_FMASK 0x033f 2543#define regCB_COLOR2_FMASK_BASE_IDX 1 2544#define regCB_COLOR2_FMASK_BASE_EXT 0x0340 2545#define regCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 2546#define regCB_COLOR2_CLEAR_WORD0 0x0341 2547#define regCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 2548#define regCB_COLOR2_CLEAR_WORD1 0x0342 2549#define regCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 2550#define regCB_COLOR2_DCC_BASE 0x0343 2551#define regCB_COLOR2_DCC_BASE_BASE_IDX 1 2552#define regCB_COLOR2_DCC_BASE_EXT 0x0344 2553#define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 2554#define regCB_COLOR3_BASE 0x0345 2555#define regCB_COLOR3_BASE_BASE_IDX 1 2556#define regCB_COLOR3_BASE_EXT 0x0346 2557#define regCB_COLOR3_BASE_EXT_BASE_IDX 1 2558#define regCB_COLOR3_ATTRIB2 0x0347 2559#define regCB_COLOR3_ATTRIB2_BASE_IDX 1 2560#define regCB_COLOR3_VIEW 0x0348 2561#define regCB_COLOR3_VIEW_BASE_IDX 1 2562#define regCB_COLOR3_INFO 0x0349 2563#define regCB_COLOR3_INFO_BASE_IDX 1 2564#define regCB_COLOR3_ATTRIB 0x034a 2565#define regCB_COLOR3_ATTRIB_BASE_IDX 1 2566#define regCB_COLOR3_DCC_CONTROL 0x034b 2567#define regCB_COLOR3_DCC_CONTROL_BASE_IDX 1 2568#define regCB_COLOR3_CMASK 0x034c 2569#define regCB_COLOR3_CMASK_BASE_IDX 1 2570#define regCB_COLOR3_CMASK_BASE_EXT 0x034d 2571#define regCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 2572#define regCB_COLOR3_FMASK 0x034e 2573#define regCB_COLOR3_FMASK_BASE_IDX 1 2574#define regCB_COLOR3_FMASK_BASE_EXT 0x034f 2575#define regCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 2576#define regCB_COLOR3_CLEAR_WORD0 0x0350 2577#define regCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 2578#define regCB_COLOR3_CLEAR_WORD1 0x0351 2579#define regCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 2580#define regCB_COLOR3_DCC_BASE 0x0352 2581#define regCB_COLOR3_DCC_BASE_BASE_IDX 1 2582#define regCB_COLOR3_DCC_BASE_EXT 0x0353 2583#define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 2584#define regCB_COLOR4_BASE 0x0354 2585#define regCB_COLOR4_BASE_BASE_IDX 1 2586#define regCB_COLOR4_BASE_EXT 0x0355 2587#define regCB_COLOR4_BASE_EXT_BASE_IDX 1 2588#define regCB_COLOR4_ATTRIB2 0x0356 2589#define regCB_COLOR4_ATTRIB2_BASE_IDX 1 2590#define regCB_COLOR4_VIEW 0x0357 2591#define regCB_COLOR4_VIEW_BASE_IDX 1 2592#define regCB_COLOR4_INFO 0x0358 2593#define regCB_COLOR4_INFO_BASE_IDX 1 2594#define regCB_COLOR4_ATTRIB 0x0359 2595#define regCB_COLOR4_ATTRIB_BASE_IDX 1 2596#define regCB_COLOR4_DCC_CONTROL 0x035a 2597#define regCB_COLOR4_DCC_CONTROL_BASE_IDX 1 2598#define regCB_COLOR4_CMASK 0x035b 2599#define regCB_COLOR4_CMASK_BASE_IDX 1 2600#define regCB_COLOR4_CMASK_BASE_EXT 0x035c 2601#define regCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 2602#define regCB_COLOR4_FMASK 0x035d 2603#define regCB_COLOR4_FMASK_BASE_IDX 1 2604#define regCB_COLOR4_FMASK_BASE_EXT 0x035e 2605#define regCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 2606#define regCB_COLOR4_CLEAR_WORD0 0x035f 2607#define regCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 2608#define regCB_COLOR4_CLEAR_WORD1 0x0360 2609#define regCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 2610#define regCB_COLOR4_DCC_BASE 0x0361 2611#define regCB_COLOR4_DCC_BASE_BASE_IDX 1 2612#define regCB_COLOR4_DCC_BASE_EXT 0x0362 2613#define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 2614#define regCB_COLOR5_BASE 0x0363 2615#define regCB_COLOR5_BASE_BASE_IDX 1 2616#define regCB_COLOR5_BASE_EXT 0x0364 2617#define regCB_COLOR5_BASE_EXT_BASE_IDX 1 2618#define regCB_COLOR5_ATTRIB2 0x0365 2619#define regCB_COLOR5_ATTRIB2_BASE_IDX 1 2620#define regCB_COLOR5_VIEW 0x0366 2621#define regCB_COLOR5_VIEW_BASE_IDX 1 2622#define regCB_COLOR5_INFO 0x0367 2623#define regCB_COLOR5_INFO_BASE_IDX 1 2624#define regCB_COLOR5_ATTRIB 0x0368 2625#define regCB_COLOR5_ATTRIB_BASE_IDX 1 2626#define regCB_COLOR5_DCC_CONTROL 0x0369 2627#define regCB_COLOR5_DCC_CONTROL_BASE_IDX 1 2628#define regCB_COLOR5_CMASK 0x036a 2629#define regCB_COLOR5_CMASK_BASE_IDX 1 2630#define regCB_COLOR5_CMASK_BASE_EXT 0x036b 2631#define regCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 2632#define regCB_COLOR5_FMASK 0x036c 2633#define regCB_COLOR5_FMASK_BASE_IDX 1 2634#define regCB_COLOR5_FMASK_BASE_EXT 0x036d 2635#define regCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 2636#define regCB_COLOR5_CLEAR_WORD0 0x036e 2637#define regCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 2638#define regCB_COLOR5_CLEAR_WORD1 0x036f 2639#define regCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 2640#define regCB_COLOR5_DCC_BASE 0x0370 2641#define regCB_COLOR5_DCC_BASE_BASE_IDX 1 2642#define regCB_COLOR5_DCC_BASE_EXT 0x0371 2643#define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 2644#define regCB_COLOR6_BASE 0x0372 2645#define regCB_COLOR6_BASE_BASE_IDX 1 2646#define regCB_COLOR6_BASE_EXT 0x0373 2647#define regCB_COLOR6_BASE_EXT_BASE_IDX 1 2648#define regCB_COLOR6_ATTRIB2 0x0374 2649#define regCB_COLOR6_ATTRIB2_BASE_IDX 1 2650#define regCB_COLOR6_VIEW 0x0375 2651#define regCB_COLOR6_VIEW_BASE_IDX 1 2652#define regCB_COLOR6_INFO 0x0376 2653#define regCB_COLOR6_INFO_BASE_IDX 1 2654#define regCB_COLOR6_ATTRIB 0x0377 2655#define regCB_COLOR6_ATTRIB_BASE_IDX 1 2656#define regCB_COLOR6_DCC_CONTROL 0x0378 2657#define regCB_COLOR6_DCC_CONTROL_BASE_IDX 1 2658#define regCB_COLOR6_CMASK 0x0379 2659#define regCB_COLOR6_CMASK_BASE_IDX 1 2660#define regCB_COLOR6_CMASK_BASE_EXT 0x037a 2661#define regCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 2662#define regCB_COLOR6_FMASK 0x037b 2663#define regCB_COLOR6_FMASK_BASE_IDX 1 2664#define regCB_COLOR6_FMASK_BASE_EXT 0x037c 2665#define regCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 2666#define regCB_COLOR6_CLEAR_WORD0 0x037d 2667#define regCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 2668#define regCB_COLOR6_CLEAR_WORD1 0x037e 2669#define regCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 2670#define regCB_COLOR6_DCC_BASE 0x037f 2671#define regCB_COLOR6_DCC_BASE_BASE_IDX 1 2672#define regCB_COLOR6_DCC_BASE_EXT 0x0380 2673#define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 2674#define regCB_COLOR7_BASE 0x0381 2675#define regCB_COLOR7_BASE_BASE_IDX 1 2676#define regCB_COLOR7_BASE_EXT 0x0382 2677#define regCB_COLOR7_BASE_EXT_BASE_IDX 1 2678#define regCB_COLOR7_ATTRIB2 0x0383 2679#define regCB_COLOR7_ATTRIB2_BASE_IDX 1 2680#define regCB_COLOR7_VIEW 0x0384 2681#define regCB_COLOR7_VIEW_BASE_IDX 1 2682#define regCB_COLOR7_INFO 0x0385 2683#define regCB_COLOR7_INFO_BASE_IDX 1 2684#define regCB_COLOR7_ATTRIB 0x0386 2685#define regCB_COLOR7_ATTRIB_BASE_IDX 1 2686#define regCB_COLOR7_DCC_CONTROL 0x0387 2687#define regCB_COLOR7_DCC_CONTROL_BASE_IDX 1 2688#define regCB_COLOR7_CMASK 0x0388 2689#define regCB_COLOR7_CMASK_BASE_IDX 1 2690#define regCB_COLOR7_CMASK_BASE_EXT 0x0389 2691#define regCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 2692#define regCB_COLOR7_FMASK 0x038a 2693#define regCB_COLOR7_FMASK_BASE_IDX 1 2694#define regCB_COLOR7_FMASK_BASE_EXT 0x038b 2695#define regCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 2696#define regCB_COLOR7_CLEAR_WORD0 0x038c 2697#define regCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 2698#define regCB_COLOR7_CLEAR_WORD1 0x038d 2699#define regCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 2700#define regCB_COLOR7_DCC_BASE 0x038e 2701#define regCB_COLOR7_DCC_BASE_BASE_IDX 1 2702#define regCB_COLOR7_DCC_BASE_EXT 0x038f 2703#define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 2704 2705 2706// addressBlock: gc_gfxudec 2707// base address: 0x30000 2708#define regCP_EOP_DONE_ADDR_LO 0x2000 2709#define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 2710#define regCP_EOP_DONE_ADDR_HI 0x2001 2711#define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 2712#define regCP_EOP_DONE_DATA_LO 0x2002 2713#define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 2714#define regCP_EOP_DONE_DATA_HI 0x2003 2715#define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 2716#define regCP_EOP_LAST_FENCE_LO 0x2004 2717#define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 2718#define regCP_EOP_LAST_FENCE_HI 0x2005 2719#define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 2720#define regCP_STREAM_OUT_ADDR_LO 0x2006 2721#define regCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 2722#define regCP_STREAM_OUT_ADDR_HI 0x2007 2723#define regCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 2724#define regCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008 2725#define regCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 2726#define regCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009 2727#define regCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 2728#define regCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a 2729#define regCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 2730#define regCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b 2731#define regCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 2732#define regCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c 2733#define regCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 2734#define regCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d 2735#define regCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 2736#define regCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e 2737#define regCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 2738#define regCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f 2739#define regCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 2740#define regCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010 2741#define regCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 2742#define regCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011 2743#define regCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 2744#define regCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012 2745#define regCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 2746#define regCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013 2747#define regCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 2748#define regCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014 2749#define regCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 2750#define regCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015 2751#define regCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 2752#define regCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016 2753#define regCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 2754#define regCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017 2755#define regCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 2756#define regCP_PIPE_STATS_ADDR_LO 0x2018 2757#define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 2758#define regCP_PIPE_STATS_ADDR_HI 0x2019 2759#define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 2760#define regCP_VGT_IAVERT_COUNT_LO 0x201a 2761#define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 2762#define regCP_VGT_IAVERT_COUNT_HI 0x201b 2763#define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 2764#define regCP_VGT_IAPRIM_COUNT_LO 0x201c 2765#define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 2766#define regCP_VGT_IAPRIM_COUNT_HI 0x201d 2767#define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 2768#define regCP_VGT_GSPRIM_COUNT_LO 0x201e 2769#define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 2770#define regCP_VGT_GSPRIM_COUNT_HI 0x201f 2771#define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 2772#define regCP_VGT_VSINVOC_COUNT_LO 0x2020 2773#define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 2774#define regCP_VGT_VSINVOC_COUNT_HI 0x2021 2775#define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 2776#define regCP_VGT_GSINVOC_COUNT_LO 0x2022 2777#define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 2778#define regCP_VGT_GSINVOC_COUNT_HI 0x2023 2779#define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 2780#define regCP_VGT_HSINVOC_COUNT_LO 0x2024 2781#define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 2782#define regCP_VGT_HSINVOC_COUNT_HI 0x2025 2783#define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 2784#define regCP_VGT_DSINVOC_COUNT_LO 0x2026 2785#define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 2786#define regCP_VGT_DSINVOC_COUNT_HI 0x2027 2787#define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 2788#define regCP_PA_CINVOC_COUNT_LO 0x2028 2789#define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 2790#define regCP_PA_CINVOC_COUNT_HI 0x2029 2791#define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 2792#define regCP_PA_CPRIM_COUNT_LO 0x202a 2793#define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 2794#define regCP_PA_CPRIM_COUNT_HI 0x202b 2795#define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 2796#define regCP_SC_PSINVOC_COUNT0_LO 0x202c 2797#define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 2798#define regCP_SC_PSINVOC_COUNT0_HI 0x202d 2799#define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 2800#define regCP_SC_PSINVOC_COUNT1_LO 0x202e 2801#define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 2802#define regCP_SC_PSINVOC_COUNT1_HI 0x202f 2803#define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 2804#define regCP_VGT_CSINVOC_COUNT_LO 0x2030 2805#define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 2806#define regCP_VGT_CSINVOC_COUNT_HI 0x2031 2807#define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 2808#define regCP_PIPE_STATS_CONTROL 0x203d 2809#define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 2810#define regCP_STREAM_OUT_CONTROL 0x203e 2811#define regCP_STREAM_OUT_CONTROL_BASE_IDX 1 2812#define regCP_STRMOUT_CNTL 0x203f 2813#define regCP_STRMOUT_CNTL_BASE_IDX 1 2814#define regSCRATCH_REG0 0x2040 2815#define regSCRATCH_REG0_BASE_IDX 1 2816#define regSCRATCH_REG1 0x2041 2817#define regSCRATCH_REG1_BASE_IDX 1 2818#define regSCRATCH_REG2 0x2042 2819#define regSCRATCH_REG2_BASE_IDX 1 2820#define regSCRATCH_REG3 0x2043 2821#define regSCRATCH_REG3_BASE_IDX 1 2822#define regSCRATCH_REG4 0x2044 2823#define regSCRATCH_REG4_BASE_IDX 1 2824#define regSCRATCH_REG5 0x2045 2825#define regSCRATCH_REG5_BASE_IDX 1 2826#define regSCRATCH_REG6 0x2046 2827#define regSCRATCH_REG6_BASE_IDX 1 2828#define regSCRATCH_REG7 0x2047 2829#define regSCRATCH_REG7_BASE_IDX 1 2830#define regCP_APPEND_DATA_HI 0x204c 2831#define regCP_APPEND_DATA_HI_BASE_IDX 1 2832#define regCP_APPEND_LAST_CS_FENCE_HI 0x204d 2833#define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 2834#define regCP_APPEND_LAST_PS_FENCE_HI 0x204e 2835#define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 2836#define regSCRATCH_UMSK 0x2050 2837#define regSCRATCH_UMSK_BASE_IDX 1 2838#define regSCRATCH_ADDR 0x2051 2839#define regSCRATCH_ADDR_BASE_IDX 1 2840#define regCP_PFP_ATOMIC_PREOP_LO 0x2052 2841#define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 2842#define regCP_PFP_ATOMIC_PREOP_HI 0x2053 2843#define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 2844#define regCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 2845#define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 2846#define regCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 2847#define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 2848#define regCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 2849#define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 2850#define regCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 2851#define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 2852#define regCP_APPEND_ADDR_LO 0x2058 2853#define regCP_APPEND_ADDR_LO_BASE_IDX 1 2854#define regCP_APPEND_ADDR_HI 0x2059 2855#define regCP_APPEND_ADDR_HI_BASE_IDX 1 2856#define regCP_APPEND_DATA_LO 0x205a 2857#define regCP_APPEND_DATA_LO_BASE_IDX 1 2858#define regCP_APPEND_LAST_CS_FENCE_LO 0x205b 2859#define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 2860#define regCP_APPEND_LAST_PS_FENCE_LO 0x205c 2861#define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 2862#define regCP_ATOMIC_PREOP_LO 0x205d 2863#define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 2864#define regCP_ME_ATOMIC_PREOP_LO 0x205d 2865#define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 2866#define regCP_ATOMIC_PREOP_HI 0x205e 2867#define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 2868#define regCP_ME_ATOMIC_PREOP_HI 0x205e 2869#define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 2870#define regCP_GDS_ATOMIC0_PREOP_LO 0x205f 2871#define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 2872#define regCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f 2873#define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 2874#define regCP_GDS_ATOMIC0_PREOP_HI 0x2060 2875#define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 2876#define regCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 2877#define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 2878#define regCP_GDS_ATOMIC1_PREOP_LO 0x2061 2879#define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 2880#define regCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 2881#define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 2882#define regCP_GDS_ATOMIC1_PREOP_HI 0x2062 2883#define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 2884#define regCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 2885#define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 2886#define regCP_ME_MC_WADDR_LO 0x2069 2887#define regCP_ME_MC_WADDR_LO_BASE_IDX 1 2888#define regCP_ME_MC_WADDR_HI 0x206a 2889#define regCP_ME_MC_WADDR_HI_BASE_IDX 1 2890#define regCP_ME_MC_WDATA_LO 0x206b 2891#define regCP_ME_MC_WDATA_LO_BASE_IDX 1 2892#define regCP_ME_MC_WDATA_HI 0x206c 2893#define regCP_ME_MC_WDATA_HI_BASE_IDX 1 2894#define regCP_ME_MC_RADDR_LO 0x206d 2895#define regCP_ME_MC_RADDR_LO_BASE_IDX 1 2896#define regCP_ME_MC_RADDR_HI 0x206e 2897#define regCP_ME_MC_RADDR_HI_BASE_IDX 1 2898#define regCP_SEM_WAIT_TIMER 0x206f 2899#define regCP_SEM_WAIT_TIMER_BASE_IDX 1 2900#define regCP_SIG_SEM_ADDR_LO 0x2070 2901#define regCP_SIG_SEM_ADDR_LO_BASE_IDX 1 2902#define regCP_SIG_SEM_ADDR_HI 0x2071 2903#define regCP_SIG_SEM_ADDR_HI_BASE_IDX 1 2904#define regCP_WAIT_REG_MEM_TIMEOUT 0x2074 2905#define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 2906#define regCP_WAIT_SEM_ADDR_LO 0x2075 2907#define regCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 2908#define regCP_WAIT_SEM_ADDR_HI 0x2076 2909#define regCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 2910#define regCP_DMA_PFP_CONTROL 0x2077 2911#define regCP_DMA_PFP_CONTROL_BASE_IDX 1 2912#define regCP_DMA_ME_CONTROL 0x2078 2913#define regCP_DMA_ME_CONTROL_BASE_IDX 1 2914#define regCP_COHER_BASE_HI 0x2079 2915#define regCP_COHER_BASE_HI_BASE_IDX 1 2916#define regCP_COHER_START_DELAY 0x207b 2917#define regCP_COHER_START_DELAY_BASE_IDX 1 2918#define regCP_COHER_CNTL 0x207c 2919#define regCP_COHER_CNTL_BASE_IDX 1 2920#define regCP_COHER_SIZE 0x207d 2921#define regCP_COHER_SIZE_BASE_IDX 1 2922#define regCP_COHER_BASE 0x207e 2923#define regCP_COHER_BASE_BASE_IDX 1 2924#define regCP_COHER_STATUS 0x207f 2925#define regCP_COHER_STATUS_BASE_IDX 1 2926#define regCP_DMA_ME_SRC_ADDR 0x2080 2927#define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 2928#define regCP_DMA_ME_SRC_ADDR_HI 0x2081 2929#define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 2930#define regCP_DMA_ME_DST_ADDR 0x2082 2931#define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 2932#define regCP_DMA_ME_DST_ADDR_HI 0x2083 2933#define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 2934#define regCP_DMA_ME_COMMAND 0x2084 2935#define regCP_DMA_ME_COMMAND_BASE_IDX 1 2936#define regCP_DMA_PFP_SRC_ADDR 0x2085 2937#define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 2938#define regCP_DMA_PFP_SRC_ADDR_HI 0x2086 2939#define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 2940#define regCP_DMA_PFP_DST_ADDR 0x2087 2941#define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 2942#define regCP_DMA_PFP_DST_ADDR_HI 0x2088 2943#define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 2944#define regCP_DMA_PFP_COMMAND 0x2089 2945#define regCP_DMA_PFP_COMMAND_BASE_IDX 1 2946#define regCP_DMA_CNTL 0x208a 2947#define regCP_DMA_CNTL_BASE_IDX 1 2948#define regCP_DMA_READ_TAGS 0x208b 2949#define regCP_DMA_READ_TAGS_BASE_IDX 1 2950#define regCP_COHER_SIZE_HI 0x208c 2951#define regCP_COHER_SIZE_HI_BASE_IDX 1 2952#define regCP_PFP_IB_CONTROL 0x208d 2953#define regCP_PFP_IB_CONTROL_BASE_IDX 1 2954#define regCP_PFP_LOAD_CONTROL 0x208e 2955#define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 2956#define regCP_SCRATCH_INDEX 0x208f 2957#define regCP_SCRATCH_INDEX_BASE_IDX 1 2958#define regCP_SCRATCH_DATA 0x2090 2959#define regCP_SCRATCH_DATA_BASE_IDX 1 2960#define regCP_RB_OFFSET 0x2091 2961#define regCP_RB_OFFSET_BASE_IDX 1 2962#define regCP_IB2_OFFSET 0x2093 2963#define regCP_IB2_OFFSET_BASE_IDX 1 2964#define regCP_IB2_PREAMBLE_BEGIN 0x2096 2965#define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 2966#define regCP_IB2_PREAMBLE_END 0x2097 2967#define regCP_IB2_PREAMBLE_END_BASE_IDX 1 2968#define regCP_CE_IB1_OFFSET 0x2098 2969#define regCP_CE_IB1_OFFSET_BASE_IDX 1 2970#define regCP_CE_IB2_OFFSET 0x2099 2971#define regCP_CE_IB2_OFFSET_BASE_IDX 1 2972#define regCP_CE_COUNTER 0x209a 2973#define regCP_CE_COUNTER_BASE_IDX 1 2974#define regCP_CE_RB_OFFSET 0x209b 2975#define regCP_CE_RB_OFFSET_BASE_IDX 1 2976#define regCP_CE_INIT_CMD_BUFSZ 0x20bd 2977#define regCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 2978#define regCP_CE_IB1_CMD_BUFSZ 0x20be 2979#define regCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 2980#define regCP_CE_IB2_CMD_BUFSZ 0x20bf 2981#define regCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 2982#define regCP_IB2_CMD_BUFSZ 0x20c1 2983#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 2984#define regCP_ST_CMD_BUFSZ 0x20c2 2985#define regCP_ST_CMD_BUFSZ_BASE_IDX 1 2986#define regCP_CE_INIT_BASE_LO 0x20c3 2987#define regCP_CE_INIT_BASE_LO_BASE_IDX 1 2988#define regCP_CE_INIT_BASE_HI 0x20c4 2989#define regCP_CE_INIT_BASE_HI_BASE_IDX 1 2990#define regCP_CE_INIT_BUFSZ 0x20c5 2991#define regCP_CE_INIT_BUFSZ_BASE_IDX 1 2992#define regCP_CE_IB1_BASE_LO 0x20c6 2993#define regCP_CE_IB1_BASE_LO_BASE_IDX 1 2994#define regCP_CE_IB1_BASE_HI 0x20c7 2995#define regCP_CE_IB1_BASE_HI_BASE_IDX 1 2996#define regCP_CE_IB1_BUFSZ 0x20c8 2997#define regCP_CE_IB1_BUFSZ_BASE_IDX 1 2998#define regCP_CE_IB2_BASE_LO 0x20c9 2999#define regCP_CE_IB2_BASE_LO_BASE_IDX 1 3000#define regCP_CE_IB2_BASE_HI 0x20ca
3001#define regCP_CE_IB2_BASE_HI_BASE_IDX 1 3002#define regCP_CE_IB2_BUFSZ 0x20cb 3003#define regCP_CE_IB2_BUFSZ_BASE_IDX 1 3004#define regCP_IB2_BASE_LO 0x20cf 3005#define regCP_IB2_BASE_LO_BASE_IDX 1 3006#define regCP_IB2_BASE_HI 0x20d0 3007#define regCP_IB2_BASE_HI_BASE_IDX 1 3008#define regCP_IB2_BUFSZ 0x20d1 3009#define regCP_IB2_BUFSZ_BASE_IDX 1 3010#define regCP_ST_BASE_LO 0x20d2 3011#define regCP_ST_BASE_LO_BASE_IDX 1 3012#define regCP_ST_BASE_HI 0x20d3 3013#define regCP_ST_BASE_HI_BASE_IDX 1 3014#define regCP_ST_BUFSZ 0x20d4 3015#define regCP_ST_BUFSZ_BASE_IDX 1 3016#define regCP_EOP_DONE_EVENT_CNTL 0x20d5 3017#define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 3018#define regCP_EOP_DONE_DATA_CNTL 0x20d6 3019#define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 3020#define regCP_EOP_DONE_CNTX_ID 0x20d7 3021#define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 3022#define regCP_PFP_COMPLETION_STATUS 0x20ec 3023#define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 3024#define regCP_CE_COMPLETION_STATUS 0x20ed 3025#define regCP_CE_COMPLETION_STATUS_BASE_IDX 1 3026#define regCP_PRED_NOT_VISIBLE 0x20ee 3027#define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 3028#define regCP_PFP_METADATA_BASE_ADDR 0x20f0 3029#define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 3030#define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 3031#define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 3032#define regCP_CE_METADATA_BASE_ADDR 0x20f2 3033#define regCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 3034#define regCP_CE_METADATA_BASE_ADDR_HI 0x20f3 3035#define regCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 3036#define regCP_DRAW_INDX_INDR_ADDR 0x20f4 3037#define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 3038#define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 3039#define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 3040#define regCP_DISPATCH_INDR_ADDR 0x20f6 3041#define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 3042#define regCP_DISPATCH_INDR_ADDR_HI 0x20f7 3043#define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 3044#define regCP_INDEX_BASE_ADDR 0x20f8 3045#define regCP_INDEX_BASE_ADDR_BASE_IDX 1 3046#define regCP_INDEX_BASE_ADDR_HI 0x20f9 3047#define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 3048#define regCP_INDEX_TYPE 0x20fa 3049#define regCP_INDEX_TYPE_BASE_IDX 1 3050#define regCP_GDS_BKUP_ADDR 0x20fb 3051#define regCP_GDS_BKUP_ADDR_BASE_IDX 1 3052#define regCP_GDS_BKUP_ADDR_HI 0x20fc 3053#define regCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 3054#define regCP_SAMPLE_STATUS 0x20fd 3055#define regCP_SAMPLE_STATUS_BASE_IDX 1 3056#define regCP_ME_COHER_CNTL 0x20fe 3057#define regCP_ME_COHER_CNTL_BASE_IDX 1 3058#define regCP_ME_COHER_SIZE 0x20ff 3059#define regCP_ME_COHER_SIZE_BASE_IDX 1 3060#define regCP_ME_COHER_SIZE_HI 0x2100 3061#define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 3062#define regCP_ME_COHER_BASE 0x2101 3063#define regCP_ME_COHER_BASE_BASE_IDX 1 3064#define regCP_ME_COHER_BASE_HI 0x2102 3065#define regCP_ME_COHER_BASE_HI_BASE_IDX 1 3066#define regCP_ME_COHER_STATUS 0x2103 3067#define regCP_ME_COHER_STATUS_BASE_IDX 1 3068#define regRLC_GPM_PERF_COUNT_0 0x2140 3069#define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 3070#define regRLC_GPM_PERF_COUNT_1 0x2141 3071#define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 3072#define regGRBM_GFX_INDEX 0x2200 3073#define regGRBM_GFX_INDEX_BASE_IDX 1 3074#define regVGT_GSVS_RING_SIZE 0x2241 3075#define regVGT_GSVS_RING_SIZE_BASE_IDX 1 3076#define regVGT_PRIMITIVE_TYPE 0x2242 3077#define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 3078#define regVGT_INDEX_TYPE 0x2243 3079#define regVGT_INDEX_TYPE_BASE_IDX 1 3080#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244 3081#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 3082#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245 3083#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 3084#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246 3085#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 3086#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247 3087#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 3088#define regVGT_MAX_VTX_INDX 0x2248 3089#define regVGT_MAX_VTX_INDX_BASE_IDX 1 3090#define regVGT_MIN_VTX_INDX 0x2249 3091#define regVGT_MIN_VTX_INDX_BASE_IDX 1 3092#define regVGT_INDX_OFFSET 0x224a 3093#define regVGT_INDX_OFFSET_BASE_IDX 1 3094#define regVGT_MULTI_PRIM_IB_RESET_EN 0x224b 3095#define regVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 3096#define regVGT_NUM_INDICES 0x224c 3097#define regVGT_NUM_INDICES_BASE_IDX 1 3098#define regVGT_NUM_INSTANCES 0x224d 3099#define regVGT_NUM_INSTANCES_BASE_IDX 1 3100#define regVGT_TF_RING_SIZE 0x224e 3101#define regVGT_TF_RING_SIZE_BASE_IDX 1 3102#define regVGT_HS_OFFCHIP_PARAM 0x224f 3103#define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 3104#define regVGT_TF_MEMORY_BASE 0x2250 3105#define regVGT_TF_MEMORY_BASE_BASE_IDX 1 3106#define regVGT_TF_MEMORY_BASE_HI 0x2251 3107#define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 3108#define regWD_POS_BUF_BASE 0x2252 3109#define regWD_POS_BUF_BASE_BASE_IDX 1 3110#define regWD_POS_BUF_BASE_HI 0x2253 3111#define regWD_POS_BUF_BASE_HI_BASE_IDX 1 3112#define regWD_CNTL_SB_BUF_BASE 0x2254 3113#define regWD_CNTL_SB_BUF_BASE_BASE_IDX 1 3114#define regWD_CNTL_SB_BUF_BASE_HI 0x2255 3115#define regWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 3116#define regWD_INDEX_BUF_BASE 0x2256 3117#define regWD_INDEX_BUF_BASE_BASE_IDX 1 3118#define regWD_INDEX_BUF_BASE_HI 0x2257 3119#define regWD_INDEX_BUF_BASE_HI_BASE_IDX 1 3120#define regIA_MULTI_VGT_PARAM 0x2258 3121#define regIA_MULTI_VGT_PARAM_BASE_IDX 1 3122#define regVGT_INSTANCE_BASE_ID 0x225a 3123#define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 3124#define regPA_SU_LINE_STIPPLE_VALUE 0x2280 3125#define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 3126#define regPA_SC_LINE_STIPPLE_STATE 0x2281 3127#define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 3128#define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284 3129#define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 3130#define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285 3131#define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 3132#define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286 3133#define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 3134#define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b 3135#define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 3136#define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 3137#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 3138#define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1 3139#define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 3140#define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2 3141#define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 3142#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 3143#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 3144#define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 3145#define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 3146#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 3147#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 3148#define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 3149#define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 3150#define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa 3151#define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 3152#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab 3153#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 3154#define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac 3155#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 3156#define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0 3157#define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 3158#define regPA_SC_TRAP_SCREEN_H 0x22b1 3159#define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 3160#define regPA_SC_TRAP_SCREEN_V 0x22b2 3161#define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 3162#define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 3163#define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 3164#define regPA_SC_TRAP_SCREEN_COUNT 0x22b4 3165#define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 3166#define regPA_STATE_STEREO_X 0x22b5 3167#define regPA_STATE_STEREO_X_BASE_IDX 1 3168#define regSQ_THREAD_TRACE_BASE 0x2330 3169#define regSQ_THREAD_TRACE_BASE_BASE_IDX 1 3170#define regSQ_THREAD_TRACE_SIZE 0x2331 3171#define regSQ_THREAD_TRACE_SIZE_BASE_IDX 1 3172#define regSQ_THREAD_TRACE_MASK 0x2332 3173#define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 3174#define regSQ_THREAD_TRACE_TOKEN_MASK 0x2333 3175#define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 3176#define regSQ_THREAD_TRACE_PERF_MASK 0x2334 3177#define regSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1 3178#define regSQ_THREAD_TRACE_CTRL 0x2335 3179#define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 3180#define regSQ_THREAD_TRACE_MODE 0x2336 3181#define regSQ_THREAD_TRACE_MODE_BASE_IDX 1 3182#define regSQ_THREAD_TRACE_BASE2 0x2337 3183#define regSQ_THREAD_TRACE_BASE2_BASE_IDX 1 3184#define regSQ_THREAD_TRACE_TOKEN_MASK2 0x2338 3185#define regSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1 3186#define regSQ_THREAD_TRACE_WPTR 0x2339 3187#define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 3188#define regSQ_THREAD_TRACE_STATUS 0x233a 3189#define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 3190#define regSQ_THREAD_TRACE_HIWATER 0x233b 3191#define regSQ_THREAD_TRACE_HIWATER_BASE_IDX 1 3192#define regSQ_THREAD_TRACE_CNTR 0x233c 3193#define regSQ_THREAD_TRACE_CNTR_BASE_IDX 1 3194#define regSQ_THREAD_TRACE_USERDATA_0 0x2340 3195#define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 3196#define regSQ_THREAD_TRACE_USERDATA_1 0x2341 3197#define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 3198#define regSQ_THREAD_TRACE_USERDATA_2 0x2342 3199#define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 3200#define regSQ_THREAD_TRACE_USERDATA_3 0x2343 3201#define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 3202#define regSQC_CACHES 0x2348 3203#define regSQC_CACHES_BASE_IDX 1 3204#define regSQC_WRITEBACK 0x2349 3205#define regSQC_WRITEBACK_BASE_IDX 1 3206#define regDB_OCCLUSION_COUNT0_LOW 0x23c0 3207#define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 3208#define regDB_OCCLUSION_COUNT0_HI 0x23c1 3209#define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 3210#define regDB_OCCLUSION_COUNT1_LOW 0x23c2 3211#define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 3212#define regDB_OCCLUSION_COUNT1_HI 0x23c3 3213#define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 3214#define regDB_OCCLUSION_COUNT2_LOW 0x23c4 3215#define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 3216#define regDB_OCCLUSION_COUNT2_HI 0x23c5 3217#define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 3218#define regDB_OCCLUSION_COUNT3_LOW 0x23c6 3219#define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 3220#define regDB_OCCLUSION_COUNT3_HI 0x23c7 3221#define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 3222#define regDB_ZPASS_COUNT_LOW 0x23fe 3223#define regDB_ZPASS_COUNT_LOW_BASE_IDX 1 3224#define regDB_ZPASS_COUNT_HI 0x23ff 3225#define regDB_ZPASS_COUNT_HI_BASE_IDX 1 3226#define regGDS_RD_ADDR 0x2400 3227#define regGDS_RD_ADDR_BASE_IDX 1 3228#define regGDS_RD_DATA 0x2401 3229#define regGDS_RD_DATA_BASE_IDX 1 3230#define regGDS_RD_BURST_ADDR 0x2402 3231#define regGDS_RD_BURST_ADDR_BASE_IDX 1 3232#define regGDS_RD_BURST_COUNT 0x2403 3233#define regGDS_RD_BURST_COUNT_BASE_IDX 1 3234#define regGDS_RD_BURST_DATA 0x2404 3235#define regGDS_RD_BURST_DATA_BASE_IDX 1 3236#define regGDS_WR_ADDR 0x2405 3237#define regGDS_WR_ADDR_BASE_IDX 1 3238#define regGDS_WR_DATA 0x2406 3239#define regGDS_WR_DATA_BASE_IDX 1 3240#define regGDS_WR_BURST_ADDR 0x2407 3241#define regGDS_WR_BURST_ADDR_BASE_IDX 1 3242#define regGDS_WR_BURST_DATA 0x2408 3243#define regGDS_WR_BURST_DATA_BASE_IDX 1 3244#define regGDS_WRITE_COMPLETE 0x2409 3245#define regGDS_WRITE_COMPLETE_BASE_IDX 1 3246#define regGDS_ATOM_CNTL 0x240a 3247#define regGDS_ATOM_CNTL_BASE_IDX 1 3248#define regGDS_ATOM_COMPLETE 0x240b 3249#define regGDS_ATOM_COMPLETE_BASE_IDX 1 3250#define regGDS_ATOM_BASE 0x240c 3251#define regGDS_ATOM_BASE_BASE_IDX 1 3252#define regGDS_ATOM_SIZE 0x240d 3253#define regGDS_ATOM_SIZE_BASE_IDX 1 3254#define regGDS_ATOM_OFFSET0 0x240e 3255#define regGDS_ATOM_OFFSET0_BASE_IDX 1 3256#define regGDS_ATOM_OFFSET1 0x240f 3257#define regGDS_ATOM_OFFSET1_BASE_IDX 1 3258#define regGDS_ATOM_DST 0x2410 3259#define regGDS_ATOM_DST_BASE_IDX 1 3260#define regGDS_ATOM_OP 0x2411 3261#define regGDS_ATOM_OP_BASE_IDX 1 3262#define regGDS_ATOM_SRC0 0x2412 3263#define regGDS_ATOM_SRC0_BASE_IDX 1 3264#define regGDS_ATOM_SRC0_U 0x2413 3265#define regGDS_ATOM_SRC0_U_BASE_IDX 1 3266#define regGDS_ATOM_SRC1 0x2414 3267#define regGDS_ATOM_SRC1_BASE_IDX 1 3268#define regGDS_ATOM_SRC1_U 0x2415 3269#define regGDS_ATOM_SRC1_U_BASE_IDX 1 3270#define regGDS_ATOM_READ0 0x2416 3271#define regGDS_ATOM_READ0_BASE_IDX 1 3272#define regGDS_ATOM_READ0_U 0x2417 3273#define regGDS_ATOM_READ0_U_BASE_IDX 1 3274#define regGDS_ATOM_READ1 0x2418 3275#define regGDS_ATOM_READ1_BASE_IDX 1 3276#define regGDS_ATOM_READ1_U 0x2419 3277#define regGDS_ATOM_READ1_U_BASE_IDX 1 3278#define regGDS_GWS_RESOURCE_CNTL 0x241a 3279#define regGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 3280#define regGDS_GWS_RESOURCE 0x241b 3281#define regGDS_GWS_RESOURCE_BASE_IDX 1 3282#define regGDS_GWS_RESOURCE_CNT 0x241c 3283#define regGDS_GWS_RESOURCE_CNT_BASE_IDX 1 3284#define regGDS_OA_CNTL 0x241d 3285#define regGDS_OA_CNTL_BASE_IDX 1 3286#define regGDS_OA_COUNTER 0x241e 3287#define regGDS_OA_COUNTER_BASE_IDX 1 3288#define regGDS_OA_ADDRESS 0x241f 3289#define regGDS_OA_ADDRESS_BASE_IDX 1 3290#define regGDS_OA_INCDEC 0x2420 3291#define regGDS_OA_INCDEC_BASE_IDX 1 3292#define regGDS_OA_RING_SIZE 0x2421 3293#define regGDS_OA_RING_SIZE_BASE_IDX 1 3294#define regSPI_CONFIG_CNTL 0x2440 3295#define regSPI_CONFIG_CNTL_BASE_IDX 1 3296#define regSPI_CONFIG_CNTL_1 0x2441 3297#define regSPI_CONFIG_CNTL_1_BASE_IDX 1 3298#define regSPI_CONFIG_CNTL_2 0x2442 3299#define regSPI_CONFIG_CNTL_2_BASE_IDX 1 3300#define regSPI_WAVE_LIMIT_CNTL 0x2443 3301#define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 3302 3303 3304// addressBlock: gc_grbmdec 3305// base address: 0x8000 3306#define regGRBM_CNTL 0x0000 3307#define regGRBM_CNTL_BASE_IDX 0 3308#define regGRBM_SKEW_CNTL 0x0001 3309#define regGRBM_SKEW_CNTL_BASE_IDX 0 3310#define regGRBM_STATUS2 0x0002 3311#define regGRBM_STATUS2_BASE_IDX 0 3312#define regGRBM_PWR_CNTL 0x0003 3313#define regGRBM_PWR_CNTL_BASE_IDX 0 3314#define regGRBM_STATUS 0x0004 3315#define regGRBM_STATUS_BASE_IDX 0 3316#define regGRBM_STATUS_SE0 0x0005 3317#define regGRBM_STATUS_SE0_BASE_IDX 0 3318#define regGRBM_STATUS_SE1 0x0006 3319#define regGRBM_STATUS_SE1_BASE_IDX 0 3320#define regGRBM_SOFT_RESET 0x0008 3321#define regGRBM_SOFT_RESET_BASE_IDX 0 3322#define regGRBM_GFX_CLKEN_CNTL 0x000c 3323#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 3324#define regGRBM_WAIT_IDLE_CLOCKS 0x000d 3325#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 3326#define regGRBM_STATUS_SE2 0x000e 3327#define regGRBM_STATUS_SE2_BASE_IDX 0 3328#define regGRBM_STATUS_SE3 0x000f 3329#define regGRBM_STATUS_SE3_BASE_IDX 0 3330#define regGRBM_READ_ERROR 0x0016 3331#define regGRBM_READ_ERROR_BASE_IDX 0 3332#define regGRBM_READ_ERROR2 0x0017 3333#define regGRBM_READ_ERROR2_BASE_IDX 0 3334#define regGRBM_INT_CNTL 0x0018 3335#define regGRBM_INT_CNTL_BASE_IDX 0 3336#define regGRBM_TRAP_OP 0x0019 3337#define regGRBM_TRAP_OP_BASE_IDX 0 3338#define regGRBM_TRAP_ADDR 0x001a 3339#define regGRBM_TRAP_ADDR_BASE_IDX 0 3340#define regGRBM_TRAP_ADDR_MSK 0x001b 3341#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 3342#define regGRBM_TRAP_WD 0x001c 3343#define regGRBM_TRAP_WD_BASE_IDX 0 3344#define regGRBM_TRAP_WD_MSK 0x001d 3345#define regGRBM_TRAP_WD_MSK_BASE_IDX 0 3346#define regGRBM_WRITE_ERROR 0x001f 3347#define regGRBM_WRITE_ERROR_BASE_IDX 0 3348#define regGRBM_CHIP_REVISION 0x0021 3349#define regGRBM_CHIP_REVISION_BASE_IDX 0 3350#define regGRBM_GFX_CNTL 0x0022 3351#define regGRBM_GFX_CNTL_BASE_IDX 0 3352#define regGRBM_IH_CREDIT 0x0024 3353#define regGRBM_IH_CREDIT_BASE_IDX 0 3354#define regGRBM_PWR_CNTL2 0x0025 3355#define regGRBM_PWR_CNTL2_BASE_IDX 0 3356#define regGRBM_UTCL2_INVAL_RANGE_START 0x0026 3357#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 3358#define regGRBM_UTCL2_INVAL_RANGE_END 0x0027 3359#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 3360#define regGRBM_CHICKEN_BITS 0x0029 3361#define regGRBM_CHICKEN_BITS_BASE_IDX 0 3362#define regGRBM_FENCE_RANGE0 0x002a 3363#define regGRBM_FENCE_RANGE0_BASE_IDX 0 3364#define regGRBM_FENCE_RANGE1 0x002b 3365#define regGRBM_FENCE_RANGE1_BASE_IDX 0 3366#define regGRBM_NOWHERE 0x003f 3367#define regGRBM_NOWHERE_BASE_IDX 0 3368#define regGRBM_SCRATCH_REG0 0x0040 3369#define regGRBM_SCRATCH_REG0_BASE_IDX 0 3370#define regGRBM_SCRATCH_REG1 0x0041 3371#define regGRBM_SCRATCH_REG1_BASE_IDX 0 3372#define regGRBM_SCRATCH_REG2 0x0042 3373#define regGRBM_SCRATCH_REG2_BASE_IDX 0 3374#define regGRBM_SCRATCH_REG3 0x0043 3375#define regGRBM_SCRATCH_REG3_BASE_IDX 0 3376#define regGRBM_SCRATCH_REG4 0x0044 3377#define regGRBM_SCRATCH_REG4_BASE_IDX 0 3378#define regGRBM_SCRATCH_REG5 0x0045 3379#define regGRBM_SCRATCH_REG5_BASE_IDX 0 3380#define regGRBM_SCRATCH_REG6 0x0046 3381#define regGRBM_SCRATCH_REG6_BASE_IDX 0 3382#define regGRBM_SCRATCH_REG7 0x0047 3383#define regGRBM_SCRATCH_REG7_BASE_IDX 0 3384#define regVIOLATION_DATA_ASYNC_VF_PROG 0x0048 3385#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 3386 3387 3388// addressBlock: gc_hypdec 3389// base address: 0x3e000 3390#define regCP_HYP_PFP_UCODE_ADDR 0x5814 3391#define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 3392#define regCP_PFP_UCODE_ADDR 0x5814 3393#define regCP_PFP_UCODE_ADDR_BASE_IDX 1 3394#define regCP_HYP_PFP_UCODE_DATA 0x5815 3395#define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 3396#define regCP_PFP_UCODE_DATA 0x5815 3397#define regCP_PFP_UCODE_DATA_BASE_IDX 1 3398#define regCP_HYP_ME_UCODE_ADDR 0x5816 3399#define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 3400#define regCP_ME_RAM_RADDR 0x5816 3401#define regCP_ME_RAM_RADDR_BASE_IDX 1 3402#define regCP_ME_RAM_WADDR 0x5816 3403#define regCP_ME_RAM_WADDR_BASE_IDX 1 3404#define regCP_HYP_ME_UCODE_DATA 0x5817 3405#define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 3406#define regCP_ME_RAM_DATA 0x5817 3407#define regCP_ME_RAM_DATA_BASE_IDX 1 3408#define regCP_CE_UCODE_ADDR 0x5818 3409#define regCP_CE_UCODE_ADDR_BASE_IDX 1 3410#define regCP_HYP_CE_UCODE_ADDR 0x5818 3411#define regCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 3412#define regCP_CE_UCODE_DATA 0x5819 3413#define regCP_CE_UCODE_DATA_BASE_IDX 1 3414#define regCP_HYP_CE_UCODE_DATA 0x5819 3415#define regCP_HYP_CE_UCODE_DATA_BASE_IDX 1 3416#define regCP_HYP_MEC1_UCODE_ADDR 0x581a 3417#define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 3418#define regCP_MEC_ME1_UCODE_ADDR 0x581a 3419#define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 3420#define regCP_HYP_MEC1_UCODE_DATA 0x581b 3421#define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 3422#define regCP_MEC_ME1_UCODE_DATA 0x581b 3423#define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 3424#define regCP_HYP_MEC2_UCODE_ADDR 0x581c 3425#define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 3426#define regCP_MEC_ME2_UCODE_ADDR 0x581c 3427#define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 3428#define regCP_HYP_MEC2_UCODE_DATA 0x581d 3429#define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 3430#define regCP_MEC_ME2_UCODE_DATA 0x581d 3431#define regCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 3432#define regRLC_GPM_UCODE_ADDR 0x583c 3433#define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 3434#define regRLC_GPM_UCODE_DATA 0x583d 3435#define regRLC_GPM_UCODE_DATA_BASE_IDX 1 3436#define regGRBM_GFX_INDEX_SR_SELECT 0x5a00 3437#define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 3438#define regGRBM_GFX_INDEX_SR_DATA 0x5a01 3439#define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 3440#define regGRBM_GFX_CNTL_SR_SELECT 0x5a02 3441#define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 3442#define regGRBM_GFX_CNTL_SR_DATA 0x5a03 3443#define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 3444#define regGRBM_CAM_INDEX 0x5a04 3445#define regGRBM_CAM_INDEX_BASE_IDX 1 3446#define regGRBM_HYP_CAM_INDEX 0x5a04 3447#define regGRBM_HYP_CAM_INDEX_BASE_IDX 1 3448#define regGRBM_CAM_DATA 0x5a05 3449#define regGRBM_CAM_DATA_BASE_IDX 1 3450#define regGRBM_HYP_CAM_DATA 0x5a05 3451#define regGRBM_HYP_CAM_DATA_BASE_IDX 1 3452#define regRLC_GPU_IOV_VF_ENABLE 0x5b00 3453#define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 3454#define regRLC_GPU_IOV_CFG_REG6 0x5b06 3455#define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 3456#define regRLC_GPU_IOV_CFG_REG8 0x5b20 3457#define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 3458#define regRLC_RLCV_TIMER_INT_0 0x5b25 3459#define regRLC_RLCV_TIMER_INT_0_BASE_IDX 1 3460#define regRLC_RLCV_TIMER_CTRL 0x5b26 3461#define regRLC_RLCV_TIMER_CTRL_BASE_IDX 1 3462#define regRLC_RLCV_TIMER_STAT 0x5b27 3463#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1 3464#define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a 3465#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 3466#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b 3467#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 3468#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c 3469#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 3470#define regRLC_GPU_IOV_VF_MASK 0x5b2d 3471#define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 3472#define regRLC_HYP_SEMAPHORE_0 0x5b2e 3473#define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 3474#define regRLC_HYP_SEMAPHORE_1 0x5b2f 3475#define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 3476#define regRLC_CLK_CNTL 0x5b31 3477#define regRLC_CLK_CNTL_BASE_IDX 1 3478#define regRLC_GPU_IOV_SCH_BLOCK 0x5b34 3479#define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 3480#define regRLC_GPU_IOV_CFG_REG1 0x5b35 3481#define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 3482#define regRLC_GPU_IOV_CFG_REG2 0x5b36 3483#define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 3484#define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 3485#define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 3486#define regRLC_GPU_IOV_SCH_0 0x5b38 3487#define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 3488#define regRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 3489#define regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 3490#define regRLC_GPU_IOV_SCH_3 0x5b3a 3491#define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 3492#define regRLC_GPU_IOV_SCH_1 0x5b3b 3493#define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 3494#define regRLC_GPU_IOV_SCH_2 0x5b3c 3495#define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 3496#define regRLC_GPU_IOV_INT_STAT 0x5b3f 3497#define regRLC_GPU_IOV_INT_STAT_BASE_IDX 1 3498#define regRLC_RLCV_TIMER_INT_1 0x5b40 3499#define regRLC_RLCV_TIMER_INT_1_BASE_IDX 1 3500#define regRLC_GPU_IOV_UCODE_ADDR 0x5b42 3501#define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 3502#define regRLC_GPU_IOV_UCODE_DATA 0x5b43 3503#define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 3504#define regRLC_GPU_IOV_SCRATCH_ADDR 0x5b44 3505#define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 3506#define regRLC_GPU_IOV_SCRATCH_DATA 0x5b45 3507#define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 3508#define regRLC_GPU_IOV_F32_CNTL 0x5b46 3509#define regRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 3510#define regRLC_GPU_IOV_F32_RESET 0x5b47 3511#define regRLC_GPU_IOV_F32_RESET_BASE_IDX 1 3512#define regRLC_GPU_IOV_SDMA0_STATUS 0x5b48 3513#define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 3514#define regRLC_GPU_IOV_SDMA1_STATUS 0x5b49 3515#define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 3516#define regRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c 3517#define regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 3518#define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d 3519#define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 3520#define regRLC_GPU_IOV_INT_DISABLE 0x5b4e 3521#define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 3522#define regRLC_GPU_IOV_INT_FORCE 0x5b4f 3523#define regRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 3524#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50 3525#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 3526#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51 3527#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 3528#define regRLC_HYP_SEMAPHORE_2 0x5b52 3529#define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 3530#define regRLC_HYP_SEMAPHORE_3 0x5b53 3531#define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 3532#define regRLC_GPU_IOV_SDMA2_STATUS 0x5b54 3533#define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 3534#define regRLC_GPU_IOV_SDMA3_STATUS 0x5b55 3535#define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 3536#define regRLC_GPU_IOV_SDMA4_STATUS 0x5b56 3537#define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 3538#define regRLC_GPU_IOV_SDMA5_STATUS 0x5b57 3539#define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 3540#define regRLC_GPU_IOV_SDMA6_STATUS 0x5b58 3541#define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 3542#define regRLC_GPU_IOV_SDMA7_STATUS 0x5b59 3543#define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 3544#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5b5a 3545#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 3546#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5b5b 3547#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 3548#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5b5c 3549#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 3550#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5b5d 3551#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 3552#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5b5e 3553#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 3554#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5b5f 3555#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 3556 3557 3558// addressBlock: gc_padec 3559// base address: 0x8800 3560#define regVGT_VTX_VECT_EJECT_REG 0x022c 3561#define regVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 3562#define regVGT_DMA_DATA_FIFO_DEPTH 0x022d 3563#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 3564#define regVGT_DMA_REQ_FIFO_DEPTH 0x022e 3565#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 3566#define regVGT_DRAW_INIT_FIFO_DEPTH 0x022f 3567#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 3568#define regVGT_LAST_COPY_STATE 0x0230 3569#define regVGT_LAST_COPY_STATE_BASE_IDX 0 3570#define regVGT_CACHE_INVALIDATION 0x0231 3571#define regVGT_CACHE_INVALIDATION_BASE_IDX 0 3572#define regVGT_STRMOUT_DELAY 0x0233 3573#define regVGT_STRMOUT_DELAY_BASE_IDX 0 3574#define regVGT_FIFO_DEPTHS 0x0234 3575#define regVGT_FIFO_DEPTHS_BASE_IDX 0 3576#define regVGT_GS_VERTEX_REUSE 0x0235 3577#define regVGT_GS_VERTEX_REUSE_BASE_IDX 0 3578#define regVGT_MC_LAT_CNTL 0x0236 3579#define regVGT_MC_LAT_CNTL_BASE_IDX 0 3580#define regIA_CNTL_STATUS 0x0237 3581#define regIA_CNTL_STATUS_BASE_IDX 0 3582#define regVGT_CNTL_STATUS 0x023c 3583#define regVGT_CNTL_STATUS_BASE_IDX 0 3584#define regWD_CNTL_STATUS 0x023f 3585#define regWD_CNTL_STATUS_BASE_IDX 0 3586#define regCC_GC_PRIM_CONFIG 0x0240 3587#define regCC_GC_PRIM_CONFIG_BASE_IDX 0 3588#define regGC_USER_PRIM_CONFIG 0x0241 3589#define regGC_USER_PRIM_CONFIG_BASE_IDX 0 3590#define regWD_QOS 0x0242 3591#define regWD_QOS_BASE_IDX 0 3592#define regWD_UTCL1_CNTL 0x0243 3593#define regWD_UTCL1_CNTL_BASE_IDX 0 3594#define regWD_UTCL1_STATUS 0x0244 3595#define regWD_UTCL1_STATUS_BASE_IDX 0 3596#define regIA_UTCL1_CNTL 0x0246 3597#define regIA_UTCL1_CNTL_BASE_IDX 0 3598#define regIA_UTCL1_STATUS 0x0247 3599#define regIA_UTCL1_STATUS_BASE_IDX 0 3600#define regVGT_SYS_CONFIG 0x0263 3601#define regVGT_SYS_CONFIG_BASE_IDX 0 3602#define regVGT_VS_MAX_WAVE_ID 0x0268 3603#define regVGT_VS_MAX_WAVE_ID_BASE_IDX 0 3604#define regVGT_GS_MAX_WAVE_ID 0x0269 3605#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 3606#define regGFX_PIPE_CONTROL 0x026d 3607#define regGFX_PIPE_CONTROL_BASE_IDX 0 3608#define regCC_GC_SHADER_ARRAY_CONFIG 0x026f 3609#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 3610#define regGC_USER_SHADER_ARRAY_CONFIG 0x0270 3611#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 3612#define regVGT_DMA_PRIMITIVE_TYPE 0x0271 3613#define regVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 3614#define regVGT_DMA_CONTROL 0x0272 3615#define regVGT_DMA_CONTROL_BASE_IDX 0 3616#define regVGT_DMA_LS_HS_CONFIG 0x0273 3617#define regVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 3618#define regWD_BUF_RESOURCE_1 0x0276 3619#define regWD_BUF_RESOURCE_1_BASE_IDX 0 3620#define regWD_BUF_RESOURCE_2 0x0277 3621#define regWD_BUF_RESOURCE_2_BASE_IDX 0 3622#define regPA_CL_CNTL_STATUS 0x0284 3623#define regPA_CL_CNTL_STATUS_BASE_IDX 0 3624#define regPA_CL_ENHANCE 0x0285 3625#define regPA_CL_ENHANCE_BASE_IDX 0 3626#define regPA_SU_CNTL_STATUS 0x0294 3627#define regPA_SU_CNTL_STATUS_BASE_IDX 0 3628#define regPA_SC_FIFO_DEPTH_CNTL 0x0295 3629#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 3630#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0 3631#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 3632#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1 3633#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 3634#define regPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2 3635#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 3636#define regPA_SC_FORCE_EOV_MAX_CNTS 0x02c9 3637#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 3638#define regPA_SC_BINNER_EVENT_CNTL_0 0x02cc 3639#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 3640#define regPA_SC_BINNER_EVENT_CNTL_1 0x02cd 3641#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 3642#define regPA_SC_BINNER_EVENT_CNTL_2 0x02ce 3643#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 3644#define regPA_SC_BINNER_EVENT_CNTL_3 0x02cf 3645#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 3646#define regPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0 3647#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 3648#define regPA_SC_BINNER_PERF_CNTL_0 0x02d1 3649#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 3650#define regPA_SC_BINNER_PERF_CNTL_1 0x02d2 3651#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 3652#define regPA_SC_BINNER_PERF_CNTL_2 0x02d3 3653#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 3654#define regPA_SC_BINNER_PERF_CNTL_3 0x02d4 3655#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 3656#define regPA_SC_ENHANCE_2 0x02dc 3657#define regPA_SC_ENHANCE_2_BASE_IDX 0 3658#define regPA_SC_FIFO_SIZE 0x02f3 3659#define regPA_SC_FIFO_SIZE_BASE_IDX 0 3660#define regPA_SC_IF_FIFO_SIZE 0x02f5 3661#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 0 3662#define regPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8 3663#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 3664#define regPA_UTCL1_CNTL1 0x02f9 3665#define regPA_UTCL1_CNTL1_BASE_IDX 0 3666#define regPA_UTCL1_CNTL2 0x02fa 3667#define regPA_UTCL1_CNTL2_BASE_IDX 0 3668#define regPA_SIDEBAND_REQUEST_DELAYS 0x02fb 3669#define regPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 3670#define regPA_SC_ENHANCE 0x02fc 3671#define regPA_SC_ENHANCE_BASE_IDX 0 3672#define regPA_SC_ENHANCE_1 0x02fd 3673#define regPA_SC_ENHANCE_1_BASE_IDX 0 3674#define regPA_SC_DSM_CNTL 0x02fe 3675#define regPA_SC_DSM_CNTL_BASE_IDX 0 3676#define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff 3677#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 3678 3679 3680// addressBlock: gc_perfddec 3681// base address: 0x34000 3682#define regCPG_PERFCOUNTER1_LO 0x3000 3683#define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 3684#define regCPG_PERFCOUNTER1_HI 0x3001 3685#define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 3686#define regCPG_PERFCOUNTER0_LO 0x3002 3687#define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 3688#define regCPG_PERFCOUNTER0_HI 0x3003 3689#define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 3690#define regCPC_PERFCOUNTER1_LO 0x3004 3691#define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 3692#define regCPC_PERFCOUNTER1_HI 0x3005 3693#define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 3694#define regCPC_PERFCOUNTER0_LO 0x3006 3695#define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 3696#define regCPC_PERFCOUNTER0_HI 0x3007 3697#define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 3698#define regCPF_PERFCOUNTER1_LO 0x3008 3699#define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 3700#define regCPF_PERFCOUNTER1_HI 0x3009 3701#define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 3702#define regCPF_PERFCOUNTER0_LO 0x300a 3703#define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 3704#define regCPF_PERFCOUNTER0_HI 0x300b 3705#define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 3706#define regCPF_LATENCY_STATS_DATA 0x300c 3707#define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 3708#define regCPG_LATENCY_STATS_DATA 0x300d 3709#define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 3710#define regCPC_LATENCY_STATS_DATA 0x300e 3711#define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 3712#define regGRBM_PERFCOUNTER0_LO 0x3040 3713#define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 3714#define regGRBM_PERFCOUNTER0_HI 0x3041 3715#define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 3716#define regGRBM_PERFCOUNTER1_LO 0x3043 3717#define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 3718#define regGRBM_PERFCOUNTER1_HI 0x3044 3719#define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 3720#define regGRBM_SE0_PERFCOUNTER_LO 0x3045 3721#define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 3722#define regGRBM_SE0_PERFCOUNTER_HI 0x3046 3723#define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 3724#define regGRBM_SE1_PERFCOUNTER_LO 0x3047 3725#define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 3726#define regGRBM_SE1_PERFCOUNTER_HI 0x3048 3727#define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 3728#define regGRBM_SE2_PERFCOUNTER_LO 0x3049 3729#define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 3730#define regGRBM_SE2_PERFCOUNTER_HI 0x304a 3731#define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 3732#define regGRBM_SE3_PERFCOUNTER_LO 0x304b 3733#define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 3734#define regGRBM_SE3_PERFCOUNTER_HI 0x304c 3735#define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 3736#define regWD_PERFCOUNTER0_LO 0x3080 3737#define regWD_PERFCOUNTER0_LO_BASE_IDX 1 3738#define regWD_PERFCOUNTER0_HI 0x3081 3739#define regWD_PERFCOUNTER0_HI_BASE_IDX 1 3740#define regWD_PERFCOUNTER1_LO 0x3082 3741#define regWD_PERFCOUNTER1_LO_BASE_IDX 1 3742#define regWD_PERFCOUNTER1_HI 0x3083 3743#define regWD_PERFCOUNTER1_HI_BASE_IDX 1 3744#define regWD_PERFCOUNTER2_LO 0x3084 3745#define regWD_PERFCOUNTER2_LO_BASE_IDX 1 3746#define regWD_PERFCOUNTER2_HI 0x3085 3747#define regWD_PERFCOUNTER2_HI_BASE_IDX 1 3748#define regWD_PERFCOUNTER3_LO 0x3086 3749#define regWD_PERFCOUNTER3_LO_BASE_IDX 1 3750#define regWD_PERFCOUNTER3_HI 0x3087 3751#define regWD_PERFCOUNTER3_HI_BASE_IDX 1 3752#define regIA_PERFCOUNTER0_LO 0x3088 3753#define regIA_PERFCOUNTER0_LO_BASE_IDX 1 3754#define regIA_PERFCOUNTER0_HI 0x3089 3755#define regIA_PERFCOUNTER0_HI_BASE_IDX 1 3756#define regIA_PERFCOUNTER1_LO 0x308a 3757#define regIA_PERFCOUNTER1_LO_BASE_IDX 1 3758#define regIA_PERFCOUNTER1_HI 0x308b 3759#define regIA_PERFCOUNTER1_HI_BASE_IDX 1 3760#define regIA_PERFCOUNTER2_LO 0x308c 3761#define regIA_PERFCOUNTER2_LO_BASE_IDX 1 3762#define regIA_PERFCOUNTER2_HI 0x308d 3763#define regIA_PERFCOUNTER2_HI_BASE_IDX 1 3764#define regIA_PERFCOUNTER3_LO 0x308e 3765#define regIA_PERFCOUNTER3_LO_BASE_IDX 1 3766#define regIA_PERFCOUNTER3_HI 0x308f 3767#define regIA_PERFCOUNTER3_HI_BASE_IDX 1 3768#define regVGT_PERFCOUNTER0_LO 0x3090 3769#define regVGT_PERFCOUNTER0_LO_BASE_IDX 1 3770#define regVGT_PERFCOUNTER0_HI 0x3091 3771#define regVGT_PERFCOUNTER0_HI_BASE_IDX 1 3772#define regVGT_PERFCOUNTER1_LO 0x3092 3773#define regVGT_PERFCOUNTER1_LO_BASE_IDX 1 3774#define regVGT_PERFCOUNTER1_HI 0x3093 3775#define regVGT_PERFCOUNTER1_HI_BASE_IDX 1 3776#define regVGT_PERFCOUNTER2_LO 0x3094 3777#define regVGT_PERFCOUNTER2_LO_BASE_IDX 1 3778#define regVGT_PERFCOUNTER2_HI 0x3095 3779#define regVGT_PERFCOUNTER2_HI_BASE_IDX 1 3780#define regVGT_PERFCOUNTER3_LO 0x3096 3781#define regVGT_PERFCOUNTER3_LO_BASE_IDX 1 3782#define regVGT_PERFCOUNTER3_HI 0x3097 3783#define regVGT_PERFCOUNTER3_HI_BASE_IDX 1 3784#define regPA_SU_PERFCOUNTER0_LO 0x3100 3785#define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 3786#define regPA_SU_PERFCOUNTER0_HI 0x3101 3787#define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 3788#define regPA_SU_PERFCOUNTER1_LO 0x3102 3789#define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 3790#define regPA_SU_PERFCOUNTER1_HI 0x3103 3791#define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 3792#define regPA_SU_PERFCOUNTER2_LO 0x3104 3793#define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 3794#define regPA_SU_PERFCOUNTER2_HI 0x3105 3795#define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 3796#define regPA_SU_PERFCOUNTER3_LO 0x3106 3797#define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 3798#define regPA_SU_PERFCOUNTER3_HI 0x3107 3799#define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 3800#define regPA_SC_PERFCOUNTER0_LO 0x3140 3801#define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 3802#define regPA_SC_PERFCOUNTER0_HI 0x3141 3803#define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 3804#define regPA_SC_PERFCOUNTER1_LO 0x3142 3805#define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 3806#define regPA_SC_PERFCOUNTER1_HI 0x3143 3807#define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 3808#define regPA_SC_PERFCOUNTER2_LO 0x3144 3809#define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 3810#define regPA_SC_PERFCOUNTER2_HI 0x3145 3811#define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 3812#define regPA_SC_PERFCOUNTER3_LO 0x3146 3813#define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 3814#define regPA_SC_PERFCOUNTER3_HI 0x3147 3815#define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 3816#define regPA_SC_PERFCOUNTER4_LO 0x3148 3817#define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 3818#define regPA_SC_PERFCOUNTER4_HI 0x3149 3819#define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 3820#define regPA_SC_PERFCOUNTER5_LO 0x314a 3821#define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 3822#define regPA_SC_PERFCOUNTER5_HI 0x314b 3823#define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 3824#define regPA_SC_PERFCOUNTER6_LO 0x314c 3825#define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 3826#define regPA_SC_PERFCOUNTER6_HI 0x314d 3827#define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 3828#define regPA_SC_PERFCOUNTER7_LO 0x314e 3829#define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 3830#define regPA_SC_PERFCOUNTER7_HI 0x314f 3831#define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 3832#define regSPI_PERFCOUNTER0_HI 0x3180 3833#define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 3834#define regSPI_PERFCOUNTER0_LO 0x3181 3835#define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 3836#define regSPI_PERFCOUNTER1_HI 0x3182 3837#define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 3838#define regSPI_PERFCOUNTER1_LO 0x3183 3839#define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 3840#define regSPI_PERFCOUNTER2_HI 0x3184 3841#define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 3842#define regSPI_PERFCOUNTER2_LO 0x3185 3843#define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 3844#define regSPI_PERFCOUNTER3_HI 0x3186 3845#define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 3846#define regSPI_PERFCOUNTER3_LO 0x3187 3847#define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 3848#define regSPI_PERFCOUNTER4_HI 0x3188 3849#define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 3850#define regSPI_PERFCOUNTER4_LO 0x3189 3851#define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 3852#define regSPI_PERFCOUNTER5_HI 0x318a 3853#define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 3854#define regSPI_PERFCOUNTER5_LO 0x318b 3855#define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 3856#define regSQ_PERFCOUNTER0_LO 0x31c0 3857#define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 3858#define regSQ_PERFCOUNTER0_HI 0x31c1 3859#define regSQ_PERFCOUNTER0_HI_BASE_IDX 1 3860#define regSQ_PERFCOUNTER1_LO 0x31c2 3861#define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 3862#define regSQ_PERFCOUNTER1_HI 0x31c3 3863#define regSQ_PERFCOUNTER1_HI_BASE_IDX 1 3864#define regSQ_PERFCOUNTER2_LO 0x31c4 3865#define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 3866#define regSQ_PERFCOUNTER2_HI 0x31c5 3867#define regSQ_PERFCOUNTER2_HI_BASE_IDX 1 3868#define regSQ_PERFCOUNTER3_LO 0x31c6 3869#define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 3870#define regSQ_PERFCOUNTER3_HI 0x31c7 3871#define regSQ_PERFCOUNTER3_HI_BASE_IDX 1 3872#define regSQ_PERFCOUNTER4_LO 0x31c8 3873#define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 3874#define regSQ_PERFCOUNTER4_HI 0x31c9 3875#define regSQ_PERFCOUNTER4_HI_BASE_IDX 1 3876#define regSQ_PERFCOUNTER5_LO 0x31ca 3877#define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 3878#define regSQ_PERFCOUNTER5_HI 0x31cb 3879#define regSQ_PERFCOUNTER5_HI_BASE_IDX 1 3880#define regSQ_PERFCOUNTER6_LO 0x31cc 3881#define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 3882#define regSQ_PERFCOUNTER6_HI 0x31cd 3883#define regSQ_PERFCOUNTER6_HI_BASE_IDX 1 3884#define regSQ_PERFCOUNTER7_LO 0x31ce 3885#define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 3886#define regSQ_PERFCOUNTER7_HI 0x31cf 3887#define regSQ_PERFCOUNTER7_HI_BASE_IDX 1 3888#define regSQ_PERFCOUNTER8_LO 0x31d0 3889#define regSQ_PERFCOUNTER8_LO_BASE_IDX 1 3890#define regSQ_PERFCOUNTER8_HI 0x31d1 3891#define regSQ_PERFCOUNTER8_HI_BASE_IDX 1 3892#define regSQ_PERFCOUNTER9_LO 0x31d2 3893#define regSQ_PERFCOUNTER9_LO_BASE_IDX 1 3894#define regSQ_PERFCOUNTER9_HI 0x31d3 3895#define regSQ_PERFCOUNTER9_HI_BASE_IDX 1 3896#define regSQ_PERFCOUNTER10_LO 0x31d4 3897#define regSQ_PERFCOUNTER10_LO_BASE_IDX 1 3898#define regSQ_PERFCOUNTER10_HI 0x31d5 3899#define regSQ_PERFCOUNTER10_HI_BASE_IDX 1 3900#define regSQ_PERFCOUNTER11_LO 0x31d6 3901#define regSQ_PERFCOUNTER11_LO_BASE_IDX 1 3902#define regSQ_PERFCOUNTER11_HI 0x31d7 3903#define regSQ_PERFCOUNTER11_HI_BASE_IDX 1 3904#define regSQ_PERFCOUNTER12_LO 0x31d8 3905#define regSQ_PERFCOUNTER12_LO_BASE_IDX 1 3906#define regSQ_PERFCOUNTER12_HI 0x31d9 3907#define regSQ_PERFCOUNTER12_HI_BASE_IDX 1 3908#define regSQ_PERFCOUNTER13_LO 0x31da 3909#define regSQ_PERFCOUNTER13_LO_BASE_IDX 1 3910#define regSQ_PERFCOUNTER13_HI 0x31db 3911#define regSQ_PERFCOUNTER13_HI_BASE_IDX 1 3912#define regSQ_PERFCOUNTER14_LO 0x31dc 3913#define regSQ_PERFCOUNTER14_LO_BASE_IDX 1 3914#define regSQ_PERFCOUNTER14_HI 0x31dd 3915#define regSQ_PERFCOUNTER14_HI_BASE_IDX 1 3916#define regSQ_PERFCOUNTER15_LO 0x31de 3917#define regSQ_PERFCOUNTER15_LO_BASE_IDX 1 3918#define regSQ_PERFCOUNTER15_HI 0x31df 3919#define regSQ_PERFCOUNTER15_HI_BASE_IDX 1 3920#define regSX_PERFCOUNTER0_LO 0x3240 3921#define regSX_PERFCOUNTER0_LO_BASE_IDX 1 3922#define regSX_PERFCOUNTER0_HI 0x3241 3923#define regSX_PERFCOUNTER0_HI_BASE_IDX 1 3924#define regSX_PERFCOUNTER1_LO 0x3242 3925#define regSX_PERFCOUNTER1_LO_BASE_IDX 1 3926#define regSX_PERFCOUNTER1_HI 0x3243 3927#define regSX_PERFCOUNTER1_HI_BASE_IDX 1 3928#define regSX_PERFCOUNTER2_LO 0x3244 3929#define regSX_PERFCOUNTER2_LO_BASE_IDX 1 3930#define regSX_PERFCOUNTER2_HI 0x3245 3931#define regSX_PERFCOUNTER2_HI_BASE_IDX 1 3932#define regSX_PERFCOUNTER3_LO 0x3246 3933#define regSX_PERFCOUNTER3_LO_BASE_IDX 1 3934#define regSX_PERFCOUNTER3_HI 0x3247 3935#define regSX_PERFCOUNTER3_HI_BASE_IDX 1 3936#define regGDS_PERFCOUNTER0_LO 0x3280 3937#define regGDS_PERFCOUNTER0_LO_BASE_IDX 1 3938#define regGDS_PERFCOUNTER0_HI 0x3281 3939#define regGDS_PERFCOUNTER0_HI_BASE_IDX 1 3940#define regGDS_PERFCOUNTER1_LO 0x3282 3941#define regGDS_PERFCOUNTER1_LO_BASE_IDX 1 3942#define regGDS_PERFCOUNTER1_HI 0x3283 3943#define regGDS_PERFCOUNTER1_HI_BASE_IDX 1 3944#define regGDS_PERFCOUNTER2_LO 0x3284 3945#define regGDS_PERFCOUNTER2_LO_BASE_IDX 1 3946#define regGDS_PERFCOUNTER2_HI 0x3285 3947#define regGDS_PERFCOUNTER2_HI_BASE_IDX 1 3948#define regGDS_PERFCOUNTER3_LO 0x3286 3949#define regGDS_PERFCOUNTER3_LO_BASE_IDX 1 3950#define regGDS_PERFCOUNTER3_HI 0x3287 3951#define regGDS_PERFCOUNTER3_HI_BASE_IDX 1 3952#define regTA_PERFCOUNTER0_LO 0x32c0 3953#define regTA_PERFCOUNTER0_LO_BASE_IDX 1 3954#define regTA_PERFCOUNTER0_HI 0x32c1 3955#define regTA_PERFCOUNTER0_HI_BASE_IDX 1 3956#define regTA_PERFCOUNTER1_LO 0x32c2 3957#define regTA_PERFCOUNTER1_LO_BASE_IDX 1 3958#define regTA_PERFCOUNTER1_HI 0x32c3 3959#define regTA_PERFCOUNTER1_HI_BASE_IDX 1 3960#define regTD_PERFCOUNTER0_LO 0x3300 3961#define regTD_PERFCOUNTER0_LO_BASE_IDX 1 3962#define regTD_PERFCOUNTER0_HI 0x3301 3963#define regTD_PERFCOUNTER0_HI_BASE_IDX 1 3964#define regTD_PERFCOUNTER1_LO 0x3302 3965#define regTD_PERFCOUNTER1_LO_BASE_IDX 1 3966#define regTD_PERFCOUNTER1_HI 0x3303 3967#define regTD_PERFCOUNTER1_HI_BASE_IDX 1 3968#define regTCP_PERFCOUNTER0_LO 0x3340 3969#define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 3970#define regTCP_PERFCOUNTER0_HI 0x3341 3971#define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 3972#define regTCP_PERFCOUNTER1_LO 0x3342 3973#define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 3974#define regTCP_PERFCOUNTER1_HI 0x3343 3975#define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 3976#define regTCP_PERFCOUNTER2_LO 0x3344 3977#define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 3978#define regTCP_PERFCOUNTER2_HI 0x3345 3979#define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 3980#define regTCP_PERFCOUNTER3_LO 0x3346 3981#define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 3982#define regTCP_PERFCOUNTER3_HI 0x3347 3983#define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 3984#define regTCC_PERFCOUNTER0_LO 0x3380 3985#define regTCC_PERFCOUNTER0_LO_BASE_IDX 1 3986#define regTCC_PERFCOUNTER0_HI 0x3381 3987#define regTCC_PERFCOUNTER0_HI_BASE_IDX 1 3988#define regTCC_PERFCOUNTER1_LO 0x3382 3989#define regTCC_PERFCOUNTER1_LO_BASE_IDX 1 3990#define regTCC_PERFCOUNTER1_HI 0x3383 3991#define regTCC_PERFCOUNTER1_HI_BASE_IDX 1 3992#define regTCC_PERFCOUNTER2_LO 0x3384 3993#define regTCC_PERFCOUNTER2_LO_BASE_IDX 1 3994#define regTCC_PERFCOUNTER2_HI 0x3385 3995#define regTCC_PERFCOUNTER2_HI_BASE_IDX 1 3996#define regTCC_PERFCOUNTER3_LO 0x3386 3997#define regTCC_PERFCOUNTER3_LO_BASE_IDX 1 3998#define regTCC_PERFCOUNTER3_HI 0x3387 3999#define regTCC_PERFCOUNTER3_HI_BASE_IDX 1 4000#define regTCA_PERFCOUNTER0_LO 0x3390
4001#define regTCA_PERFCOUNTER0_LO_BASE_IDX 1 4002#define regTCA_PERFCOUNTER0_HI 0x3391 4003#define regTCA_PERFCOUNTER0_HI_BASE_IDX 1 4004#define regTCA_PERFCOUNTER1_LO 0x3392 4005#define regTCA_PERFCOUNTER1_LO_BASE_IDX 1 4006#define regTCA_PERFCOUNTER1_HI 0x3393 4007#define regTCA_PERFCOUNTER1_HI_BASE_IDX 1 4008#define regTCA_PERFCOUNTER2_LO 0x3394 4009#define regTCA_PERFCOUNTER2_LO_BASE_IDX 1 4010#define regTCA_PERFCOUNTER2_HI 0x3395 4011#define regTCA_PERFCOUNTER2_HI_BASE_IDX 1 4012#define regTCA_PERFCOUNTER3_LO 0x3396 4013#define regTCA_PERFCOUNTER3_LO_BASE_IDX 1 4014#define regTCA_PERFCOUNTER3_HI 0x3397 4015#define regTCA_PERFCOUNTER3_HI_BASE_IDX 1 4016#define regCB_PERFCOUNTER0_LO 0x3406 4017#define regCB_PERFCOUNTER0_LO_BASE_IDX 1 4018#define regCB_PERFCOUNTER0_HI 0x3407 4019#define regCB_PERFCOUNTER0_HI_BASE_IDX 1 4020#define regCB_PERFCOUNTER1_LO 0x3408 4021#define regCB_PERFCOUNTER1_LO_BASE_IDX 1 4022#define regCB_PERFCOUNTER1_HI 0x3409 4023#define regCB_PERFCOUNTER1_HI_BASE_IDX 1 4024#define regCB_PERFCOUNTER2_LO 0x340a 4025#define regCB_PERFCOUNTER2_LO_BASE_IDX 1 4026#define regCB_PERFCOUNTER2_HI 0x340b 4027#define regCB_PERFCOUNTER2_HI_BASE_IDX 1 4028#define regCB_PERFCOUNTER3_LO 0x340c 4029#define regCB_PERFCOUNTER3_LO_BASE_IDX 1 4030#define regCB_PERFCOUNTER3_HI 0x340d 4031#define regCB_PERFCOUNTER3_HI_BASE_IDX 1 4032#define regDB_PERFCOUNTER0_LO 0x3440 4033#define regDB_PERFCOUNTER0_LO_BASE_IDX 1 4034#define regDB_PERFCOUNTER0_HI 0x3441 4035#define regDB_PERFCOUNTER0_HI_BASE_IDX 1 4036#define regDB_PERFCOUNTER1_LO 0x3442 4037#define regDB_PERFCOUNTER1_LO_BASE_IDX 1 4038#define regDB_PERFCOUNTER1_HI 0x3443 4039#define regDB_PERFCOUNTER1_HI_BASE_IDX 1 4040#define regDB_PERFCOUNTER2_LO 0x3444 4041#define regDB_PERFCOUNTER2_LO_BASE_IDX 1 4042#define regDB_PERFCOUNTER2_HI 0x3445 4043#define regDB_PERFCOUNTER2_HI_BASE_IDX 1 4044#define regDB_PERFCOUNTER3_LO 0x3446 4045#define regDB_PERFCOUNTER3_LO_BASE_IDX 1 4046#define regDB_PERFCOUNTER3_HI 0x3447 4047#define regDB_PERFCOUNTER3_HI_BASE_IDX 1 4048#define regRLC_PERFCOUNTER0_LO 0x3480 4049#define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 4050#define regRLC_PERFCOUNTER0_HI 0x3481 4051#define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 4052#define regRLC_PERFCOUNTER1_LO 0x3482 4053#define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 4054#define regRLC_PERFCOUNTER1_HI 0x3483 4055#define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 4056#define regRMI_PERFCOUNTER0_LO 0x34c0 4057#define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 4058#define regRMI_PERFCOUNTER0_HI 0x34c1 4059#define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 4060#define regRMI_PERFCOUNTER1_LO 0x34c2 4061#define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 4062#define regRMI_PERFCOUNTER1_HI 0x34c3 4063#define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 4064#define regRMI_PERFCOUNTER2_LO 0x34c4 4065#define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 4066#define regRMI_PERFCOUNTER2_HI 0x34c5 4067#define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 4068#define regRMI_PERFCOUNTER3_LO 0x34c6 4069#define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 4070#define regRMI_PERFCOUNTER3_HI 0x34c7 4071#define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 4072 4073 4074// addressBlock: gc_perfsdec 4075// base address: 0x36000 4076#define regCPG_PERFCOUNTER1_SELECT 0x3800 4077#define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 4078#define regCPG_PERFCOUNTER0_SELECT1 0x3801 4079#define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 4080#define regCPG_PERFCOUNTER0_SELECT 0x3802 4081#define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 4082#define regCPC_PERFCOUNTER1_SELECT 0x3803 4083#define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 4084#define regCPC_PERFCOUNTER0_SELECT1 0x3804 4085#define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 4086#define regCPF_PERFCOUNTER1_SELECT 0x3805 4087#define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 4088#define regCPF_PERFCOUNTER0_SELECT1 0x3806 4089#define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 4090#define regCPF_PERFCOUNTER0_SELECT 0x3807 4091#define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 4092#define regCP_PERFMON_CNTL 0x3808 4093#define regCP_PERFMON_CNTL_BASE_IDX 1 4094#define regCPC_PERFCOUNTER0_SELECT 0x3809 4095#define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 4096#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a 4097#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 4098#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b 4099#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 4100#define regCPF_LATENCY_STATS_SELECT 0x380c 4101#define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 4102#define regCPG_LATENCY_STATS_SELECT 0x380d 4103#define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 4104#define regCPC_LATENCY_STATS_SELECT 0x380e 4105#define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 4106#define regCP_DRAW_OBJECT 0x3810 4107#define regCP_DRAW_OBJECT_BASE_IDX 1 4108#define regCP_DRAW_OBJECT_COUNTER 0x3811 4109#define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 4110#define regCP_DRAW_WINDOW_MASK_HI 0x3812 4111#define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 4112#define regCP_DRAW_WINDOW_HI 0x3813 4113#define regCP_DRAW_WINDOW_HI_BASE_IDX 1 4114#define regCP_DRAW_WINDOW_LO 0x3814 4115#define regCP_DRAW_WINDOW_LO_BASE_IDX 1 4116#define regCP_DRAW_WINDOW_CNTL 0x3815 4117#define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 4118#define regGRBM_PERFCOUNTER0_SELECT 0x3840 4119#define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 4120#define regGRBM_PERFCOUNTER1_SELECT 0x3841 4121#define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 4122#define regGRBM_SE0_PERFCOUNTER_SELECT 0x3842 4123#define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 4124#define regGRBM_SE1_PERFCOUNTER_SELECT 0x3843 4125#define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 4126#define regGRBM_SE2_PERFCOUNTER_SELECT 0x3844 4127#define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 4128#define regGRBM_SE3_PERFCOUNTER_SELECT 0x3845 4129#define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 4130#define regWD_PERFCOUNTER0_SELECT 0x3880 4131#define regWD_PERFCOUNTER0_SELECT_BASE_IDX 1 4132#define regWD_PERFCOUNTER1_SELECT 0x3881 4133#define regWD_PERFCOUNTER1_SELECT_BASE_IDX 1 4134#define regWD_PERFCOUNTER2_SELECT 0x3882 4135#define regWD_PERFCOUNTER2_SELECT_BASE_IDX 1 4136#define regWD_PERFCOUNTER3_SELECT 0x3883 4137#define regWD_PERFCOUNTER3_SELECT_BASE_IDX 1 4138#define regIA_PERFCOUNTER0_SELECT 0x3884 4139#define regIA_PERFCOUNTER0_SELECT_BASE_IDX 1 4140#define regIA_PERFCOUNTER1_SELECT 0x3885 4141#define regIA_PERFCOUNTER1_SELECT_BASE_IDX 1 4142#define regIA_PERFCOUNTER2_SELECT 0x3886 4143#define regIA_PERFCOUNTER2_SELECT_BASE_IDX 1 4144#define regIA_PERFCOUNTER3_SELECT 0x3887 4145#define regIA_PERFCOUNTER3_SELECT_BASE_IDX 1 4146#define regIA_PERFCOUNTER0_SELECT1 0x3888 4147#define regIA_PERFCOUNTER0_SELECT1_BASE_IDX 1 4148#define regVGT_PERFCOUNTER0_SELECT 0x388c 4149#define regVGT_PERFCOUNTER0_SELECT_BASE_IDX 1 4150#define regVGT_PERFCOUNTER1_SELECT 0x388d 4151#define regVGT_PERFCOUNTER1_SELECT_BASE_IDX 1 4152#define regVGT_PERFCOUNTER2_SELECT 0x388e 4153#define regVGT_PERFCOUNTER2_SELECT_BASE_IDX 1 4154#define regVGT_PERFCOUNTER3_SELECT 0x388f 4155#define regVGT_PERFCOUNTER3_SELECT_BASE_IDX 1 4156#define regVGT_PERFCOUNTER0_SELECT1 0x3890 4157#define regVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1 4158#define regVGT_PERFCOUNTER1_SELECT1 0x3891 4159#define regVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1 4160#define regVGT_PERFCOUNTER_SEID_MASK 0x3894 4161#define regVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1 4162#define regPA_SU_PERFCOUNTER0_SELECT 0x3900 4163#define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 4164#define regPA_SU_PERFCOUNTER0_SELECT1 0x3901 4165#define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 4166#define regPA_SU_PERFCOUNTER1_SELECT 0x3902 4167#define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 4168#define regPA_SU_PERFCOUNTER1_SELECT1 0x3903 4169#define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 4170#define regPA_SU_PERFCOUNTER2_SELECT 0x3904 4171#define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 4172#define regPA_SU_PERFCOUNTER3_SELECT 0x3905 4173#define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 4174#define regPA_SC_PERFCOUNTER0_SELECT 0x3940 4175#define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 4176#define regPA_SC_PERFCOUNTER0_SELECT1 0x3941 4177#define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 4178#define regPA_SC_PERFCOUNTER1_SELECT 0x3942 4179#define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 4180#define regPA_SC_PERFCOUNTER2_SELECT 0x3943 4181#define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 4182#define regPA_SC_PERFCOUNTER3_SELECT 0x3944 4183#define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 4184#define regPA_SC_PERFCOUNTER4_SELECT 0x3945 4185#define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 4186#define regPA_SC_PERFCOUNTER5_SELECT 0x3946 4187#define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 4188#define regPA_SC_PERFCOUNTER6_SELECT 0x3947 4189#define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 4190#define regPA_SC_PERFCOUNTER7_SELECT 0x3948 4191#define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 4192#define regSPI_PERFCOUNTER0_SELECT 0x3980 4193#define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 4194#define regSPI_PERFCOUNTER1_SELECT 0x3981 4195#define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 4196#define regSPI_PERFCOUNTER2_SELECT 0x3982 4197#define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 4198#define regSPI_PERFCOUNTER3_SELECT 0x3983 4199#define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 4200#define regSPI_PERFCOUNTER0_SELECT1 0x3984 4201#define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 4202#define regSPI_PERFCOUNTER1_SELECT1 0x3985 4203#define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 4204#define regSPI_PERFCOUNTER2_SELECT1 0x3986 4205#define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 4206#define regSPI_PERFCOUNTER3_SELECT1 0x3987 4207#define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 4208#define regSPI_PERFCOUNTER4_SELECT 0x3988 4209#define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 4210#define regSPI_PERFCOUNTER5_SELECT 0x3989 4211#define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 4212#define regSPI_PERFCOUNTER_BINS 0x398a 4213#define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 4214#define regSQ_PERFCOUNTER0_SELECT 0x39c0 4215#define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 4216#define regSQ_PERFCOUNTER1_SELECT 0x39c1 4217#define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 4218#define regSQ_PERFCOUNTER2_SELECT 0x39c2 4219#define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 4220#define regSQ_PERFCOUNTER3_SELECT 0x39c3 4221#define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 4222#define regSQ_PERFCOUNTER4_SELECT 0x39c4 4223#define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 4224#define regSQ_PERFCOUNTER5_SELECT 0x39c5 4225#define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 4226#define regSQ_PERFCOUNTER6_SELECT 0x39c6 4227#define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 4228#define regSQ_PERFCOUNTER7_SELECT 0x39c7 4229#define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 4230#define regSQ_PERFCOUNTER8_SELECT 0x39c8 4231#define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 4232#define regSQ_PERFCOUNTER9_SELECT 0x39c9 4233#define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 4234#define regSQ_PERFCOUNTER10_SELECT 0x39ca 4235#define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 4236#define regSQ_PERFCOUNTER11_SELECT 0x39cb 4237#define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 4238#define regSQ_PERFCOUNTER12_SELECT 0x39cc 4239#define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 4240#define regSQ_PERFCOUNTER13_SELECT 0x39cd 4241#define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 4242#define regSQ_PERFCOUNTER14_SELECT 0x39ce 4243#define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 4244#define regSQ_PERFCOUNTER15_SELECT 0x39cf 4245#define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 4246#define regSQ_PERFCOUNTER_CTRL 0x39e0 4247#define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 4248#define regSQ_PERFCOUNTER_MASK 0x39e1 4249#define regSQ_PERFCOUNTER_MASK_BASE_IDX 1 4250#define regSQ_PERFCOUNTER_CTRL2 0x39e2 4251#define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 4252#define regSX_PERFCOUNTER0_SELECT 0x3a40 4253#define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 4254#define regSX_PERFCOUNTER1_SELECT 0x3a41 4255#define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 4256#define regSX_PERFCOUNTER2_SELECT 0x3a42 4257#define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 4258#define regSX_PERFCOUNTER3_SELECT 0x3a43 4259#define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 4260#define regSX_PERFCOUNTER0_SELECT1 0x3a44 4261#define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 4262#define regSX_PERFCOUNTER1_SELECT1 0x3a45 4263#define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 4264#define regGDS_PERFCOUNTER0_SELECT 0x3a80 4265#define regGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 4266#define regGDS_PERFCOUNTER1_SELECT 0x3a81 4267#define regGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 4268#define regGDS_PERFCOUNTER2_SELECT 0x3a82 4269#define regGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 4270#define regGDS_PERFCOUNTER3_SELECT 0x3a83 4271#define regGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 4272#define regGDS_PERFCOUNTER0_SELECT1 0x3a84 4273#define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 4274#define regTA_PERFCOUNTER0_SELECT 0x3ac0 4275#define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 4276#define regTA_PERFCOUNTER0_SELECT1 0x3ac1 4277#define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 4278#define regTA_PERFCOUNTER1_SELECT 0x3ac2 4279#define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 4280#define regTD_PERFCOUNTER0_SELECT 0x3b00 4281#define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 4282#define regTD_PERFCOUNTER0_SELECT1 0x3b01 4283#define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 4284#define regTD_PERFCOUNTER1_SELECT 0x3b02 4285#define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 4286#define regTCP_PERFCOUNTER0_SELECT 0x3b40 4287#define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 4288#define regTCP_PERFCOUNTER0_SELECT1 0x3b41 4289#define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 4290#define regTCP_PERFCOUNTER1_SELECT 0x3b42 4291#define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 4292#define regTCP_PERFCOUNTER1_SELECT1 0x3b43 4293#define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 4294#define regTCP_PERFCOUNTER2_SELECT 0x3b44 4295#define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 4296#define regTCP_PERFCOUNTER3_SELECT 0x3b45 4297#define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 4298#define regTCC_PERFCOUNTER0_SELECT 0x3b80 4299#define regTCC_PERFCOUNTER0_SELECT_BASE_IDX 1 4300#define regTCC_PERFCOUNTER0_SELECT1 0x3b81 4301#define regTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1 4302#define regTCC_PERFCOUNTER1_SELECT 0x3b82 4303#define regTCC_PERFCOUNTER1_SELECT_BASE_IDX 1 4304#define regTCC_PERFCOUNTER1_SELECT1 0x3b83 4305#define regTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1 4306#define regTCC_PERFCOUNTER2_SELECT 0x3b84 4307#define regTCC_PERFCOUNTER2_SELECT_BASE_IDX 1 4308#define regTCC_PERFCOUNTER3_SELECT 0x3b85 4309#define regTCC_PERFCOUNTER3_SELECT_BASE_IDX 1 4310#define regTCA_PERFCOUNTER0_SELECT 0x3b90 4311#define regTCA_PERFCOUNTER0_SELECT_BASE_IDX 1 4312#define regTCA_PERFCOUNTER0_SELECT1 0x3b91 4313#define regTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1 4314#define regTCA_PERFCOUNTER1_SELECT 0x3b92 4315#define regTCA_PERFCOUNTER1_SELECT_BASE_IDX 1 4316#define regTCA_PERFCOUNTER1_SELECT1 0x3b93 4317#define regTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1 4318#define regTCA_PERFCOUNTER2_SELECT 0x3b94 4319#define regTCA_PERFCOUNTER2_SELECT_BASE_IDX 1 4320#define regTCA_PERFCOUNTER3_SELECT 0x3b95 4321#define regTCA_PERFCOUNTER3_SELECT_BASE_IDX 1 4322#define regCB_PERFCOUNTER_FILTER 0x3c00 4323#define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 4324#define regCB_PERFCOUNTER0_SELECT 0x3c01 4325#define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 4326#define regCB_PERFCOUNTER0_SELECT1 0x3c02 4327#define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 4328#define regCB_PERFCOUNTER1_SELECT 0x3c03 4329#define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 4330#define regCB_PERFCOUNTER2_SELECT 0x3c04 4331#define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 4332#define regCB_PERFCOUNTER3_SELECT 0x3c05 4333#define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 4334#define regDB_PERFCOUNTER0_SELECT 0x3c40 4335#define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 4336#define regDB_PERFCOUNTER0_SELECT1 0x3c41 4337#define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 4338#define regDB_PERFCOUNTER1_SELECT 0x3c42 4339#define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 4340#define regDB_PERFCOUNTER1_SELECT1 0x3c43 4341#define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 4342#define regDB_PERFCOUNTER2_SELECT 0x3c44 4343#define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 4344#define regDB_PERFCOUNTER3_SELECT 0x3c46 4345#define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 4346#define regRLC_SPM_PERFMON_CNTL 0x3c80 4347#define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 4348#define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 4349#define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 4350#define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 4351#define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 4352#define regRLC_SPM_PERFMON_RING_SIZE 0x3c83 4353#define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 4354#define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84 4355#define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 4356#define regRLC_SPM_SE_MUXSEL_ADDR 0x3c85 4357#define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 4358#define regRLC_SPM_SE_MUXSEL_DATA 0x3c86 4359#define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 4360#define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87 4361#define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4362#define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88 4363#define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4364#define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89 4365#define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4366#define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a 4367#define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4368#define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b 4369#define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4370#define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c 4371#define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4372#define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d 4373#define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4374#define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e 4375#define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4376#define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90 4377#define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4378#define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91 4379#define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4380#define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92 4381#define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4382#define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93 4383#define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4384#define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94 4385#define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4386#define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95 4387#define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4388#define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96 4389#define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4390#define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97 4391#define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4392#define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98 4393#define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4394#define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a 4395#define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4396#define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b 4397#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 4398#define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c 4399#define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 4400#define regRLC_SPM_RING_RDPTR 0x3c9d 4401#define regRLC_SPM_RING_RDPTR_BASE_IDX 1 4402#define regRLC_SPM_SEGMENT_THRESHOLD 0x3c9e 4403#define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 4404#define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3 4405#define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 4406#define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX 0x3ca4 4407#define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX 1 4408#define regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1 0x3caf 4409#define regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1_BASE_IDX 1 4410#define regRLC_PERFMON_CLK_CNTL_UCODE 0x3cbe 4411#define regRLC_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 4412#define regRLC_PERFMON_CLK_CNTL 0x3cbf 4413#define regRLC_PERFMON_CLK_CNTL_BASE_IDX 1 4414#define regRLC_PERFMON_CNTL 0x3cc0 4415#define regRLC_PERFMON_CNTL_BASE_IDX 1 4416#define regRLC_PERFCOUNTER0_SELECT 0x3cc1 4417#define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 4418#define regRLC_PERFCOUNTER1_SELECT 0x3cc2 4419#define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 4420#define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 4421#define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 4422#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 4423#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 4424#define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 4425#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 4426#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 4427#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 4428#define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 4429#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 4430#define regRMI_PERFCOUNTER0_SELECT 0x3d00 4431#define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 4432#define regRMI_PERFCOUNTER0_SELECT1 0x3d01 4433#define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 4434#define regRMI_PERFCOUNTER1_SELECT 0x3d02 4435#define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 4436#define regRMI_PERFCOUNTER2_SELECT 0x3d03 4437#define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 4438#define regRMI_PERFCOUNTER2_SELECT1 0x3d04 4439#define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 4440#define regRMI_PERFCOUNTER3_SELECT 0x3d05 4441#define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 4442#define regRMI_PERF_COUNTER_CNTL 0x3d06 4443#define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 4444 4445 4446// addressBlock: gc_pwrdec 4447// base address: 0x3c000 4448#define regCGTS_SM_CTRL_REG 0x5000 4449#define regCGTS_SM_CTRL_REG_BASE_IDX 1 4450#define regCGTS_RD_CTRL_REG 0x5001 4451#define regCGTS_RD_CTRL_REG_BASE_IDX 1 4452#define regCGTS_RD_REG 0x5002 4453#define regCGTS_RD_REG_BASE_IDX 1 4454#define regCGTS_TCC_DISABLE 0x5003 4455#define regCGTS_TCC_DISABLE_BASE_IDX 1 4456#define regCGTS_USER_TCC_DISABLE 0x5004 4457#define regCGTS_USER_TCC_DISABLE_BASE_IDX 1 4458#define regCGTS_TCC_DISABLE2 0x5005 4459#define regCGTS_TCC_DISABLE2_BASE_IDX 1 4460#define regCGTS_USER_TCC_DISABLE2 0x5006 4461#define regCGTS_USER_TCC_DISABLE2_BASE_IDX 1 4462#define regCGTS_CU0_SP0_CTRL_REG 0x5008 4463#define regCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1 4464#define regCGTS_CU0_LDS_SQ_CTRL_REG 0x5009 4465#define regCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1 4466#define regCGTS_CU0_TA_SQC_CTRL_REG 0x500a 4467#define regCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1 4468#define regCGTS_CU0_SP1_CTRL_REG 0x500b 4469#define regCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1 4470#define regCGTS_CU1_SP0_CTRL_REG 0x500d 4471#define regCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1 4472#define regCGTS_CU1_LDS_SQ_CTRL_REG 0x500e 4473#define regCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1 4474#define regCGTS_CU1_TA_SQC_CTRL_REG 0x500f 4475#define regCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1 4476#define regCGTS_CU1_SP1_CTRL_REG 0x5010 4477#define regCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1 4478#define regCGTS_CU2_SP0_CTRL_REG 0x5012 4479#define regCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1 4480#define regCGTS_CU2_LDS_SQ_CTRL_REG 0x5013 4481#define regCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1 4482#define regCGTS_CU2_TA_SQC_CTRL_REG 0x5014 4483#define regCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1 4484#define regCGTS_CU2_SP1_CTRL_REG 0x5015 4485#define regCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1 4486#define regCGTS_CU3_SP0_CTRL_REG 0x5017 4487#define regCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1 4488#define regCGTS_CU3_LDS_SQ_CTRL_REG 0x5018 4489#define regCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1 4490#define regCGTS_CU3_TA_SQC_CTRL_REG 0x5019 4491#define regCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 4492#define regCGTS_CU3_SP1_CTRL_REG 0x501a 4493#define regCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1 4494#define regCGTS_CU4_SP0_CTRL_REG 0x501c 4495#define regCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1 4496#define regCGTS_CU4_LDS_SQ_CTRL_REG 0x501d 4497#define regCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1 4498#define regCGTS_CU4_TA_SQC_CTRL_REG 0x501e 4499#define regCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1 4500#define regCGTS_CU4_SP1_CTRL_REG 0x501f 4501#define regCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1 4502#define regCGTS_CU5_SP0_CTRL_REG 0x5021 4503#define regCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1 4504#define regCGTS_CU5_LDS_SQ_CTRL_REG 0x5022 4505#define regCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1 4506#define regCGTS_CU5_TA_SQC_CTRL_REG 0x5023 4507#define regCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1 4508#define regCGTS_CU5_SP1_CTRL_REG 0x5024 4509#define regCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1 4510#define regCGTS_CU6_SP0_CTRL_REG 0x5026 4511#define regCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1 4512#define regCGTS_CU6_LDS_SQ_CTRL_REG 0x5027 4513#define regCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1 4514#define regCGTS_CU6_TA_SQC_CTRL_REG 0x5028 4515#define regCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1 4516#define regCGTS_CU6_SP1_CTRL_REG 0x5029 4517#define regCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1 4518#define regCGTS_CU7_SP0_CTRL_REG 0x502b 4519#define regCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1 4520#define regCGTS_CU7_LDS_SQ_CTRL_REG 0x502c 4521#define regCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1 4522#define regCGTS_CU7_TA_SQC_CTRL_REG 0x502d 4523#define regCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1 4524#define regCGTS_CU7_SP1_CTRL_REG 0x502e 4525#define regCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1 4526#define regCGTS_CU8_SP0_CTRL_REG 0x5030 4527#define regCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1 4528#define regCGTS_CU8_LDS_SQ_CTRL_REG 0x5031 4529#define regCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1 4530#define regCGTS_CU8_TA_SQC_CTRL_REG 0x5032 4531#define regCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1 4532#define regCGTS_CU8_SP1_CTRL_REG 0x5033 4533#define regCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1 4534#define regCGTS_CU9_SP0_CTRL_REG 0x5035 4535#define regCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1 4536#define regCGTS_CU9_LDS_SQ_CTRL_REG 0x5036 4537#define regCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1 4538#define regCGTS_CU9_TA_SQC_CTRL_REG 0x5037 4539#define regCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1 4540#define regCGTS_CU9_SP1_CTRL_REG 0x5038 4541#define regCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1 4542#define regCGTS_CU10_SP0_CTRL_REG 0x503a 4543#define regCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1 4544#define regCGTS_CU10_LDS_SQ_CTRL_REG 0x503b 4545#define regCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1 4546#define regCGTS_CU10_TA_SQC_CTRL_REG 0x503c 4547#define regCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1 4548#define regCGTS_CU10_SP1_CTRL_REG 0x503d 4549#define regCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1 4550#define regCGTS_CU11_SP0_CTRL_REG 0x503f 4551#define regCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1 4552#define regCGTS_CU11_LDS_SQ_CTRL_REG 0x5040 4553#define regCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1 4554#define regCGTS_CU11_TA_SQC_CTRL_REG 0x5041 4555#define regCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1 4556#define regCGTS_CU11_SP1_CTRL_REG 0x5042 4557#define regCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1 4558#define regCGTS_CU12_SP0_CTRL_REG 0x5044 4559#define regCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1 4560#define regCGTS_CU12_LDS_SQ_CTRL_REG 0x5045 4561#define regCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1 4562#define regCGTS_CU12_TA_SQC_CTRL_REG 0x5046 4563#define regCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1 4564#define regCGTS_CU12_SP1_CTRL_REG 0x5047 4565#define regCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1 4566#define regCGTS_CU13_SP0_CTRL_REG 0x5049 4567#define regCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1 4568#define regCGTS_CU13_LDS_SQ_CTRL_REG 0x504a 4569#define regCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1 4570#define regCGTS_CU13_TA_SQC_CTRL_REG 0x504b 4571#define regCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1 4572#define regCGTS_CU13_SP1_CTRL_REG 0x504c 4573#define regCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1 4574#define regCGTS_CU14_SP0_CTRL_REG 0x504e 4575#define regCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1 4576#define regCGTS_CU14_LDS_SQ_CTRL_REG 0x504f 4577#define regCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1 4578#define regCGTS_CU14_TA_SQC_CTRL_REG 0x5050 4579#define regCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1 4580#define regCGTS_CU14_SP1_CTRL_REG 0x5051 4581#define regCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1 4582#define regCGTS_CU15_SP0_CTRL_REG 0x5053 4583#define regCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1 4584#define regCGTS_CU15_LDS_SQ_CTRL_REG 0x5054 4585#define regCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1 4586#define regCGTS_CU15_TA_SQC_CTRL_REG 0x5055 4587#define regCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1 4588#define regCGTS_CU15_SP1_CTRL_REG 0x5056 4589#define regCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1 4590#define regCGTS_CU0_TCPI_CTRL_REG 0x5058 4591#define regCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1 4592#define regCGTS_CU1_TCPI_CTRL_REG 0x5059 4593#define regCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1 4594#define regCGTS_CU2_TCPI_CTRL_REG 0x505a 4595#define regCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1 4596#define regCGTS_CU3_TCPI_CTRL_REG 0x505b 4597#define regCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1 4598#define regCGTS_CU4_TCPI_CTRL_REG 0x505c 4599#define regCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1 4600#define regCGTS_CU5_TCPI_CTRL_REG 0x505d 4601#define regCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1 4602#define regCGTS_CU6_TCPI_CTRL_REG 0x505e 4603#define regCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1 4604#define regCGTS_CU7_TCPI_CTRL_REG 0x505f 4605#define regCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1 4606#define regCGTS_CU8_TCPI_CTRL_REG 0x5060 4607#define regCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1 4608#define regCGTS_CU9_TCPI_CTRL_REG 0x5061 4609#define regCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1 4610#define regCGTS_CU10_TCPI_CTRL_REG 0x5062 4611#define regCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1 4612#define regCGTS_CU11_TCPI_CTRL_REG 0x5063 4613#define regCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1 4614#define regCGTS_CU12_TCPI_CTRL_REG 0x5064 4615#define regCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1 4616#define regCGTS_CU13_TCPI_CTRL_REG 0x5065 4617#define regCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1 4618#define regCGTS_CU14_TCPI_CTRL_REG 0x5066 4619#define regCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1 4620#define regCGTS_CU15_TCPI_CTRL_REG 0x5067 4621#define regCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1 4622#define regCGTT_SPI_PS_CLK_CTRL 0x507d 4623#define regCGTT_SPI_PS_CLK_CTRL_BASE_IDX 1 4624#define regCGTT_SPIS_CLK_CTRL 0x507e 4625#define regCGTT_SPIS_CLK_CTRL_BASE_IDX 1 4626#define regCGTT_SPI_CLK_CTRL 0x5080 4627#define regCGTT_SPI_CLK_CTRL_BASE_IDX 1 4628#define regCGTT_PC_CLK_CTRL 0x5081 4629#define regCGTT_PC_CLK_CTRL_BASE_IDX 1 4630#define regCGTT_BCI_CLK_CTRL 0x5082 4631#define regCGTT_BCI_CLK_CTRL_BASE_IDX 1 4632#define regCGTT_PA_CLK_CTRL 0x5088 4633#define regCGTT_PA_CLK_CTRL_BASE_IDX 1 4634#define regCGTT_SC_CLK_CTRL0 0x5089 4635#define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 4636#define regCGTT_SC_CLK_CTRL1 0x508a 4637#define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 4638#define regCGTT_SC_CLK_CTRL2 0x508b 4639#define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 4640#define regCGTT_SQG_CLK_CTRL 0x508d 4641#define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 4642#define regSQ_ALU_CLK_CTRL 0x508e 4643#define regSQ_ALU_CLK_CTRL_BASE_IDX 1 4644#define regSQ_TEX_CLK_CTRL 0x508f 4645#define regSQ_TEX_CLK_CTRL_BASE_IDX 1 4646#define regSQ_LDS_CLK_CTRL 0x5090 4647#define regSQ_LDS_CLK_CTRL_BASE_IDX 1 4648#define regSQ_POWER_THROTTLE 0x5091 4649#define regSQ_POWER_THROTTLE_BASE_IDX 1 4650#define regSQ_POWER_THROTTLE2 0x5092 4651#define regSQ_POWER_THROTTLE2_BASE_IDX 1 4652#define regCGTT_SX_CLK_CTRL0 0x5094 4653#define regCGTT_SX_CLK_CTRL0_BASE_IDX 1 4654#define regCGTT_SX_CLK_CTRL1 0x5095 4655#define regCGTT_SX_CLK_CTRL1_BASE_IDX 1 4656#define regCGTT_SX_CLK_CTRL2 0x5096 4657#define regCGTT_SX_CLK_CTRL2_BASE_IDX 1 4658#define regCGTT_SX_CLK_CTRL3 0x5097 4659#define regCGTT_SX_CLK_CTRL3_BASE_IDX 1 4660#define regCGTT_SX_CLK_CTRL4 0x5098 4661#define regCGTT_SX_CLK_CTRL4_BASE_IDX 1 4662#define regTD_CGTT_CTRL 0x509c 4663#define regTD_CGTT_CTRL_BASE_IDX 1 4664#define regTA_CGTT_CTRL 0x509d 4665#define regTA_CGTT_CTRL_BASE_IDX 1 4666#define regCGTT_TCI_CLK_CTRL 0x509f 4667#define regCGTT_TCI_CLK_CTRL_BASE_IDX 1 4668#define regCGTT_GDS_CLK_CTRL 0x50a0 4669#define regCGTT_GDS_CLK_CTRL_BASE_IDX 1 4670#define regCGTT_TCP_TCR_CLK_CTRL 0x50a1 4671#define regCGTT_TCP_TCR_CLK_CTRL_BASE_IDX 1 4672#define regCGTT_TCI_TCR_CLK_CTRL 0x50a2 4673#define regCGTT_TCI_TCR_CLK_CTRL_BASE_IDX 1 4674#define regTCX_CGTT_SCLK_CTRL 0x50a3 4675#define regTCX_CGTT_SCLK_CTRL_BASE_IDX 1 4676#define regDB_CGTT_CLK_CTRL_0 0x50a4 4677#define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 4678#define regCB_CGTT_SCLK_CTRL 0x50a8 4679#define regCB_CGTT_SCLK_CTRL_BASE_IDX 1 4680#define regTCC_CGTT_SCLK_CTRL 0x50ac 4681#define regTCC_CGTT_SCLK_CTRL_BASE_IDX 1 4682#define regTCC_CGTT_SCLK_CTRL2 0x50ad 4683#define regTCC_CGTT_SCLK_CTRL2_BASE_IDX 1 4684#define regTCC_CGTT_SCLK_CTRL3 0x50ae 4685#define regTCC_CGTT_SCLK_CTRL3_BASE_IDX 1 4686#define regTCA_CGTT_SCLK_CTRL 0x50af 4687#define regTCA_CGTT_SCLK_CTRL_BASE_IDX 1 4688#define regCGTT_CP_CLK_CTRL 0x50b0 4689#define regCGTT_CP_CLK_CTRL_BASE_IDX 1 4690#define regCGTT_CPF_CLK_CTRL 0x50b1 4691#define regCGTT_CPF_CLK_CTRL_BASE_IDX 1 4692#define regCGTT_CPC_CLK_CTRL 0x50b2 4693#define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 4694#define regCGTT_RLC_CLK_CTRL 0x50b5 4695#define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 4696#define regRLC_GFX_RM_CNTL 0x50b6 4697#define regRLC_GFX_RM_CNTL_BASE_IDX 1 4698#define regRMI_CGTT_SCLK_CTRL 0x50c0 4699#define regRMI_CGTT_SCLK_CTRL_BASE_IDX 1 4700#define regSE_CAC_CGTT_CLK_CTRL 0x50d0 4701#define regSE_CAC_CGTT_CLK_CTRL_BASE_IDX 1 4702#define regGC_CAC_CGTT_CLK_CTRL 0x50d8 4703#define regGC_CAC_CGTT_CLK_CTRL_BASE_IDX 1 4704#define regGRBM_CGTT_CLK_CNTL 0x50e0 4705#define regGRBM_CGTT_CLK_CNTL_BASE_IDX 1 4706 4707 4708// addressBlock: gc_rbdec 4709// base address: 0x9800 4710#define regDB_DEBUG 0x060c 4711#define regDB_DEBUG_BASE_IDX 0 4712#define regDB_DEBUG2 0x060d 4713#define regDB_DEBUG2_BASE_IDX 0 4714#define regDB_DEBUG3 0x060e 4715#define regDB_DEBUG3_BASE_IDX 0 4716#define regDB_DEBUG4 0x060f 4717#define regDB_DEBUG4_BASE_IDX 0 4718#define regDB_CREDIT_LIMIT 0x0614 4719#define regDB_CREDIT_LIMIT_BASE_IDX 0 4720#define regDB_WATERMARKS 0x0615 4721#define regDB_WATERMARKS_BASE_IDX 0 4722#define regDB_SUBTILE_CONTROL 0x0616 4723#define regDB_SUBTILE_CONTROL_BASE_IDX 0 4724#define regDB_FREE_CACHELINES 0x0617 4725#define regDB_FREE_CACHELINES_BASE_IDX 0 4726#define regDB_FIFO_DEPTH1 0x0618 4727#define regDB_FIFO_DEPTH1_BASE_IDX 0 4728#define regDB_FIFO_DEPTH2 0x0619 4729#define regDB_FIFO_DEPTH2_BASE_IDX 0 4730#define regDB_EXCEPTION_CONTROL 0x061a 4731#define regDB_EXCEPTION_CONTROL_BASE_IDX 0 4732#define regDB_RING_CONTROL 0x061b 4733#define regDB_RING_CONTROL_BASE_IDX 0 4734#define regDB_MEM_ARB_WATERMARKS 0x061c 4735#define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 4736#define regDB_RMI_CACHE_POLICY 0x061e 4737#define regDB_RMI_CACHE_POLICY_BASE_IDX 0 4738#define regDB_DFSM_CONFIG 0x0630 4739#define regDB_DFSM_CONFIG_BASE_IDX 0 4740#define regDB_DFSM_WATERMARK 0x0631 4741#define regDB_DFSM_WATERMARK_BASE_IDX 0 4742#define regDB_DFSM_TILES_IN_FLIGHT 0x0632 4743#define regDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 4744#define regDB_DFSM_PRIMS_IN_FLIGHT 0x0633 4745#define regDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 4746#define regDB_DFSM_WATCHDOG 0x0634 4747#define regDB_DFSM_WATCHDOG_BASE_IDX 0 4748#define regDB_DFSM_FLUSH_ENABLE 0x0635 4749#define regDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 4750#define regDB_DFSM_FLUSH_AUX_EVENT 0x0636 4751#define regDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 4752#define regCC_RB_REDUNDANCY 0x063c 4753#define regCC_RB_REDUNDANCY_BASE_IDX 0 4754#define regCC_RB_BACKEND_DISABLE 0x063d 4755#define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 4756#define regGB_ADDR_CONFIG 0x063e 4757#define regGB_ADDR_CONFIG_BASE_IDX 0 4758#define regGB_BACKEND_MAP 0x063f 4759#define regGB_BACKEND_MAP_BASE_IDX 0 4760#define regGB_GPU_ID 0x0640 4761#define regGB_GPU_ID_BASE_IDX 0 4762#define regCC_RB_DAISY_CHAIN 0x0641 4763#define regCC_RB_DAISY_CHAIN_BASE_IDX 0 4764#define regGB_ADDR_CONFIG_READ 0x0642 4765#define regGB_ADDR_CONFIG_READ_BASE_IDX 0 4766#define regGB_TILE_MODE0 0x0644 4767#define regGB_TILE_MODE0_BASE_IDX 0 4768#define regGB_TILE_MODE1 0x0645 4769#define regGB_TILE_MODE1_BASE_IDX 0 4770#define regGB_TILE_MODE2 0x0646 4771#define regGB_TILE_MODE2_BASE_IDX 0 4772#define regGB_TILE_MODE3 0x0647 4773#define regGB_TILE_MODE3_BASE_IDX 0 4774#define regGB_TILE_MODE4 0x0648 4775#define regGB_TILE_MODE4_BASE_IDX 0 4776#define regGB_TILE_MODE5 0x0649 4777#define regGB_TILE_MODE5_BASE_IDX 0 4778#define regGB_TILE_MODE6 0x064a 4779#define regGB_TILE_MODE6_BASE_IDX 0 4780#define regGB_TILE_MODE7 0x064b 4781#define regGB_TILE_MODE7_BASE_IDX 0 4782#define regGB_TILE_MODE8 0x064c 4783#define regGB_TILE_MODE8_BASE_IDX 0 4784#define regGB_TILE_MODE9 0x064d 4785#define regGB_TILE_MODE9_BASE_IDX 0 4786#define regGB_TILE_MODE10 0x064e 4787#define regGB_TILE_MODE10_BASE_IDX 0 4788#define regGB_TILE_MODE11 0x064f 4789#define regGB_TILE_MODE11_BASE_IDX 0 4790#define regGB_TILE_MODE12 0x0650 4791#define regGB_TILE_MODE12_BASE_IDX 0 4792#define regGB_TILE_MODE13 0x0651 4793#define regGB_TILE_MODE13_BASE_IDX 0 4794#define regGB_TILE_MODE14 0x0652 4795#define regGB_TILE_MODE14_BASE_IDX 0 4796#define regGB_TILE_MODE15 0x0653 4797#define regGB_TILE_MODE15_BASE_IDX 0 4798#define regGB_TILE_MODE16 0x0654 4799#define regGB_TILE_MODE16_BASE_IDX 0 4800#define regGB_TILE_MODE17 0x0655 4801#define regGB_TILE_MODE17_BASE_IDX 0 4802#define regGB_TILE_MODE18 0x0656 4803#define regGB_TILE_MODE18_BASE_IDX 0 4804#define regGB_TILE_MODE19 0x0657 4805#define regGB_TILE_MODE19_BASE_IDX 0 4806#define regGB_TILE_MODE20 0x0658 4807#define regGB_TILE_MODE20_BASE_IDX 0 4808#define regGB_TILE_MODE21 0x0659 4809#define regGB_TILE_MODE21_BASE_IDX 0 4810#define regGB_TILE_MODE22 0x065a 4811#define regGB_TILE_MODE22_BASE_IDX 0 4812#define regGB_TILE_MODE23 0x065b 4813#define regGB_TILE_MODE23_BASE_IDX 0 4814#define regGB_TILE_MODE24 0x065c 4815#define regGB_TILE_MODE24_BASE_IDX 0 4816#define regGB_TILE_MODE25 0x065d 4817#define regGB_TILE_MODE25_BASE_IDX 0 4818#define regGB_TILE_MODE26 0x065e 4819#define regGB_TILE_MODE26_BASE_IDX 0 4820#define regGB_TILE_MODE27 0x065f 4821#define regGB_TILE_MODE27_BASE_IDX 0 4822#define regGB_TILE_MODE28 0x0660 4823#define regGB_TILE_MODE28_BASE_IDX 0 4824#define regGB_TILE_MODE29 0x0661 4825#define regGB_TILE_MODE29_BASE_IDX 0 4826#define regGB_TILE_MODE30 0x0662 4827#define regGB_TILE_MODE30_BASE_IDX 0 4828#define regGB_TILE_MODE31 0x0663 4829#define regGB_TILE_MODE31_BASE_IDX 0 4830#define regGB_MACROTILE_MODE0 0x0664 4831#define regGB_MACROTILE_MODE0_BASE_IDX 0 4832#define regGB_MACROTILE_MODE1 0x0665 4833#define regGB_MACROTILE_MODE1_BASE_IDX 0 4834#define regGB_MACROTILE_MODE2 0x0666 4835#define regGB_MACROTILE_MODE2_BASE_IDX 0 4836#define regGB_MACROTILE_MODE3 0x0667 4837#define regGB_MACROTILE_MODE3_BASE_IDX 0 4838#define regGB_MACROTILE_MODE4 0x0668 4839#define regGB_MACROTILE_MODE4_BASE_IDX 0 4840#define regGB_MACROTILE_MODE5 0x0669 4841#define regGB_MACROTILE_MODE5_BASE_IDX 0 4842#define regGB_MACROTILE_MODE6 0x066a 4843#define regGB_MACROTILE_MODE6_BASE_IDX 0 4844#define regGB_MACROTILE_MODE7 0x066b 4845#define regGB_MACROTILE_MODE7_BASE_IDX 0 4846#define regGB_MACROTILE_MODE8 0x066c 4847#define regGB_MACROTILE_MODE8_BASE_IDX 0 4848#define regGB_MACROTILE_MODE9 0x066d 4849#define regGB_MACROTILE_MODE9_BASE_IDX 0 4850#define regGB_MACROTILE_MODE10 0x066e 4851#define regGB_MACROTILE_MODE10_BASE_IDX 0 4852#define regGB_MACROTILE_MODE11 0x066f 4853#define regGB_MACROTILE_MODE11_BASE_IDX 0 4854#define regGB_MACROTILE_MODE12 0x0670 4855#define regGB_MACROTILE_MODE12_BASE_IDX 0 4856#define regGB_MACROTILE_MODE13 0x0671 4857#define regGB_MACROTILE_MODE13_BASE_IDX 0 4858#define regGB_MACROTILE_MODE14 0x0672 4859#define regGB_MACROTILE_MODE14_BASE_IDX 0 4860#define regGB_MACROTILE_MODE15 0x0673 4861#define regGB_MACROTILE_MODE15_BASE_IDX 0 4862#define regCB_HW_CONTROL 0x0680 4863#define regCB_HW_CONTROL_BASE_IDX 0 4864#define regCB_HW_CONTROL_1 0x0681 4865#define regCB_HW_CONTROL_1_BASE_IDX 0 4866#define regCB_HW_CONTROL_2 0x0682 4867#define regCB_HW_CONTROL_2_BASE_IDX 0 4868#define regCB_HW_CONTROL_3 0x0683 4869#define regCB_HW_CONTROL_3_BASE_IDX 0 4870#define regCB_HW_MEM_ARBITER_RD 0x0686 4871#define regCB_HW_MEM_ARBITER_RD_BASE_IDX 0 4872#define regCB_HW_MEM_ARBITER_WR 0x0687 4873#define regCB_HW_MEM_ARBITER_WR_BASE_IDX 0 4874#define regCB_DCC_CONFIG 0x0688 4875#define regCB_DCC_CONFIG_BASE_IDX 0 4876#define regGC_USER_RB_REDUNDANCY 0x06de 4877#define regGC_USER_RB_REDUNDANCY_BASE_IDX 0 4878#define regGC_USER_RB_BACKEND_DISABLE 0x06df 4879#define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 4880 4881 4882// addressBlock: gc_rlcpdec 4883// base address: 0x3b000 4884#define regRLC_CNTL 0x4c00 4885#define regRLC_CNTL_BASE_IDX 1 4886#define regRLC_STAT 0x4c04 4887#define regRLC_STAT_BASE_IDX 1 4888#define regRLC_SAFE_MODE 0x4c05 4889#define regRLC_SAFE_MODE_BASE_IDX 1 4890#define regRLC_MEM_SLP_CNTL 0x4c06 4891#define regRLC_MEM_SLP_CNTL_BASE_IDX 1 4892#define regRLC_RLCV_SAFE_MODE 0x4c08 4893#define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 4894#define regRLC_RLCV_COMMAND 0x4c0a 4895#define regRLC_RLCV_COMMAND_BASE_IDX 1 4896#define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c 4897#define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 4898#define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d 4899#define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 4900#define regRLC_GPM_TIMER_INT_0 0x4c0e 4901#define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 4902#define regRLC_GPM_TIMER_INT_1 0x4c0f 4903#define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 4904#define regRLC_GPM_TIMER_INT_2 0x4c10 4905#define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 4906#define regRLC_GPM_TIMER_CTRL 0x4c11 4907#define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 4908#define regRLC_LB_CNTR_MAX 0x4c12 4909#define regRLC_LB_CNTR_MAX_BASE_IDX 1 4910#define regRLC_GPM_TIMER_STAT 0x4c13 4911#define regRLC_GPM_TIMER_STAT_BASE_IDX 1 4912#define regRLC_GPM_TIMER_INT_3 0x4c15 4913#define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 4914#define regRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16 4915#define regRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1 4916#define regRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17 4917#define regRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1 4918#define regRLC_INT_STAT 0x4c18 4919#define regRLC_INT_STAT_BASE_IDX 1 4920#define regRLC_LB_CNTL 0x4c19 4921#define regRLC_LB_CNTL_BASE_IDX 1 4922#define regRLC_MGCG_CTRL 0x4c1a 4923#define regRLC_MGCG_CTRL_BASE_IDX 1 4924#define regRLC_LB_CNTR_INIT 0x4c1b 4925#define regRLC_LB_CNTR_INIT_BASE_IDX 1 4926#define regRLC_LOAD_BALANCE_CNTR 0x4c1c 4927#define regRLC_LOAD_BALANCE_CNTR_BASE_IDX 1 4928#define regRLC_JUMP_TABLE_RESTORE 0x4c1e 4929#define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 4930#define regRLC_PG_DELAY_2 0x4c1f 4931#define regRLC_PG_DELAY_2_BASE_IDX 1 4932#define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24 4933#define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 4934#define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25 4935#define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 4936#define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 4937#define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 4938#define regRLC_UCODE_CNTL 0x4c27 4939#define regRLC_UCODE_CNTL_BASE_IDX 1 4940#define regRLC_GPM_THREAD_RESET 0x4c28 4941#define regRLC_GPM_THREAD_RESET_BASE_IDX 1 4942#define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 4943#define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 4944#define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a 4945#define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 4946#define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 4947#define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 4948#define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 4949#define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 4950#define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32 4951#define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 4952#define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33 4953#define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 4954#define regRLC_CLK_COUNT_CTRL 0x4c34 4955#define regRLC_CLK_COUNT_CTRL_BASE_IDX 1 4956#define regRLC_CLK_COUNT_STAT 0x4c35 4957#define regRLC_CLK_COUNT_STAT_BASE_IDX 1 4958#define regRLC_GPM_STAT 0x4c40 4959#define regRLC_GPM_STAT_BASE_IDX 1 4960#define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41 4961#define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 4962#define regRLC_GPU_CLOCK_32 0x4c42 4963#define regRLC_GPU_CLOCK_32_BASE_IDX 1 4964#define regRLC_PG_CNTL 0x4c43 4965#define regRLC_PG_CNTL_BASE_IDX 1 4966#define regRLC_GPM_THREAD_PRIORITY 0x4c44 4967#define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 4968#define regRLC_GPM_THREAD_ENABLE 0x4c45 4969#define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1 4970#define regRLC_CGTT_MGCG_OVERRIDE 0x4c48 4971#define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 4972#define regRLC_CGCG_CGLS_CTRL 0x4c49 4973#define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1 4974#define regRLC_CGCG_RAMP_CTRL 0x4c4a 4975#define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1 4976#define regRLC_DYN_PG_STATUS 0x4c4b 4977#define regRLC_DYN_PG_STATUS_BASE_IDX 1 4978#define regRLC_DYN_PG_REQUEST 0x4c4c 4979#define regRLC_DYN_PG_REQUEST_BASE_IDX 1 4980#define regRLC_PG_DELAY 0x4c4d 4981#define regRLC_PG_DELAY_BASE_IDX 1 4982#define regRLC_CU_STATUS 0x4c4e 4983#define regRLC_CU_STATUS_BASE_IDX 1 4984#define regRLC_LB_INIT_CU_MASK 0x4c4f 4985#define regRLC_LB_INIT_CU_MASK_BASE_IDX 1 4986#define regRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50 4987#define regRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1 4988#define regRLC_LB_PARAMS 0x4c51 4989#define regRLC_LB_PARAMS_BASE_IDX 1 4990#define regRLC_THREAD1_DELAY 0x4c52 4991#define regRLC_THREAD1_DELAY_BASE_IDX 1 4992#define regRLC_PG_ALWAYS_ON_CU_MASK 0x4c53 4993#define regRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1 4994#define regRLC_MAX_PG_CU 0x4c54 4995#define regRLC_MAX_PG_CU_BASE_IDX 1 4996#define regRLC_AUTO_PG_CTRL 0x4c55 4997#define regRLC_AUTO_PG_CTRL_BASE_IDX 1 4998#define regRLC_SERDES_RD_PENDING 0x4c58 4999#define regRLC_SERDES_RD_PENDING_BASE_IDX 1 5000#define regRLC_SERDES_RD_MASTER_INDEX 0x4c59
5001#define regRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1 5002#define regRLC_SERDES_RD_DATA_0 0x4c5a 5003#define regRLC_SERDES_RD_DATA_0_BASE_IDX 1 5004#define regRLC_SERDES_RD_DATA_1 0x4c5b 5005#define regRLC_SERDES_RD_DATA_1_BASE_IDX 1 5006#define regRLC_SERDES_RD_DATA_2 0x4c5c 5007#define regRLC_SERDES_RD_DATA_2_BASE_IDX 1 5008#define regRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d 5009#define regRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1 5010#define regRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e 5011#define regRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1 5012#define regRLC_SERDES_WR_CTRL 0x4c5f 5013#define regRLC_SERDES_WR_CTRL_BASE_IDX 1 5014#define regRLC_SERDES_WR_DATA 0x4c60 5015#define regRLC_SERDES_WR_DATA_BASE_IDX 1 5016#define regRLC_SERDES_CU_MASTER_BUSY 0x4c61 5017#define regRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1 5018#define regRLC_SERDES_NONCU_MASTER_BUSY 0x4c62 5019#define regRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1 5020#define regRLC_GPM_GENERAL_0 0x4c63 5021#define regRLC_GPM_GENERAL_0_BASE_IDX 1 5022#define regRLC_GPM_GENERAL_1 0x4c64 5023#define regRLC_GPM_GENERAL_1_BASE_IDX 1 5024#define regRLC_GPM_GENERAL_2 0x4c65 5025#define regRLC_GPM_GENERAL_2_BASE_IDX 1 5026#define regRLC_GPM_GENERAL_3 0x4c66 5027#define regRLC_GPM_GENERAL_3_BASE_IDX 1 5028#define regRLC_GPM_GENERAL_4 0x4c67 5029#define regRLC_GPM_GENERAL_4_BASE_IDX 1 5030#define regRLC_GPM_GENERAL_5 0x4c68 5031#define regRLC_GPM_GENERAL_5_BASE_IDX 1 5032#define regRLC_GPM_GENERAL_6 0x4c69 5033#define regRLC_GPM_GENERAL_6_BASE_IDX 1 5034#define regRLC_GPM_GENERAL_7 0x4c6a 5035#define regRLC_GPM_GENERAL_7_BASE_IDX 1 5036#define regRLC_GPM_SCRATCH_ADDR 0x4c6c 5037#define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 5038#define regRLC_GPM_SCRATCH_DATA 0x4c6d 5039#define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1 5040#define regRLC_STATIC_PG_STATUS 0x4c6e 5041#define regRLC_STATIC_PG_STATUS_BASE_IDX 1 5042#define regRLC_SPM_MC_CNTL 0x4c71 5043#define regRLC_SPM_MC_CNTL_BASE_IDX 1 5044#define regRLC_SPM_INT_CNTL 0x4c72 5045#define regRLC_SPM_INT_CNTL_BASE_IDX 1 5046#define regRLC_SPM_INT_STATUS 0x4c73 5047#define regRLC_SPM_INT_STATUS_BASE_IDX 1 5048#define regRLC_GPM_LOG_SIZE 0x4c77 5049#define regRLC_GPM_LOG_SIZE_BASE_IDX 1 5050#define regRLC_PG_DELAY_3 0x4c78 5051#define regRLC_PG_DELAY_3_BASE_IDX 1 5052#define regRLC_GPR_REG1 0x4c79 5053#define regRLC_GPR_REG1_BASE_IDX 1 5054#define regRLC_GPR_REG2 0x4c7a 5055#define regRLC_GPR_REG2_BASE_IDX 1 5056#define regRLC_GPM_LOG_CONT 0x4c7b 5057#define regRLC_GPM_LOG_CONT_BASE_IDX 1 5058#define regRLC_GPM_INT_DISABLE_TH0 0x4c7c 5059#define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 5060#define regRLC_GPM_INT_FORCE_TH0 0x4c7e 5061#define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 5062#define regRLC_GPM_INT_FORCE_TH1 0x4c7f 5063#define regRLC_GPM_INT_FORCE_TH1_BASE_IDX 1 5064#define regRLC_SRM_CNTL 0x4c80 5065#define regRLC_SRM_CNTL_BASE_IDX 1 5066#define regRLC_SRM_ARAM_ADDR 0x4c83 5067#define regRLC_SRM_ARAM_ADDR_BASE_IDX 1 5068#define regRLC_SRM_ARAM_DATA 0x4c84 5069#define regRLC_SRM_ARAM_DATA_BASE_IDX 1 5070#define regRLC_SRM_DRAM_ADDR 0x4c85 5071#define regRLC_SRM_DRAM_ADDR_BASE_IDX 1 5072#define regRLC_SRM_DRAM_DATA 0x4c86 5073#define regRLC_SRM_DRAM_DATA_BASE_IDX 1 5074#define regRLC_SRM_GPM_COMMAND 0x4c87 5075#define regRLC_SRM_GPM_COMMAND_BASE_IDX 1 5076#define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88 5077#define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 5078#define regRLC_SRM_RLCV_COMMAND 0x4c89 5079#define regRLC_SRM_RLCV_COMMAND_BASE_IDX 1 5080#define regRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a 5081#define regRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1 5082#define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b 5083#define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 5084#define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c 5085#define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 5086#define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d 5087#define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 5088#define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e 5089#define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 5090#define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f 5091#define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 5092#define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 5093#define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 5094#define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 5095#define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 5096#define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 5097#define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 5098#define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 5099#define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 5100#define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 5101#define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 5102#define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 5103#define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 5104#define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 5105#define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 5106#define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 5107#define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 5108#define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 5109#define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 5110#define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 5111#define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 5112#define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a 5113#define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 5114#define regRLC_SRM_STAT 0x4c9b 5115#define regRLC_SRM_STAT_BASE_IDX 1 5116#define regRLC_SRM_GPM_ABORT 0x4c9c 5117#define regRLC_SRM_GPM_ABORT_BASE_IDX 1 5118#define regRLC_CSIB_ADDR_LO 0x4ca2 5119#define regRLC_CSIB_ADDR_LO_BASE_IDX 1 5120#define regRLC_CSIB_ADDR_HI 0x4ca3 5121#define regRLC_CSIB_ADDR_HI_BASE_IDX 1 5122#define regRLC_CSIB_LENGTH 0x4ca4 5123#define regRLC_CSIB_LENGTH_BASE_IDX 1 5124#define regRLC_CP_SCHEDULERS 0x4caa 5125#define regRLC_CP_SCHEDULERS_BASE_IDX 1 5126#define regRLC_GPM_GENERAL_8 0x4cad 5127#define regRLC_GPM_GENERAL_8_BASE_IDX 1 5128#define regRLC_GPM_GENERAL_9 0x4cae 5129#define regRLC_GPM_GENERAL_9_BASE_IDX 1 5130#define regRLC_GPM_GENERAL_10 0x4caf 5131#define regRLC_GPM_GENERAL_10_BASE_IDX 1 5132#define regRLC_GPM_GENERAL_11 0x4cb0 5133#define regRLC_GPM_GENERAL_11_BASE_IDX 1 5134#define regRLC_GPM_GENERAL_12 0x4cb1 5135#define regRLC_GPM_GENERAL_12_BASE_IDX 1 5136#define regRLC_GPM_UTCL1_CNTL_0 0x4cb2 5137#define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 5138#define regRLC_GPM_UTCL1_CNTL_1 0x4cb3 5139#define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 5140#define regRLC_GPM_UTCL1_CNTL_2 0x4cb4 5141#define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 5142#define regRLC_SPM_UTCL1_CNTL 0x4cb5 5143#define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1 5144#define regRLC_UTCL1_STATUS_2 0x4cb6 5145#define regRLC_UTCL1_STATUS_2_BASE_IDX 1 5146#define regRLC_LB_THR_CONFIG_2 0x4cb8 5147#define regRLC_LB_THR_CONFIG_2_BASE_IDX 1 5148#define regRLC_LB_THR_CONFIG_3 0x4cb9 5149#define regRLC_LB_THR_CONFIG_3_BASE_IDX 1 5150#define regRLC_LB_THR_CONFIG_4 0x4cba 5151#define regRLC_LB_THR_CONFIG_4_BASE_IDX 1 5152#define regRLC_SPM_UTCL1_ERROR_1 0x4cbc 5153#define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 5154#define regRLC_SPM_UTCL1_ERROR_2 0x4cbd 5155#define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 5156#define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe 5157#define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 5158#define regRLC_LB_THR_CONFIG_1 0x4cbf 5159#define regRLC_LB_THR_CONFIG_1_BASE_IDX 1 5160#define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 5161#define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 5162#define regRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 5163#define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 5164#define regRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 5165#define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 5166#define regRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 5167#define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 5168#define regRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 5169#define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 5170#define regRLC_SEMAPHORE_0 0x4cc7 5171#define regRLC_SEMAPHORE_0_BASE_IDX 1 5172#define regRLC_SEMAPHORE_1 0x4cc8 5173#define regRLC_SEMAPHORE_1_BASE_IDX 1 5174#define regRLC_CP_EOF_INT 0x4cca 5175#define regRLC_CP_EOF_INT_BASE_IDX 1 5176#define regRLC_CP_EOF_INT_CNT 0x4ccb 5177#define regRLC_CP_EOF_INT_CNT_BASE_IDX 1 5178#define regRLC_SPARE_INT 0x4ccc 5179#define regRLC_SPARE_INT_BASE_IDX 1 5180#define regRLC_PREWALKER_UTCL1_CNTL 0x4ccd 5181#define regRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1 5182#define regRLC_PREWALKER_UTCL1_TRIG 0x4cce 5183#define regRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1 5184#define regRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf 5185#define regRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1 5186#define regRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0 5187#define regRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1 5188#define regRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1 5189#define regRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1 5190#define regRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2 5191#define regRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1 5192#define regRLC_DSM_TRIG 0x4cd3 5193#define regRLC_DSM_TRIG_BASE_IDX 1 5194#define regRLC_UTCL1_STATUS 0x4cd4 5195#define regRLC_UTCL1_STATUS_BASE_IDX 1 5196#define regRLC_R2I_CNTL_0 0x4cd5 5197#define regRLC_R2I_CNTL_0_BASE_IDX 1 5198#define regRLC_R2I_CNTL_1 0x4cd6 5199#define regRLC_R2I_CNTL_1_BASE_IDX 1 5200#define regRLC_R2I_CNTL_2 0x4cd7 5201#define regRLC_R2I_CNTL_2_BASE_IDX 1 5202#define regRLC_R2I_CNTL_3 0x4cd8 5203#define regRLC_R2I_CNTL_3_BASE_IDX 1 5204#define regRLC_UTCL2_CNTL 0x4cd9 5205#define regRLC_UTCL2_CNTL_BASE_IDX 1 5206#define regRLC_LBPW_CU_STAT 0x4cda 5207#define regRLC_LBPW_CU_STAT_BASE_IDX 1 5208#define regRLC_DS_CNTL 0x4cdb 5209#define regRLC_DS_CNTL_BASE_IDX 1 5210#define regRLC_GPM_INT_STAT_TH0 0x4cdc 5211#define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1 5212#define regRLC_GPM_GENERAL_13 0x4cdd 5213#define regRLC_GPM_GENERAL_13_BASE_IDX 1 5214#define regRLC_GPM_GENERAL_14 0x4cde 5215#define regRLC_GPM_GENERAL_14_BASE_IDX 1 5216#define regRLC_GPM_GENERAL_15 0x4cdf 5217#define regRLC_GPM_GENERAL_15_BASE_IDX 1 5218#define regRLC_SPARE_INT_1 0x4ce0 5219#define regRLC_SPARE_INT_1_BASE_IDX 1 5220#define regRLC_RLCV_SPARE_INT_1 0x4ce1 5221#define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1 5222#define regRLC_SEMAPHORE_2 0x4ce3 5223#define regRLC_SEMAPHORE_2_BASE_IDX 1 5224#define regRLC_SEMAPHORE_3 0x4ce4 5225#define regRLC_SEMAPHORE_3_BASE_IDX 1 5226#define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4ce8 5227#define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 5228#define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4ce9 5229#define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 5230#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea 5231#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 5232#define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb 5233#define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 5234#define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec 5235#define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 5236#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef 5237#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 5238#define regRLC_CPG_STAT_INVAL 0x4d09 5239#define regRLC_CPG_STAT_INVAL_BASE_IDX 1 5240#define regRLC_EDC_CNT 0x4d40 5241#define regRLC_EDC_CNT_BASE_IDX 1 5242#define regRLC_EDC_CNT2 0x4d41 5243#define regRLC_EDC_CNT2_BASE_IDX 1 5244#define regRLC_DSM_CNTL 0x4d42 5245#define regRLC_DSM_CNTL_BASE_IDX 1 5246#define regRLC_DSM_CNTLA 0x4d43 5247#define regRLC_DSM_CNTLA_BASE_IDX 1 5248#define regRLC_DSM_CNTL2 0x4d44 5249#define regRLC_DSM_CNTL2_BASE_IDX 1 5250#define regRLC_DSM_CNTL2A 0x4d45 5251#define regRLC_DSM_CNTL2A_BASE_IDX 1 5252#define regRLC_RLCV_SPARE_INT 0x4f30 5253#define regRLC_RLCV_SPARE_INT_BASE_IDX 1 5254 5255 5256// addressBlock: gc_rmi_rmidec 5257// base address: 0x9e00 5258#define regRMI_GENERAL_CNTL 0x0780 5259#define regRMI_GENERAL_CNTL_BASE_IDX 0 5260#define regRMI_GENERAL_CNTL1 0x0781 5261#define regRMI_GENERAL_CNTL1_BASE_IDX 0 5262#define regRMI_GENERAL_STATUS 0x0782 5263#define regRMI_GENERAL_STATUS_BASE_IDX 0 5264#define regRMI_SUBBLOCK_STATUS0 0x0783 5265#define regRMI_SUBBLOCK_STATUS0_BASE_IDX 0 5266#define regRMI_SUBBLOCK_STATUS1 0x0784 5267#define regRMI_SUBBLOCK_STATUS1_BASE_IDX 0 5268#define regRMI_SUBBLOCK_STATUS2 0x0785 5269#define regRMI_SUBBLOCK_STATUS2_BASE_IDX 0 5270#define regRMI_SUBBLOCK_STATUS3 0x0786 5271#define regRMI_SUBBLOCK_STATUS3_BASE_IDX 0 5272#define regRMI_XBAR_CONFIG 0x0787 5273#define regRMI_XBAR_CONFIG_BASE_IDX 0 5274#define regRMI_PROBE_POP_LOGIC_CNTL 0x0788 5275#define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0 5276#define regRMI_UTC_XNACK_N_MISC_CNTL 0x0789 5277#define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0 5278#define regRMI_DEMUX_CNTL 0x078a 5279#define regRMI_DEMUX_CNTL_BASE_IDX 0 5280#define regRMI_UTCL1_CNTL1 0x078b 5281#define regRMI_UTCL1_CNTL1_BASE_IDX 0 5282#define regRMI_UTCL1_CNTL2 0x078c 5283#define regRMI_UTCL1_CNTL2_BASE_IDX 0 5284#define regRMI_UTC_UNIT_CONFIG 0x078d 5285#define regRMI_UTC_UNIT_CONFIG_BASE_IDX 0 5286#define regRMI_TCIW_FORMATTER0_CNTL 0x078e 5287#define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0 5288#define regRMI_TCIW_FORMATTER1_CNTL 0x078f 5289#define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0 5290#define regRMI_SCOREBOARD_CNTL 0x0790 5291#define regRMI_SCOREBOARD_CNTL_BASE_IDX 0 5292#define regRMI_SCOREBOARD_STATUS0 0x0791 5293#define regRMI_SCOREBOARD_STATUS0_BASE_IDX 0 5294#define regRMI_SCOREBOARD_STATUS1 0x0792 5295#define regRMI_SCOREBOARD_STATUS1_BASE_IDX 0 5296#define regRMI_SCOREBOARD_STATUS2 0x0793 5297#define regRMI_SCOREBOARD_STATUS2_BASE_IDX 0 5298#define regRMI_XBAR_ARBITER_CONFIG 0x0794 5299#define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0 5300#define regRMI_XBAR_ARBITER_CONFIG_1 0x0795 5301#define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0 5302#define regRMI_CLOCK_CNTRL 0x0796 5303#define regRMI_CLOCK_CNTRL_BASE_IDX 0 5304#define regRMI_UTCL1_STATUS 0x0797 5305#define regRMI_UTCL1_STATUS_BASE_IDX 0 5306#define regRMI_SPARE 0x079e 5307#define regRMI_SPARE_BASE_IDX 0 5308#define regRMI_SPARE_1 0x079f 5309#define regRMI_SPARE_1_BASE_IDX 0 5310#define regRMI_SPARE_2 0x07a0 5311#define regRMI_SPARE_2_BASE_IDX 0 5312 5313 5314// addressBlock: gc_shdec 5315// base address: 0xb000 5316#define regSPI_SHADER_PGM_RSRC3_PS 0x0c07 5317#define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 5318#define regSPI_SHADER_PGM_LO_PS 0x0c08 5319#define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0 5320#define regSPI_SHADER_PGM_HI_PS 0x0c09 5321#define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0 5322#define regSPI_SHADER_PGM_RSRC1_PS 0x0c0a 5323#define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 5324#define regSPI_SHADER_PGM_RSRC2_PS 0x0c0b 5325#define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 5326#define regSPI_SHADER_USER_DATA_PS_0 0x0c0c 5327#define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 5328#define regSPI_SHADER_USER_DATA_PS_1 0x0c0d 5329#define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 5330#define regSPI_SHADER_USER_DATA_PS_2 0x0c0e 5331#define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 5332#define regSPI_SHADER_USER_DATA_PS_3 0x0c0f 5333#define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 5334#define regSPI_SHADER_USER_DATA_PS_4 0x0c10 5335#define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 5336#define regSPI_SHADER_USER_DATA_PS_5 0x0c11 5337#define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 5338#define regSPI_SHADER_USER_DATA_PS_6 0x0c12 5339#define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 5340#define regSPI_SHADER_USER_DATA_PS_7 0x0c13 5341#define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 5342#define regSPI_SHADER_USER_DATA_PS_8 0x0c14 5343#define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 5344#define regSPI_SHADER_USER_DATA_PS_9 0x0c15 5345#define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 5346#define regSPI_SHADER_USER_DATA_PS_10 0x0c16 5347#define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 5348#define regSPI_SHADER_USER_DATA_PS_11 0x0c17 5349#define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 5350#define regSPI_SHADER_USER_DATA_PS_12 0x0c18 5351#define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 5352#define regSPI_SHADER_USER_DATA_PS_13 0x0c19 5353#define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 5354#define regSPI_SHADER_USER_DATA_PS_14 0x0c1a 5355#define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 5356#define regSPI_SHADER_USER_DATA_PS_15 0x0c1b 5357#define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 5358#define regSPI_SHADER_USER_DATA_PS_16 0x0c1c 5359#define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 5360#define regSPI_SHADER_USER_DATA_PS_17 0x0c1d 5361#define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 5362#define regSPI_SHADER_USER_DATA_PS_18 0x0c1e 5363#define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 5364#define regSPI_SHADER_USER_DATA_PS_19 0x0c1f 5365#define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 5366#define regSPI_SHADER_USER_DATA_PS_20 0x0c20 5367#define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 5368#define regSPI_SHADER_USER_DATA_PS_21 0x0c21 5369#define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 5370#define regSPI_SHADER_USER_DATA_PS_22 0x0c22 5371#define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 5372#define regSPI_SHADER_USER_DATA_PS_23 0x0c23 5373#define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 5374#define regSPI_SHADER_USER_DATA_PS_24 0x0c24 5375#define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 5376#define regSPI_SHADER_USER_DATA_PS_25 0x0c25 5377#define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 5378#define regSPI_SHADER_USER_DATA_PS_26 0x0c26 5379#define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 5380#define regSPI_SHADER_USER_DATA_PS_27 0x0c27 5381#define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 5382#define regSPI_SHADER_USER_DATA_PS_28 0x0c28 5383#define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 5384#define regSPI_SHADER_USER_DATA_PS_29 0x0c29 5385#define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 5386#define regSPI_SHADER_USER_DATA_PS_30 0x0c2a 5387#define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 5388#define regSPI_SHADER_USER_DATA_PS_31 0x0c2b 5389#define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 5390#define regSPI_SHADER_PGM_RSRC3_VS 0x0c46 5391#define regSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0 5392#define regSPI_SHADER_LATE_ALLOC_VS 0x0c47 5393#define regSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0 5394#define regSPI_SHADER_PGM_LO_VS 0x0c48 5395#define regSPI_SHADER_PGM_LO_VS_BASE_IDX 0 5396#define regSPI_SHADER_PGM_HI_VS 0x0c49 5397#define regSPI_SHADER_PGM_HI_VS_BASE_IDX 0 5398#define regSPI_SHADER_PGM_RSRC1_VS 0x0c4a 5399#define regSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0 5400#define regSPI_SHADER_PGM_RSRC2_VS 0x0c4b 5401#define regSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0 5402#define regSPI_SHADER_USER_DATA_VS_0 0x0c4c 5403#define regSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0 5404#define regSPI_SHADER_USER_DATA_VS_1 0x0c4d 5405#define regSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0 5406#define regSPI_SHADER_USER_DATA_VS_2 0x0c4e 5407#define regSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0 5408#define regSPI_SHADER_USER_DATA_VS_3 0x0c4f 5409#define regSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0 5410#define regSPI_SHADER_USER_DATA_VS_4 0x0c50 5411#define regSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0 5412#define regSPI_SHADER_USER_DATA_VS_5 0x0c51 5413#define regSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0 5414#define regSPI_SHADER_USER_DATA_VS_6 0x0c52 5415#define regSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0 5416#define regSPI_SHADER_USER_DATA_VS_7 0x0c53 5417#define regSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0 5418#define regSPI_SHADER_USER_DATA_VS_8 0x0c54 5419#define regSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0 5420#define regSPI_SHADER_USER_DATA_VS_9 0x0c55 5421#define regSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0 5422#define regSPI_SHADER_USER_DATA_VS_10 0x0c56 5423#define regSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0 5424#define regSPI_SHADER_USER_DATA_VS_11 0x0c57 5425#define regSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0 5426#define regSPI_SHADER_USER_DATA_VS_12 0x0c58 5427#define regSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0 5428#define regSPI_SHADER_USER_DATA_VS_13 0x0c59 5429#define regSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0 5430#define regSPI_SHADER_USER_DATA_VS_14 0x0c5a 5431#define regSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0 5432#define regSPI_SHADER_USER_DATA_VS_15 0x0c5b 5433#define regSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0 5434#define regSPI_SHADER_USER_DATA_VS_16 0x0c5c 5435#define regSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0 5436#define regSPI_SHADER_USER_DATA_VS_17 0x0c5d 5437#define regSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0 5438#define regSPI_SHADER_USER_DATA_VS_18 0x0c5e 5439#define regSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0 5440#define regSPI_SHADER_USER_DATA_VS_19 0x0c5f 5441#define regSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0 5442#define regSPI_SHADER_USER_DATA_VS_20 0x0c60 5443#define regSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0 5444#define regSPI_SHADER_USER_DATA_VS_21 0x0c61 5445#define regSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0 5446#define regSPI_SHADER_USER_DATA_VS_22 0x0c62 5447#define regSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0 5448#define regSPI_SHADER_USER_DATA_VS_23 0x0c63 5449#define regSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0 5450#define regSPI_SHADER_USER_DATA_VS_24 0x0c64 5451#define regSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0 5452#define regSPI_SHADER_USER_DATA_VS_25 0x0c65 5453#define regSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0 5454#define regSPI_SHADER_USER_DATA_VS_26 0x0c66 5455#define regSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0 5456#define regSPI_SHADER_USER_DATA_VS_27 0x0c67 5457#define regSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0 5458#define regSPI_SHADER_USER_DATA_VS_28 0x0c68 5459#define regSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0 5460#define regSPI_SHADER_USER_DATA_VS_29 0x0c69 5461#define regSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0 5462#define regSPI_SHADER_USER_DATA_VS_30 0x0c6a 5463#define regSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0 5464#define regSPI_SHADER_USER_DATA_VS_31 0x0c6b 5465#define regSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0 5466#define regSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c 5467#define regSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0 5468#define regSPI_SHADER_PGM_RSRC4_GS 0x0c81 5469#define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 5470#define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82 5471#define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 5472#define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83 5473#define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 5474#define regSPI_SHADER_PGM_LO_ES 0x0c84 5475#define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0 5476#define regSPI_SHADER_PGM_HI_ES 0x0c85 5477#define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0 5478#define regSPI_SHADER_PGM_RSRC3_GS 0x0c87 5479#define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 5480#define regSPI_SHADER_PGM_LO_GS 0x0c88 5481#define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0 5482#define regSPI_SHADER_PGM_HI_GS 0x0c89 5483#define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0 5484#define regSPI_SHADER_PGM_RSRC1_GS 0x0c8a 5485#define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 5486#define regSPI_SHADER_PGM_RSRC2_GS 0x0c8b 5487#define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 5488#define regSPI_SHADER_USER_DATA_ES_0 0x0ccc 5489#define regSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0 5490#define regSPI_SHADER_USER_DATA_ES_1 0x0ccd 5491#define regSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0 5492#define regSPI_SHADER_USER_DATA_ES_2 0x0cce 5493#define regSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0 5494#define regSPI_SHADER_USER_DATA_ES_3 0x0ccf 5495#define regSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0 5496#define regSPI_SHADER_USER_DATA_ES_4 0x0cd0 5497#define regSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0 5498#define regSPI_SHADER_USER_DATA_ES_5 0x0cd1 5499#define regSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0 5500#define regSPI_SHADER_USER_DATA_ES_6 0x0cd2 5501#define regSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0 5502#define regSPI_SHADER_USER_DATA_ES_7 0x0cd3 5503#define regSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0 5504#define regSPI_SHADER_USER_DATA_ES_8 0x0cd4 5505#define regSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0 5506#define regSPI_SHADER_USER_DATA_ES_9 0x0cd5 5507#define regSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0 5508#define regSPI_SHADER_USER_DATA_ES_10 0x0cd6 5509#define regSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0 5510#define regSPI_SHADER_USER_DATA_ES_11 0x0cd7 5511#define regSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0 5512#define regSPI_SHADER_USER_DATA_ES_12 0x0cd8 5513#define regSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0 5514#define regSPI_SHADER_USER_DATA_ES_13 0x0cd9 5515#define regSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0 5516#define regSPI_SHADER_USER_DATA_ES_14 0x0cda 5517#define regSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0 5518#define regSPI_SHADER_USER_DATA_ES_15 0x0cdb 5519#define regSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0 5520#define regSPI_SHADER_USER_DATA_ES_16 0x0cdc 5521#define regSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0 5522#define regSPI_SHADER_USER_DATA_ES_17 0x0cdd 5523#define regSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0 5524#define regSPI_SHADER_USER_DATA_ES_18 0x0cde 5525#define regSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0 5526#define regSPI_SHADER_USER_DATA_ES_19 0x0cdf 5527#define regSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0 5528#define regSPI_SHADER_USER_DATA_ES_20 0x0ce0 5529#define regSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0 5530#define regSPI_SHADER_USER_DATA_ES_21 0x0ce1 5531#define regSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0 5532#define regSPI_SHADER_USER_DATA_ES_22 0x0ce2 5533#define regSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0 5534#define regSPI_SHADER_USER_DATA_ES_23 0x0ce3 5535#define regSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0 5536#define regSPI_SHADER_USER_DATA_ES_24 0x0ce4 5537#define regSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0 5538#define regSPI_SHADER_USER_DATA_ES_25 0x0ce5 5539#define regSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0 5540#define regSPI_SHADER_USER_DATA_ES_26 0x0ce6 5541#define regSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0 5542#define regSPI_SHADER_USER_DATA_ES_27 0x0ce7 5543#define regSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0 5544#define regSPI_SHADER_USER_DATA_ES_28 0x0ce8 5545#define regSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0 5546#define regSPI_SHADER_USER_DATA_ES_29 0x0ce9 5547#define regSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0 5548#define regSPI_SHADER_USER_DATA_ES_30 0x0cea 5549#define regSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0 5550#define regSPI_SHADER_USER_DATA_ES_31 0x0ceb 5551#define regSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0 5552#define regSPI_SHADER_PGM_RSRC4_HS 0x0d01 5553#define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 5554#define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02 5555#define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 5556#define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03 5557#define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 5558#define regSPI_SHADER_PGM_LO_LS 0x0d04 5559#define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0 5560#define regSPI_SHADER_PGM_HI_LS 0x0d05 5561#define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0 5562#define regSPI_SHADER_PGM_RSRC3_HS 0x0d07 5563#define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 5564#define regSPI_SHADER_PGM_LO_HS 0x0d08 5565#define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0 5566#define regSPI_SHADER_PGM_HI_HS 0x0d09 5567#define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0 5568#define regSPI_SHADER_PGM_RSRC1_HS 0x0d0a 5569#define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 5570#define regSPI_SHADER_PGM_RSRC2_HS 0x0d0b 5571#define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 5572#define regSPI_SHADER_USER_DATA_LS_0 0x0d0c 5573#define regSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0 5574#define regSPI_SHADER_USER_DATA_LS_1 0x0d0d 5575#define regSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0 5576#define regSPI_SHADER_USER_DATA_LS_2 0x0d0e 5577#define regSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0 5578#define regSPI_SHADER_USER_DATA_LS_3 0x0d0f 5579#define regSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0 5580#define regSPI_SHADER_USER_DATA_LS_4 0x0d10 5581#define regSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0 5582#define regSPI_SHADER_USER_DATA_LS_5 0x0d11 5583#define regSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0 5584#define regSPI_SHADER_USER_DATA_LS_6 0x0d12 5585#define regSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0 5586#define regSPI_SHADER_USER_DATA_LS_7 0x0d13 5587#define regSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0 5588#define regSPI_SHADER_USER_DATA_LS_8 0x0d14 5589#define regSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0 5590#define regSPI_SHADER_USER_DATA_LS_9 0x0d15 5591#define regSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0 5592#define regSPI_SHADER_USER_DATA_LS_10 0x0d16 5593#define regSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0 5594#define regSPI_SHADER_USER_DATA_LS_11 0x0d17 5595#define regSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0 5596#define regSPI_SHADER_USER_DATA_LS_12 0x0d18 5597#define regSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0 5598#define regSPI_SHADER_USER_DATA_LS_13 0x0d19 5599#define regSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0 5600#define regSPI_SHADER_USER_DATA_LS_14 0x0d1a 5601#define regSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0 5602#define regSPI_SHADER_USER_DATA_LS_15 0x0d1b 5603#define regSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0 5604#define regSPI_SHADER_USER_DATA_LS_16 0x0d1c 5605#define regSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0 5606#define regSPI_SHADER_USER_DATA_LS_17 0x0d1d 5607#define regSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0 5608#define regSPI_SHADER_USER_DATA_LS_18 0x0d1e 5609#define regSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0 5610#define regSPI_SHADER_USER_DATA_LS_19 0x0d1f 5611#define regSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0 5612#define regSPI_SHADER_USER_DATA_LS_20 0x0d20 5613#define regSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0 5614#define regSPI_SHADER_USER_DATA_LS_21 0x0d21 5615#define regSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0 5616#define regSPI_SHADER_USER_DATA_LS_22 0x0d22 5617#define regSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0 5618#define regSPI_SHADER_USER_DATA_LS_23 0x0d23 5619#define regSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0 5620#define regSPI_SHADER_USER_DATA_LS_24 0x0d24 5621#define regSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0 5622#define regSPI_SHADER_USER_DATA_LS_25 0x0d25 5623#define regSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0 5624#define regSPI_SHADER_USER_DATA_LS_26 0x0d26 5625#define regSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0 5626#define regSPI_SHADER_USER_DATA_LS_27 0x0d27 5627#define regSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0 5628#define regSPI_SHADER_USER_DATA_LS_28 0x0d28 5629#define regSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0 5630#define regSPI_SHADER_USER_DATA_LS_29 0x0d29 5631#define regSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0 5632#define regSPI_SHADER_USER_DATA_LS_30 0x0d2a 5633#define regSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0 5634#define regSPI_SHADER_USER_DATA_LS_31 0x0d2b 5635#define regSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0 5636#define regSPI_SHADER_USER_DATA_COMMON_0 0x0d4c 5637#define regSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0 5638#define regSPI_SHADER_USER_DATA_COMMON_1 0x0d4d 5639#define regSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0 5640#define regSPI_SHADER_USER_DATA_COMMON_2 0x0d4e 5641#define regSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0 5642#define regSPI_SHADER_USER_DATA_COMMON_3 0x0d4f 5643#define regSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0 5644#define regSPI_SHADER_USER_DATA_COMMON_4 0x0d50 5645#define regSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0 5646#define regSPI_SHADER_USER_DATA_COMMON_5 0x0d51 5647#define regSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0 5648#define regSPI_SHADER_USER_DATA_COMMON_6 0x0d52 5649#define regSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0 5650#define regSPI_SHADER_USER_DATA_COMMON_7 0x0d53 5651#define regSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0 5652#define regSPI_SHADER_USER_DATA_COMMON_8 0x0d54 5653#define regSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0 5654#define regSPI_SHADER_USER_DATA_COMMON_9 0x0d55 5655#define regSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0 5656#define regSPI_SHADER_USER_DATA_COMMON_10 0x0d56 5657#define regSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0 5658#define regSPI_SHADER_USER_DATA_COMMON_11 0x0d57 5659#define regSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0 5660#define regSPI_SHADER_USER_DATA_COMMON_12 0x0d58 5661#define regSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0 5662#define regSPI_SHADER_USER_DATA_COMMON_13 0x0d59 5663#define regSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0 5664#define regSPI_SHADER_USER_DATA_COMMON_14 0x0d5a 5665#define regSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0 5666#define regSPI_SHADER_USER_DATA_COMMON_15 0x0d5b 5667#define regSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0 5668#define regSPI_SHADER_USER_DATA_COMMON_16 0x0d5c 5669#define regSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0 5670#define regSPI_SHADER_USER_DATA_COMMON_17 0x0d5d 5671#define regSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0 5672#define regSPI_SHADER_USER_DATA_COMMON_18 0x0d5e 5673#define regSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0 5674#define regSPI_SHADER_USER_DATA_COMMON_19 0x0d5f 5675#define regSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0 5676#define regSPI_SHADER_USER_DATA_COMMON_20 0x0d60 5677#define regSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0 5678#define regSPI_SHADER_USER_DATA_COMMON_21 0x0d61 5679#define regSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0 5680#define regSPI_SHADER_USER_DATA_COMMON_22 0x0d62 5681#define regSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0 5682#define regSPI_SHADER_USER_DATA_COMMON_23 0x0d63 5683#define regSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0 5684#define regSPI_SHADER_USER_DATA_COMMON_24 0x0d64 5685#define regSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0 5686#define regSPI_SHADER_USER_DATA_COMMON_25 0x0d65 5687#define regSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0 5688#define regSPI_SHADER_USER_DATA_COMMON_26 0x0d66 5689#define regSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0 5690#define regSPI_SHADER_USER_DATA_COMMON_27 0x0d67 5691#define regSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0 5692#define regSPI_SHADER_USER_DATA_COMMON_28 0x0d68 5693#define regSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0 5694#define regSPI_SHADER_USER_DATA_COMMON_29 0x0d69 5695#define regSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0 5696#define regSPI_SHADER_USER_DATA_COMMON_30 0x0d6a 5697#define regSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0 5698#define regSPI_SHADER_USER_DATA_COMMON_31 0x0d6b 5699#define regSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0 5700#define regCOMPUTE_DISPATCH_INITIATOR 0x0e00 5701#define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 5702#define regCOMPUTE_DIM_X 0x0e01 5703#define regCOMPUTE_DIM_X_BASE_IDX 0 5704#define regCOMPUTE_DIM_Y 0x0e02 5705#define regCOMPUTE_DIM_Y_BASE_IDX 0 5706#define regCOMPUTE_DIM_Z 0x0e03 5707#define regCOMPUTE_DIM_Z_BASE_IDX 0 5708#define regCOMPUTE_START_X 0x0e04 5709#define regCOMPUTE_START_X_BASE_IDX 0 5710#define regCOMPUTE_START_Y 0x0e05 5711#define regCOMPUTE_START_Y_BASE_IDX 0 5712#define regCOMPUTE_START_Z 0x0e06 5713#define regCOMPUTE_START_Z_BASE_IDX 0 5714#define regCOMPUTE_NUM_THREAD_X 0x0e07 5715#define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0 5716#define regCOMPUTE_NUM_THREAD_Y 0x0e08 5717#define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 5718#define regCOMPUTE_NUM_THREAD_Z 0x0e09 5719#define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 5720#define regCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a 5721#define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 5722#define regCOMPUTE_PERFCOUNT_ENABLE 0x0e0b 5723#define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 5724#define regCOMPUTE_PGM_LO 0x0e0c 5725#define regCOMPUTE_PGM_LO_BASE_IDX 0 5726#define regCOMPUTE_PGM_HI 0x0e0d 5727#define regCOMPUTE_PGM_HI_BASE_IDX 0 5728#define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e 5729#define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 5730#define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f 5731#define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 5732#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10 5733#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 5734#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11 5735#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 5736#define regCOMPUTE_PGM_RSRC1 0x0e12 5737#define regCOMPUTE_PGM_RSRC1_BASE_IDX 0 5738#define regCOMPUTE_PGM_RSRC2 0x0e13 5739#define regCOMPUTE_PGM_RSRC2_BASE_IDX 0 5740#define regCOMPUTE_VMID 0x0e14 5741#define regCOMPUTE_VMID_BASE_IDX 0 5742#define regCOMPUTE_RESOURCE_LIMITS 0x0e15 5743#define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 5744#define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16 5745#define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 5746#define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17 5747#define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 5748#define regCOMPUTE_TMPRING_SIZE 0x0e18 5749#define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0 5750#define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19 5751#define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 5752#define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a 5753#define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 5754#define regCOMPUTE_RESTART_X 0x0e1b 5755#define regCOMPUTE_RESTART_X_BASE_IDX 0 5756#define regCOMPUTE_RESTART_Y 0x0e1c 5757#define regCOMPUTE_RESTART_Y_BASE_IDX 0 5758#define regCOMPUTE_RESTART_Z 0x0e1d 5759#define regCOMPUTE_RESTART_Z_BASE_IDX 0 5760#define regCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e 5761#define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 5762#define regCOMPUTE_MISC_RESERVED 0x0e1f 5763#define regCOMPUTE_MISC_RESERVED_BASE_IDX 0 5764#define regCOMPUTE_DISPATCH_ID 0x0e20 5765#define regCOMPUTE_DISPATCH_ID_BASE_IDX 0 5766#define regCOMPUTE_THREADGROUP_ID 0x0e21 5767#define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0 5768#define regCOMPUTE_RELAUNCH 0x0e22 5769#define regCOMPUTE_RELAUNCH_BASE_IDX 0 5770#define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23 5771#define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 5772#define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24 5773#define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 5774#define regCOMPUTE_STATIC_THREAD_MGMT_SE4 0x0e25 5775#define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 0 5776#define regCOMPUTE_STATIC_THREAD_MGMT_SE5 0x0e26 5777#define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 0 5778#define regCOMPUTE_STATIC_THREAD_MGMT_SE6 0x0e27 5779#define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 0 5780#define regCOMPUTE_STATIC_THREAD_MGMT_SE7 0x0e28 5781#define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 0 5782#define regCOMPUTE_RESTART_X2 0x0e29 5783#define regCOMPUTE_RESTART_X2_BASE_IDX 0 5784#define regCOMPUTE_RESTART_Y2 0x0e2a 5785#define regCOMPUTE_RESTART_Y2_BASE_IDX 0 5786#define regCOMPUTE_RESTART_Z2 0x0e2b 5787#define regCOMPUTE_RESTART_Z2_BASE_IDX 0 5788#define regCOMPUTE_SHADER_CHKSUM 0x0e2c 5789#define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 5790#define regCOMPUTE_PGM_RSRC3 0x0e2d 5791#define regCOMPUTE_PGM_RSRC3_BASE_IDX 0 5792#define regCOMPUTE_USER_DATA_0 0x0e40 5793#define regCOMPUTE_USER_DATA_0_BASE_IDX 0 5794#define regCOMPUTE_USER_DATA_1 0x0e41 5795#define regCOMPUTE_USER_DATA_1_BASE_IDX 0 5796#define regCOMPUTE_USER_DATA_2 0x0e42 5797#define regCOMPUTE_USER_DATA_2_BASE_IDX 0 5798#define regCOMPUTE_USER_DATA_3 0x0e43 5799#define regCOMPUTE_USER_DATA_3_BASE_IDX 0 5800#define regCOMPUTE_USER_DATA_4 0x0e44 5801#define regCOMPUTE_USER_DATA_4_BASE_IDX 0 5802#define regCOMPUTE_USER_DATA_5 0x0e45 5803#define regCOMPUTE_USER_DATA_5_BASE_IDX 0 5804#define regCOMPUTE_USER_DATA_6 0x0e46 5805#define regCOMPUTE_USER_DATA_6_BASE_IDX 0 5806#define regCOMPUTE_USER_DATA_7 0x0e47 5807#define regCOMPUTE_USER_DATA_7_BASE_IDX 0 5808#define regCOMPUTE_USER_DATA_8 0x0e48 5809#define regCOMPUTE_USER_DATA_8_BASE_IDX 0 5810#define regCOMPUTE_USER_DATA_9 0x0e49 5811#define regCOMPUTE_USER_DATA_9_BASE_IDX 0 5812#define regCOMPUTE_USER_DATA_10 0x0e4a 5813#define regCOMPUTE_USER_DATA_10_BASE_IDX 0 5814#define regCOMPUTE_USER_DATA_11 0x0e4b 5815#define regCOMPUTE_USER_DATA_11_BASE_IDX 0 5816#define regCOMPUTE_USER_DATA_12 0x0e4c 5817#define regCOMPUTE_USER_DATA_12_BASE_IDX 0 5818#define regCOMPUTE_USER_DATA_13 0x0e4d 5819#define regCOMPUTE_USER_DATA_13_BASE_IDX 0 5820#define regCOMPUTE_USER_DATA_14 0x0e4e 5821#define regCOMPUTE_USER_DATA_14_BASE_IDX 0 5822#define regCOMPUTE_USER_DATA_15 0x0e4f 5823#define regCOMPUTE_USER_DATA_15_BASE_IDX 0 5824#define regCOMPUTE_DISPATCH_END 0x0e7e 5825#define regCOMPUTE_DISPATCH_END_BASE_IDX 0 5826#define regCOMPUTE_NOWHERE 0x0e7f 5827#define regCOMPUTE_NOWHERE_BASE_IDX 0 5828 5829 5830// addressBlock: gc_shsdec 5831// base address: 0x9000 5832#define regSX_DEBUG_1 0x0419 5833#define regSX_DEBUG_1_BASE_IDX 0 5834#define regSPI_PS_MAX_WAVE_ID 0x043a 5835#define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0 5836#define regSPI_START_PHASE 0x043b 5837#define regSPI_START_PHASE_BASE_IDX 0 5838#define regSPI_GFX_CNTL 0x043c 5839#define regSPI_GFX_CNTL_BASE_IDX 0 5840#define regSPI_DSM_CNTL 0x0443 5841#define regSPI_DSM_CNTL_BASE_IDX 0 5842#define regSPI_DSM_CNTL2 0x0444 5843#define regSPI_DSM_CNTL2_BASE_IDX 0 5844#define regSPI_EDC_CNT 0x0445 5845#define regSPI_EDC_CNT_BASE_IDX 0 5846#define regSPI_CONFIG_PS_CU_EN 0x0452 5847#define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0 5848#define regSPI_WF_LIFETIME_CNTL 0x04aa 5849#define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0 5850#define regSPI_WF_LIFETIME_LIMIT_0 0x04ab 5851#define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 5852#define regSPI_WF_LIFETIME_LIMIT_1 0x04ac 5853#define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 5854#define regSPI_WF_LIFETIME_LIMIT_2 0x04ad 5855#define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 5856#define regSPI_WF_LIFETIME_LIMIT_3 0x04ae 5857#define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 5858#define regSPI_WF_LIFETIME_LIMIT_4 0x04af 5859#define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 5860#define regSPI_WF_LIFETIME_LIMIT_5 0x04b0 5861#define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 5862#define regSPI_WF_LIFETIME_LIMIT_6 0x04b1 5863#define regSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0 5864#define regSPI_WF_LIFETIME_LIMIT_7 0x04b2 5865#define regSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0 5866#define regSPI_WF_LIFETIME_LIMIT_8 0x04b3 5867#define regSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0 5868#define regSPI_WF_LIFETIME_LIMIT_9 0x04b4 5869#define regSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0 5870#define regSPI_WF_LIFETIME_STATUS_0 0x04b5 5871#define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 5872#define regSPI_WF_LIFETIME_STATUS_1 0x04b6 5873#define regSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0 5874#define regSPI_WF_LIFETIME_STATUS_2 0x04b7 5875#define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 5876#define regSPI_WF_LIFETIME_STATUS_3 0x04b8 5877#define regSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0 5878#define regSPI_WF_LIFETIME_STATUS_4 0x04b9 5879#define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 5880#define regSPI_WF_LIFETIME_STATUS_5 0x04ba 5881#define regSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0 5882#define regSPI_WF_LIFETIME_STATUS_6 0x04bb 5883#define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 5884#define regSPI_WF_LIFETIME_STATUS_7 0x04bc 5885#define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 5886#define regSPI_WF_LIFETIME_STATUS_8 0x04bd 5887#define regSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0 5888#define regSPI_WF_LIFETIME_STATUS_9 0x04be 5889#define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 5890#define regSPI_WF_LIFETIME_STATUS_10 0x04bf 5891#define regSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0 5892#define regSPI_WF_LIFETIME_STATUS_11 0x04c0 5893#define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 5894#define regSPI_WF_LIFETIME_STATUS_12 0x04c1 5895#define regSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0 5896#define regSPI_WF_LIFETIME_STATUS_13 0x04c2 5897#define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 5898#define regSPI_WF_LIFETIME_STATUS_14 0x04c3 5899#define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 5900#define regSPI_WF_LIFETIME_STATUS_15 0x04c4 5901#define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 5902#define regSPI_WF_LIFETIME_STATUS_16 0x04c5 5903#define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 5904#define regSPI_WF_LIFETIME_STATUS_17 0x04c6 5905#define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 5906#define regSPI_WF_LIFETIME_STATUS_18 0x04c7 5907#define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 5908#define regSPI_WF_LIFETIME_STATUS_19 0x04c8 5909#define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 5910#define regSPI_WF_LIFETIME_STATUS_20 0x04c9 5911#define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 5912#define regSPI_LB_CTR_CTRL 0x04d4 5913#define regSPI_LB_CTR_CTRL_BASE_IDX 0 5914#define regSPI_LB_CU_MASK 0x04d5 5915#define regSPI_LB_CU_MASK_BASE_IDX 0 5916#define regSPI_LB_DATA_REG 0x04d6 5917#define regSPI_LB_DATA_REG_BASE_IDX 0 5918#define regSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7 5919#define regSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0 5920#define regSPI_GDS_CREDITS 0x04d8 5921#define regSPI_GDS_CREDITS_BASE_IDX 0 5922#define regSPI_SX_EXPORT_BUFFER_SIZES 0x04d9 5923#define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 5924#define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da 5925#define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 5926#define regSPI_CSQ_WF_ACTIVE_STATUS 0x04db 5927#define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 5928#define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc 5929#define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 5930#define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd 5931#define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 5932#define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de 5933#define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 5934#define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df 5935#define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 5936#define regSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0 5937#define regSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 5938#define regSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1 5939#define regSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 5940#define regSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2 5941#define regSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 5942#define regSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3 5943#define regSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 5944#define regSPI_LB_DATA_WAVES 0x04e4 5945#define regSPI_LB_DATA_WAVES_BASE_IDX 0 5946#define regSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5 5947#define regSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0 5948#define regSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6 5949#define regSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0 5950#define regSPI_LB_DATA_PERCU_WAVE_CS 0x04e7 5951#define regSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0 5952#define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec 5953#define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 5954#define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed 5955#define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 5956#define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee 5957#define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 5958#define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef 5959#define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 5960#define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0 5961#define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 5962#define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1 5963#define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 5964#define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2 5965#define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 5966#define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3 5967#define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 5968#define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4 5969#define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 5970#define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5 5971#define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 5972 5973 5974// addressBlock: gc_spipdec 5975// base address: 0xc700 5976#define regSPI_ARB_PRIORITY 0x11c0 5977#define regSPI_ARB_PRIORITY_BASE_IDX 0 5978#define regSPI_ARB_CYCLES_0 0x11c1 5979#define regSPI_ARB_CYCLES_0_BASE_IDX 0 5980#define regSPI_ARB_CYCLES_1 0x11c2 5981#define regSPI_ARB_CYCLES_1_BASE_IDX 0 5982#define regSPI_WCL_PIPE_PERCENT_GFX 0x11c7 5983#define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 5984#define regSPI_WCL_PIPE_PERCENT_HP3D 0x11c8 5985#define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 5986#define regSPI_WCL_PIPE_PERCENT_CS0 0x11c9 5987#define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 5988#define regSPI_WCL_PIPE_PERCENT_CS1 0x11ca 5989#define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 5990#define regSPI_WCL_PIPE_PERCENT_CS2 0x11cb 5991#define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 5992#define regSPI_WCL_PIPE_PERCENT_CS3 0x11cc 5993#define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 5994#define regSPI_WCL_PIPE_PERCENT_CS4 0x11cd 5995#define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 5996#define regSPI_WCL_PIPE_PERCENT_CS5 0x11ce 5997#define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 5998#define regSPI_WCL_PIPE_PERCENT_CS6 0x11cf 5999#define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 6000#define regSPI_WCL_PIPE_PERCENT_CS7 0x11d0
6001#define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 6002#define regSPI_GDBG_WAVE_CNTL 0x11d1 6003#define regSPI_GDBG_WAVE_CNTL_BASE_IDX 0 6004#define regSPI_GDBG_TRAP_CONFIG 0x11d2 6005#define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 6006#define regSPI_GDBG_PER_VMID_CNTL 0x11d3 6007#define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0 6008#define regSPI_GDBG_WAVE_CNTL3 0x11d5 6009#define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 6010#define regSPI_GDBG_TRAP_DATA0 0x11d8 6011#define regSPI_GDBG_TRAP_DATA0_BASE_IDX 0 6012#define regSPI_GDBG_TRAP_DATA1 0x11d9 6013#define regSPI_GDBG_TRAP_DATA1_BASE_IDX 0 6014#define regSPI_COMPUTE_QUEUE_RESET 0x11db 6015#define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 6016#define regSPI_RESOURCE_RESERVE_CU_0 0x11dc 6017#define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0 6018#define regSPI_RESOURCE_RESERVE_CU_1 0x11dd 6019#define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0 6020#define regSPI_RESOURCE_RESERVE_CU_2 0x11de 6021#define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0 6022#define regSPI_RESOURCE_RESERVE_CU_3 0x11df 6023#define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0 6024#define regSPI_RESOURCE_RESERVE_CU_4 0x11e0 6025#define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0 6026#define regSPI_RESOURCE_RESERVE_CU_5 0x11e1 6027#define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0 6028#define regSPI_RESOURCE_RESERVE_CU_6 0x11e2 6029#define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0 6030#define regSPI_RESOURCE_RESERVE_CU_7 0x11e3 6031#define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0 6032#define regSPI_RESOURCE_RESERVE_CU_8 0x11e4 6033#define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0 6034#define regSPI_RESOURCE_RESERVE_CU_9 0x11e5 6035#define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0 6036#define regSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6 6037#define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0 6038#define regSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7 6039#define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0 6040#define regSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8 6041#define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0 6042#define regSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9 6043#define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0 6044#define regSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea 6045#define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0 6046#define regSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb 6047#define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0 6048#define regSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec 6049#define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0 6050#define regSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed 6051#define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0 6052#define regSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee 6053#define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0 6054#define regSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef 6055#define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0 6056#define regSPI_RESOURCE_RESERVE_CU_10 0x11f0 6057#define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0 6058#define regSPI_RESOURCE_RESERVE_CU_11 0x11f1 6059#define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0 6060#define regSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2 6061#define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0 6062#define regSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3 6063#define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0 6064#define regSPI_RESOURCE_RESERVE_CU_12 0x11f4 6065#define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0 6066#define regSPI_RESOURCE_RESERVE_CU_13 0x11f5 6067#define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0 6068#define regSPI_RESOURCE_RESERVE_CU_14 0x11f6 6069#define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0 6070#define regSPI_RESOURCE_RESERVE_CU_15 0x11f7 6071#define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0 6072#define regSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8 6073#define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0 6074#define regSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9 6075#define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0 6076#define regSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa 6077#define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0 6078#define regSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb 6079#define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0 6080#define regSPI_COMPUTE_WF_CTX_SAVE 0x11fc 6081#define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 6082#define regSPI_ARB_CNTL_0 0x11fd 6083#define regSPI_ARB_CNTL_0_BASE_IDX 0 6084 6085 6086// addressBlock: gc_sqdec 6087// base address: 0x8c00 6088#define regSQ_CONFIG 0x0300 6089#define regSQ_CONFIG_BASE_IDX 0 6090#define regSQC_CONFIG 0x0301 6091#define regSQC_CONFIG_BASE_IDX 0 6092#define regLDS_CONFIG 0x0302 6093#define regLDS_CONFIG_BASE_IDX 0 6094#define regSQ_RANDOM_WAVE_PRI 0x0303 6095#define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0 6096#define regSQ_REG_CREDITS 0x0304 6097#define regSQ_REG_CREDITS_BASE_IDX 0 6098#define regSQ_FIFO_SIZES 0x0305 6099#define regSQ_FIFO_SIZES_BASE_IDX 0 6100#define regSQ_DSM_CNTL 0x0306 6101#define regSQ_DSM_CNTL_BASE_IDX 0 6102#define regSQ_DSM_CNTL2 0x0307 6103#define regSQ_DSM_CNTL2_BASE_IDX 0 6104#define regSQ_RUNTIME_CONFIG 0x0308 6105#define regSQ_RUNTIME_CONFIG_BASE_IDX 0 6106#define regSQ_DEBUG_STS_GLOBAL 0x0309 6107#define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 6108#define regSH_MEM_BASES 0x030a 6109#define regSH_MEM_BASES_BASE_IDX 0 6110#define regSQ_TIMEOUT_CONFIG 0x030b 6111#define regSQ_TIMEOUT_CONFIG_BASE_IDX 0 6112#define regSQ_TIMEOUT_STATUS 0x030c 6113#define regSQ_TIMEOUT_STATUS_BASE_IDX 0 6114#define regSH_MEM_CONFIG 0x030d 6115#define regSH_MEM_CONFIG_BASE_IDX 0 6116#define regSP_MFMA_PORTD_RD_CONFIG 0x030e 6117#define regSP_MFMA_PORTD_RD_CONFIG_BASE_IDX 0 6118#define regSH_CAC_CONFIG 0x030f 6119#define regSH_CAC_CONFIG_BASE_IDX 0 6120#define regSQ_DEBUG_STS_GLOBAL2 0x0310 6121#define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 6122#define regSQ_DEBUG_STS_GLOBAL3 0x0311 6123#define regSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0 6124#define regCC_GC_SHADER_RATE_CONFIG 0x0312 6125#define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 6126#define regGC_USER_SHADER_RATE_CONFIG 0x0313 6127#define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0 6128#define regSQ_INTERRUPT_AUTO_MASK 0x0314 6129#define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 6130#define regSQ_INTERRUPT_MSG_CTRL 0x0315 6131#define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 6132#define regSQ_DEBUG_PERFCOUNT_TRAP 0x0316 6133#define regSQ_DEBUG_PERFCOUNT_TRAP_BASE_IDX 0 6134#define regSQ_UTCL1_CNTL1 0x0317 6135#define regSQ_UTCL1_CNTL1_BASE_IDX 0 6136#define regSQ_UTCL1_CNTL2 0x0318 6137#define regSQ_UTCL1_CNTL2_BASE_IDX 0 6138#define regSQ_UTCL1_STATUS 0x0319 6139#define regSQ_UTCL1_STATUS_BASE_IDX 0 6140#define regSQ_FED_INTERRUPT_STATUS 0x031a 6141#define regSQ_FED_INTERRUPT_STATUS_BASE_IDX 0 6142#define regSQ_CGTS_CONFIG 0x031b 6143#define regSQ_CGTS_CONFIG_BASE_IDX 0 6144#define regSQ_SHADER_TBA_LO 0x031c 6145#define regSQ_SHADER_TBA_LO_BASE_IDX 0 6146#define regSQ_SHADER_TBA_HI 0x031d 6147#define regSQ_SHADER_TBA_HI_BASE_IDX 0 6148#define regSQ_SHADER_TMA_LO 0x031e 6149#define regSQ_SHADER_TMA_LO_BASE_IDX 0 6150#define regSQ_SHADER_TMA_HI 0x031f 6151#define regSQ_SHADER_TMA_HI_BASE_IDX 0 6152#define regSQC_DSM_CNTL 0x0320 6153#define regSQC_DSM_CNTL_BASE_IDX 0 6154#define regSQC_DSM_CNTLA 0x0321 6155#define regSQC_DSM_CNTLA_BASE_IDX 0 6156#define regSQC_DSM_CNTLB 0x0322 6157#define regSQC_DSM_CNTLB_BASE_IDX 0 6158#define regSQC_DSM_CNTL2 0x0325 6159#define regSQC_DSM_CNTL2_BASE_IDX 0 6160#define regSQC_DSM_CNTL2A 0x0326 6161#define regSQC_DSM_CNTL2A_BASE_IDX 0 6162#define regSQC_DSM_CNTL2B 0x0327 6163#define regSQC_DSM_CNTL2B_BASE_IDX 0 6164#define regSQC_DSM_CNTL2E 0x032a 6165#define regSQC_DSM_CNTL2E_BASE_IDX 0 6166#define regSQC_EDC_FUE_CNTL 0x032b 6167#define regSQC_EDC_FUE_CNTL_BASE_IDX 0 6168#define regSQC_EDC_CNT2 0x032c 6169#define regSQC_EDC_CNT2_BASE_IDX 0 6170#define regSQC_EDC_CNT3 0x032d 6171#define regSQC_EDC_CNT3_BASE_IDX 0 6172#define regSQC_EDC_PARITY_CNT3 0x032e 6173#define regSQC_EDC_PARITY_CNT3_BASE_IDX 0 6174#define regSQ_DEBUG 0x0332 6175#define regSQ_DEBUG_BASE_IDX 0 6176#define regSQ_REG_TIMESTAMP 0x0374 6177#define regSQ_REG_TIMESTAMP_BASE_IDX 0 6178#define regSQ_CMD_TIMESTAMP 0x0375 6179#define regSQ_CMD_TIMESTAMP_BASE_IDX 0 6180#define regSQ_HOSTTRAP_STATUS 0x0376 6181#define regSQ_HOSTTRAP_STATUS_BASE_IDX 0 6182#define regSQ_IND_INDEX 0x0378 6183#define regSQ_IND_INDEX_BASE_IDX 0 6184#define regSQ_IND_DATA 0x0379 6185#define regSQ_IND_DATA_BASE_IDX 0 6186#define regSQ_CONFIG1 0x037a 6187#define regSQ_CONFIG1_BASE_IDX 0 6188#define regSQ_CMD 0x037b 6189#define regSQ_CMD_BASE_IDX 0 6190#define regSQ_TIME_HI 0x037c 6191#define regSQ_TIME_HI_BASE_IDX 0 6192#define regSQ_TIME_LO 0x037d 6193#define regSQ_TIME_LO_BASE_IDX 0 6194#define regSQ_DS_0 0x037f 6195#define regSQ_DS_0_BASE_IDX 0 6196#define regSQ_DS_1 0x037f 6197#define regSQ_DS_1_BASE_IDX 0 6198#define regSQ_EXP_0 0x037f 6199#define regSQ_EXP_0_BASE_IDX 0 6200#define regSQ_EXP_1 0x037f 6201#define regSQ_EXP_1_BASE_IDX 0 6202#define regSQ_FLAT_0 0x037f 6203#define regSQ_FLAT_0_BASE_IDX 0 6204#define regSQ_FLAT_1 0x037f 6205#define regSQ_FLAT_1_BASE_IDX 0 6206#define regSQ_GLBL_0 0x037f 6207#define regSQ_GLBL_0_BASE_IDX 0 6208#define regSQ_GLBL_1 0x037f 6209#define regSQ_GLBL_1_BASE_IDX 0 6210#define regSQ_INST 0x037f 6211#define regSQ_INST_BASE_IDX 0 6212#define regSQ_MIMG_0 0x037f 6213#define regSQ_MIMG_0_BASE_IDX 0 6214#define regSQ_MIMG_1 0x037f 6215#define regSQ_MIMG_1_BASE_IDX 0 6216#define regSQ_MTBUF_0 0x037f 6217#define regSQ_MTBUF_0_BASE_IDX 0 6218#define regSQ_MTBUF_1 0x037f 6219#define regSQ_MTBUF_1_BASE_IDX 0 6220#define regSQ_MUBUF_0 0x037f 6221#define regSQ_MUBUF_0_BASE_IDX 0 6222#define regSQ_MUBUF_1 0x037f 6223#define regSQ_MUBUF_1_BASE_IDX 0 6224#define regSQ_SCRATCH_0 0x037f 6225#define regSQ_SCRATCH_0_BASE_IDX 0 6226#define regSQ_SCRATCH_1 0x037f 6227#define regSQ_SCRATCH_1_BASE_IDX 0 6228#define regSQ_SMEM_0 0x037f 6229#define regSQ_SMEM_0_BASE_IDX 0 6230#define regSQ_SMEM_1 0x037f 6231#define regSQ_SMEM_1_BASE_IDX 0 6232#define regSQ_SOP1 0x037f 6233#define regSQ_SOP1_BASE_IDX 0 6234#define regSQ_SOP2 0x037f 6235#define regSQ_SOP2_BASE_IDX 0 6236#define regSQ_SOPC 0x037f 6237#define regSQ_SOPC_BASE_IDX 0 6238#define regSQ_SOPK 0x037f 6239#define regSQ_SOPK_BASE_IDX 0 6240#define regSQ_SOPP 0x037f 6241#define regSQ_SOPP_BASE_IDX 0 6242#define regSQ_VINTRP 0x037f 6243#define regSQ_VINTRP_BASE_IDX 0 6244#define regSQ_VOP1 0x037f 6245#define regSQ_VOP1_BASE_IDX 0 6246#define regSQ_VOP2 0x037f 6247#define regSQ_VOP2_BASE_IDX 0 6248#define regSQ_VOP3P_0 0x037f 6249#define regSQ_VOP3P_0_BASE_IDX 0 6250#define regSQ_VOP3P_1 0x037f 6251#define regSQ_VOP3P_1_BASE_IDX 0 6252#define regSQ_VOP3P_MFMA_0 0x037f 6253#define regSQ_VOP3P_MFMA_0_BASE_IDX 0 6254#define regSQ_VOP3P_MFMA_1 0x037f 6255#define regSQ_VOP3P_MFMA_1_BASE_IDX 0 6256#define regSQ_VOP3_0 0x037f 6257#define regSQ_VOP3_0_BASE_IDX 0 6258#define regSQ_VOP3_0_SDST_ENC 0x037f 6259#define regSQ_VOP3_0_SDST_ENC_BASE_IDX 0 6260#define regSQ_VOP3_1 0x037f 6261#define regSQ_VOP3_1_BASE_IDX 0 6262#define regSQ_VOPC 0x037f 6263#define regSQ_VOPC_BASE_IDX 0 6264#define regSQ_VOP_DPP 0x037f 6265#define regSQ_VOP_DPP_BASE_IDX 0 6266#define regSQ_VOP_SDWA 0x037f 6267#define regSQ_VOP_SDWA_BASE_IDX 0 6268#define regSQ_VOP_SDWA_SDST_ENC 0x037f 6269#define regSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0 6270#define regSQ_LB_CTR_CTRL 0x0398 6271#define regSQ_LB_CTR_CTRL_BASE_IDX 0 6272#define regSQ_LB_DATA0 0x0399 6273#define regSQ_LB_DATA0_BASE_IDX 0 6274#define regSQ_LB_DATA1 0x039a 6275#define regSQ_LB_DATA1_BASE_IDX 0 6276#define regSQ_LB_DATA2 0x039b 6277#define regSQ_LB_DATA2_BASE_IDX 0 6278#define regSQ_LB_DATA3 0x039c 6279#define regSQ_LB_DATA3_BASE_IDX 0 6280#define regSQ_LB_CTR_SEL 0x039d 6281#define regSQ_LB_CTR_SEL_BASE_IDX 0 6282#define regSQ_LB_CTR0_CU 0x039e 6283#define regSQ_LB_CTR0_CU_BASE_IDX 0 6284#define regSQ_LB_CTR1_CU 0x039f 6285#define regSQ_LB_CTR1_CU_BASE_IDX 0 6286#define regSQ_LB_CTR2_CU 0x03a0 6287#define regSQ_LB_CTR2_CU_BASE_IDX 0 6288#define regSQ_LB_CTR3_CU 0x03a1 6289#define regSQ_LB_CTR3_CU_BASE_IDX 0 6290#define regSQC_EDC_CNT 0x03a2 6291#define regSQC_EDC_CNT_BASE_IDX 0 6292#define regSQ_EDC_SEC_CNT 0x03a3 6293#define regSQ_EDC_SEC_CNT_BASE_IDX 0 6294#define regSQ_EDC_DED_CNT 0x03a4 6295#define regSQ_EDC_DED_CNT_BASE_IDX 0 6296#define regSQ_EDC_INFO 0x03a5 6297#define regSQ_EDC_INFO_BASE_IDX 0 6298#define regSQ_EDC_CNT 0x03a6 6299#define regSQ_EDC_CNT_BASE_IDX 0 6300#define regSQ_EDC_FUE_CNTL 0x03a7 6301#define regSQ_EDC_FUE_CNTL_BASE_IDX 0 6302#define regSQ_THREAD_TRACE_WORD_CMN 0x03b0 6303#define regSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0 6304#define regSQ_THREAD_TRACE_WORD_EVENT 0x03b0 6305#define regSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0 6306#define regSQ_THREAD_TRACE_WORD_INST 0x03b0 6307#define regSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0 6308#define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0 6309#define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0 6310#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0 6311#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0 6312#define regSQ_THREAD_TRACE_WORD_ISSUE 0x03b0 6313#define regSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0 6314#define regSQ_THREAD_TRACE_WORD_MISC 0x03b0 6315#define regSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0 6316#define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0 6317#define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0 6318#define regSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0 6319#define regSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0 6320#define regSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0 6321#define regSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0 6322#define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0 6323#define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0 6324#define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0 6325#define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0 6326#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0 6327#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0 6328#define regSQ_THREAD_TRACE_WORD_WAVE 0x03b0 6329#define regSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0 6330#define regSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0 6331#define regSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0 6332#define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1 6333#define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0 6334#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1 6335#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0 6336#define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1 6337#define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0 6338#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1 6339#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0 6340#define regSQ_WREXEC_EXEC_HI 0x03b1 6341#define regSQ_WREXEC_EXEC_HI_BASE_IDX 0 6342#define regSQ_WREXEC_EXEC_LO 0x03b1 6343#define regSQ_WREXEC_EXEC_LO_BASE_IDX 0 6344#define regSQ_BUF_RSRC_WORD0 0x03c0 6345#define regSQ_BUF_RSRC_WORD0_BASE_IDX 0 6346#define regSQ_BUF_RSRC_WORD1 0x03c1 6347#define regSQ_BUF_RSRC_WORD1_BASE_IDX 0 6348#define regSQ_BUF_RSRC_WORD2 0x03c2 6349#define regSQ_BUF_RSRC_WORD2_BASE_IDX 0 6350#define regSQ_BUF_RSRC_WORD3 0x03c3 6351#define regSQ_BUF_RSRC_WORD3_BASE_IDX 0 6352#define regSQ_IMG_RSRC_WORD0 0x03c4 6353#define regSQ_IMG_RSRC_WORD0_BASE_IDX 0 6354#define regSQ_IMG_RSRC_WORD1 0x03c5 6355#define regSQ_IMG_RSRC_WORD1_BASE_IDX 0 6356#define regSQ_IMG_RSRC_WORD2 0x03c6 6357#define regSQ_IMG_RSRC_WORD2_BASE_IDX 0 6358#define regSQ_IMG_RSRC_WORD3 0x03c7 6359#define regSQ_IMG_RSRC_WORD3_BASE_IDX 0 6360#define regSQ_IMG_RSRC_WORD4 0x03c8 6361#define regSQ_IMG_RSRC_WORD4_BASE_IDX 0 6362#define regSQ_IMG_RSRC_WORD5 0x03c9 6363#define regSQ_IMG_RSRC_WORD5_BASE_IDX 0 6364#define regSQ_IMG_RSRC_WORD6 0x03ca 6365#define regSQ_IMG_RSRC_WORD6_BASE_IDX 0 6366#define regSQ_IMG_RSRC_WORD7 0x03cb 6367#define regSQ_IMG_RSRC_WORD7_BASE_IDX 0 6368#define regSQ_IMG_SAMP_WORD0 0x03cc 6369#define regSQ_IMG_SAMP_WORD0_BASE_IDX 0 6370#define regSQ_IMG_SAMP_WORD1 0x03cd 6371#define regSQ_IMG_SAMP_WORD1_BASE_IDX 0 6372#define regSQ_IMG_SAMP_WORD2 0x03ce 6373#define regSQ_IMG_SAMP_WORD2_BASE_IDX 0 6374#define regSQ_IMG_SAMP_WORD3 0x03cf 6375#define regSQ_IMG_SAMP_WORD3_BASE_IDX 0 6376#define regSQ_FLAT_SCRATCH_WORD0 0x03d0 6377#define regSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0 6378#define regSQ_FLAT_SCRATCH_WORD1 0x03d1 6379#define regSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0 6380#define regSQ_M0_GPR_IDX_WORD 0x03d2 6381#define regSQ_M0_GPR_IDX_WORD_BASE_IDX 0 6382#define regSQC_ICACHE_UTCL1_CNTL1 0x03d3 6383#define regSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0 6384#define regSQC_ICACHE_UTCL1_CNTL2 0x03d4 6385#define regSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0 6386#define regSQC_DCACHE_UTCL1_CNTL1 0x03d5 6387#define regSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0 6388#define regSQC_DCACHE_UTCL1_CNTL2 0x03d6 6389#define regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0 6390#define regSQC_ICACHE_UTCL1_STATUS 0x03d7 6391#define regSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 6392#define regSQC_DCACHE_UTCL1_STATUS 0x03d8 6393#define regSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 6394 6395 6396// addressBlock: gc_tcdec 6397// base address: 0xac00 6398#define regTCP_INVALIDATE 0x0b00 6399#define regTCP_INVALIDATE_BASE_IDX 0 6400#define regTCP_STATUS 0x0b01 6401#define regTCP_STATUS_BASE_IDX 0 6402#define regTCP_CHAN_STEER_0 0x0b03 6403#define regTCP_CHAN_STEER_0_BASE_IDX 0 6404#define regTCP_CHAN_STEER_1 0x0b04 6405#define regTCP_CHAN_STEER_1_BASE_IDX 0 6406#define regTCP_ADDR_CONFIG 0x0b05 6407#define regTCP_ADDR_CONFIG_BASE_IDX 0 6408#define regTCP_CHAN_STEER_2 0x0b09 6409#define regTCP_CHAN_STEER_2_BASE_IDX 0 6410#define regTCP_CHAN_STEER_3 0x0b0a 6411#define regTCP_CHAN_STEER_3_BASE_IDX 0 6412#define regTCP_CHAN_STEER_4 0x0b0b 6413#define regTCP_CHAN_STEER_4_BASE_IDX 0 6414#define regTCP_CHAN_STEER_5 0x0b0c 6415#define regTCP_CHAN_STEER_5_BASE_IDX 0 6416#define regTCP_EDC_CNT 0x0b17 6417#define regTCP_EDC_CNT_BASE_IDX 0 6418#define regTCP_EDC_CNT_NEW 0x0b18 6419#define regTCP_EDC_CNT_NEW_BASE_IDX 0 6420#define regTC_CFG_L1_LOAD_POLICY0 0x0b1a 6421#define regTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0 6422#define regTC_CFG_L1_LOAD_POLICY1 0x0b1b 6423#define regTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0 6424#define regTC_CFG_L1_STORE_POLICY 0x0b1c 6425#define regTC_CFG_L1_STORE_POLICY_BASE_IDX 0 6426#define regTC_CFG_L2_LOAD_POLICY0 0x0b1d 6427#define regTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0 6428#define regTC_CFG_L2_LOAD_POLICY1 0x0b1e 6429#define regTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0 6430#define regTC_CFG_L2_STORE_POLICY0 0x0b1f 6431#define regTC_CFG_L2_STORE_POLICY0_BASE_IDX 0 6432#define regTC_CFG_L2_STORE_POLICY1 0x0b20 6433#define regTC_CFG_L2_STORE_POLICY1_BASE_IDX 0 6434#define regTC_CFG_L2_ATOMIC_POLICY 0x0b21 6435#define regTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0 6436#define regTC_CFG_L1_VOLATILE 0x0b22 6437#define regTC_CFG_L1_VOLATILE_BASE_IDX 0 6438#define regTC_CFG_L2_VOLATILE 0x0b23 6439#define regTC_CFG_L2_VOLATILE_BASE_IDX 0 6440#define regTCI_MISC 0x0b5c 6441#define regTCI_MISC_BASE_IDX 0 6442#define regTCI_CNTL_3 0x0b5d 6443#define regTCI_CNTL_3_BASE_IDX 0 6444#define regTCI_DSM_CNTL 0x0b5e 6445#define regTCI_DSM_CNTL_BASE_IDX 0 6446#define regTCI_DSM_CNTL2 0x0b5f 6447#define regTCI_DSM_CNTL2_BASE_IDX 0 6448#define regTCI_EDC_CNT 0x0b60 6449#define regTCI_EDC_CNT_BASE_IDX 0 6450#define regTCI_STATUS 0x0b61 6451#define regTCI_STATUS_BASE_IDX 0 6452#define regTCI_CNTL_1 0x0b62 6453#define regTCI_CNTL_1_BASE_IDX 0 6454#define regTCI_CNTL_2 0x0b63 6455#define regTCI_CNTL_2_BASE_IDX 0 6456#define regTCC_CTRL 0x0b80 6457#define regTCC_CTRL_BASE_IDX 0 6458#define regTCC_CTRL2 0x0b81 6459#define regTCC_CTRL2_BASE_IDX 0 6460#define regTCC_EDC_CNT 0x0b82 6461#define regTCC_EDC_CNT_BASE_IDX 0 6462#define regTCC_EDC_CNT2 0x0b83 6463#define regTCC_EDC_CNT2_BASE_IDX 0 6464#define regTCC_REDUNDANCY 0x0b84 6465#define regTCC_REDUNDANCY_BASE_IDX 0 6466#define regTCC_EXE_DISABLE 0x0b85 6467#define regTCC_EXE_DISABLE_BASE_IDX 0 6468#define regTCC_DSM_CNTL 0x0b86 6469#define regTCC_DSM_CNTL_BASE_IDX 0 6470#define regTCC_DSM_CNTLA 0x0b87 6471#define regTCC_DSM_CNTLA_BASE_IDX 0 6472#define regTCC_DSM_CNTL2 0x0b88 6473#define regTCC_DSM_CNTL2_BASE_IDX 0 6474#define regTCC_DSM_CNTL2A 0x0b89 6475#define regTCC_DSM_CNTL2A_BASE_IDX 0 6476#define regTCC_DSM_CNTL2B 0x0b8a 6477#define regTCC_DSM_CNTL2B_BASE_IDX 0 6478#define regTCC_WBINVL2 0x0b8b 6479#define regTCC_WBINVL2_BASE_IDX 0 6480#define regTCC_SOFT_RESET 0x0b8c 6481#define regTCC_SOFT_RESET_BASE_IDX 0 6482#define regTCC_DSM_CNTL3 0x0b8e 6483#define regTCC_DSM_CNTL3_BASE_IDX 0 6484#define regTCA_CTRL 0x0bc0 6485#define regTCA_CTRL_BASE_IDX 0 6486#define regTCA_BURST_MASK 0x0bc1 6487#define regTCA_BURST_MASK_BASE_IDX 0 6488#define regTCA_BURST_CTRL 0x0bc2 6489#define regTCA_BURST_CTRL_BASE_IDX 0 6490#define regTCA_DSM_CNTL 0x0bc3 6491#define regTCA_DSM_CNTL_BASE_IDX 0 6492#define regTCA_DSM_CNTL2 0x0bc4 6493#define regTCA_DSM_CNTL2_BASE_IDX 0 6494#define regTCA_EDC_CNT 0x0bc5 6495#define regTCA_EDC_CNT_BASE_IDX 0 6496#define regTCX_CTRL 0x0bc6 6497#define regTCX_CTRL_BASE_IDX 0 6498#define regTCX_DSM_CNTL 0x0bc7 6499#define regTCX_DSM_CNTL_BASE_IDX 0 6500#define regTCX_DSM_CNTL2 0x0bc8 6501#define regTCX_DSM_CNTL2_BASE_IDX 0 6502#define regTCX_EDC_CNT 0x0bc9 6503#define regTCX_EDC_CNT_BASE_IDX 0 6504#define regTCX_EDC_CNT2 0x0bca 6505#define regTCX_EDC_CNT2_BASE_IDX 0 6506 6507 6508// addressBlock: gc_tcpdec 6509// base address: 0xca80 6510#define regTCP_WATCH0_ADDR_H 0x12a0 6511#define regTCP_WATCH0_ADDR_H_BASE_IDX 0 6512#define regTCP_WATCH0_ADDR_L 0x12a1 6513#define regTCP_WATCH0_ADDR_L_BASE_IDX 0 6514#define regTCP_WATCH0_CNTL 0x12a2 6515#define regTCP_WATCH0_CNTL_BASE_IDX 0 6516#define regTCP_WATCH1_ADDR_H 0x12a3 6517#define regTCP_WATCH1_ADDR_H_BASE_IDX 0 6518#define regTCP_WATCH1_ADDR_L 0x12a4 6519#define regTCP_WATCH1_ADDR_L_BASE_IDX 0 6520#define regTCP_WATCH1_CNTL 0x12a5 6521#define regTCP_WATCH1_CNTL_BASE_IDX 0 6522#define regTCP_WATCH2_ADDR_H 0x12a6 6523#define regTCP_WATCH2_ADDR_H_BASE_IDX 0 6524#define regTCP_WATCH2_ADDR_L 0x12a7 6525#define regTCP_WATCH2_ADDR_L_BASE_IDX 0 6526#define regTCP_WATCH2_CNTL 0x12a8 6527#define regTCP_WATCH2_CNTL_BASE_IDX 0 6528#define regTCP_WATCH3_ADDR_H 0x12a9 6529#define regTCP_WATCH3_ADDR_H_BASE_IDX 0 6530#define regTCP_WATCH3_ADDR_L 0x12aa 6531#define regTCP_WATCH3_ADDR_L_BASE_IDX 0 6532#define regTCP_WATCH3_CNTL 0x12ab 6533#define regTCP_WATCH3_CNTL_BASE_IDX 0 6534#define regTCP_GATCL1_CNTL 0x12b0 6535#define regTCP_GATCL1_CNTL_BASE_IDX 0 6536#define regTCP_ATC_EDC_GATCL1_CNT 0x12b1 6537#define regTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0 6538#define regTCP_GATCL1_DSM_CNTL 0x12b2 6539#define regTCP_GATCL1_DSM_CNTL_BASE_IDX 0 6540#define regTCP_DSM_CNTL 0x12b3 6541#define regTCP_DSM_CNTL_BASE_IDX 0 6542#define regTCP_UTCL1_CNTL1 0x12b5 6543#define regTCP_UTCL1_CNTL1_BASE_IDX 0 6544#define regTCP_UTCL1_CNTL2 0x12b6 6545#define regTCP_UTCL1_CNTL2_BASE_IDX 0 6546#define regTCP_UTCL1_STATUS 0x12b7 6547#define regTCP_UTCL1_STATUS_BASE_IDX 0 6548#define regTCP_DSM_CNTL2 0x12b8 6549#define regTCP_DSM_CNTL2_BASE_IDX 0 6550#define regTCP_PERFCOUNTER_FILTER 0x12b9 6551#define regTCP_PERFCOUNTER_FILTER_BASE_IDX 0 6552#define regTCP_PERFCOUNTER_FILTER_EN 0x12ba 6553#define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0 6554 6555 6556// addressBlock: gc_tpdec 6557// base address: 0x9400 6558#define regTD_STATUS 0x0526 6559#define regTD_STATUS_BASE_IDX 0 6560#define regTD_EDC_CNT 0x052e 6561#define regTD_EDC_CNT_BASE_IDX 0 6562#define regTD_DSM_CNTL 0x052f 6563#define regTD_DSM_CNTL_BASE_IDX 0 6564#define regTD_DSM_CNTL2 0x0530 6565#define regTD_DSM_CNTL2_BASE_IDX 0 6566#define regTD_SCRATCH 0x0533 6567#define regTD_SCRATCH_BASE_IDX 0 6568#define regTA_CNTL 0x0541 6569#define regTA_CNTL_BASE_IDX 0 6570#define regTA_CNTL_AUX 0x0542 6571#define regTA_CNTL_AUX_BASE_IDX 0 6572#define regTA_FEATURE_CNTL 0x0543 6573#define regTA_FEATURE_CNTL_BASE_IDX 0 6574#define regTA_STATUS 0x0548 6575#define regTA_STATUS_BASE_IDX 0 6576#define regTA_SCRATCH 0x0564 6577#define regTA_SCRATCH_BASE_IDX 0 6578#define regTA_DSM_CNTL 0x0584 6579#define regTA_DSM_CNTL_BASE_IDX 0 6580#define regTA_DSM_CNTL2 0x0585 6581#define regTA_DSM_CNTL2_BASE_IDX 0 6582#define regTA_EDC_CNT 0x0586 6583#define regTA_EDC_CNT_BASE_IDX 0 6584 6585 6586// addressBlock: gc_utcl2_atcl2dec 6587// base address: 0xa000 6588#define regATC_L2_CNTL 0x0800 6589#define regATC_L2_CNTL_BASE_IDX 0 6590#define regATC_L2_CNTL2 0x0801 6591#define regATC_L2_CNTL2_BASE_IDX 0 6592#define regATC_L2_CACHE_DATA0 0x0804 6593#define regATC_L2_CACHE_DATA0_BASE_IDX 0 6594#define regATC_L2_CACHE_DATA1 0x0805 6595#define regATC_L2_CACHE_DATA1_BASE_IDX 0 6596#define regATC_L2_CACHE_DATA2 0x0806 6597#define regATC_L2_CACHE_DATA2_BASE_IDX 0 6598#define regATC_L2_CACHE_DATA3 0x0807 6599#define regATC_L2_CACHE_DATA3_BASE_IDX 0 6600#define regATC_L2_CNTL3 0x0808 6601#define regATC_L2_CNTL3_BASE_IDX 0 6602#define regATC_L2_STATUS 0x0809 6603#define regATC_L2_STATUS_BASE_IDX 0 6604#define regATC_L2_STATUS2 0x080a 6605#define regATC_L2_STATUS2_BASE_IDX 0 6606#define regATC_L2_MISC_CG 0x080b 6607#define regATC_L2_MISC_CG_BASE_IDX 0 6608#define regATC_L2_MEM_POWER_LS 0x080c 6609#define regATC_L2_MEM_POWER_LS_BASE_IDX 0 6610#define regATC_L2_CGTT_CLK_CTRL 0x080d 6611#define regATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 6612#define regATC_L2_CACHE_4K_DSM_INDEX 0x080e 6613#define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0 6614#define regATC_L2_CACHE_32K_DSM_INDEX 0x080f 6615#define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX 0 6616#define regATC_L2_CACHE_2M_DSM_INDEX 0x0810 6617#define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0 6618#define regATC_L2_CACHE_4K_DSM_CNTL 0x0811 6619#define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0 6620#define regATC_L2_CACHE_32K_DSM_CNTL 0x0812 6621#define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX 0 6622#define regATC_L2_CACHE_2M_DSM_CNTL 0x0813 6623#define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0 6624#define regATC_L2_CNTL4 0x0814 6625#define regATC_L2_CNTL4_BASE_IDX 0 6626#define regATC_L2_MM_GROUP_RT_CLASSES 0x0815 6627#define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 6628 6629 6630// addressBlock: gc_utcl2_atcl2pfcntldec 6631// base address: 0x37500 6632#define regATC_L2_PERFCOUNTER0_CFG 0x3d40 6633#define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 6634#define regATC_L2_PERFCOUNTER1_CFG 0x3d41 6635#define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 6636#define regATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42 6637#define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 6638 6639 6640// addressBlock: gc_utcl2_atcl2pfcntrdec 6641// base address: 0x35400 6642#define regATC_L2_PERFCOUNTER_LO 0x3500 6643#define regATC_L2_PERFCOUNTER_LO_BASE_IDX 1 6644#define regATC_L2_PERFCOUNTER_HI 0x3501 6645#define regATC_L2_PERFCOUNTER_HI_BASE_IDX 1 6646 6647 6648// addressBlock: gc_utcl2_l2tlbdec 6649// base address: 0xa640 6650#define regL2TLB_TLB0_STATUS 0x0991 6651#define regL2TLB_TLB0_STATUS_BASE_IDX 0 6652#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0993 6653#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 6654#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0994 6655#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 6656#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0995 6657#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 6658#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0996 6659#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 6660 6661 6662// addressBlock: gc_utcl2_l2tlbpldec 6663// base address: 0x37570 6664#define regL2TLB_PERFCOUNTER0_CFG 0x3d5c 6665#define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 6666#define regL2TLB_PERFCOUNTER1_CFG 0x3d5d 6667#define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 6668#define regL2TLB_PERFCOUNTER2_CFG 0x3d5e 6669#define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 6670#define regL2TLB_PERFCOUNTER3_CFG 0x3d5f 6671#define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 6672#define regL2TLB_PERFCOUNTER_RSLT_CNTL 0x3d60 6673#define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 6674 6675 6676// addressBlock: gc_utcl2_l2tlbprdec 6677// base address: 0x35460 6678#define regL2TLB_PERFCOUNTER_LO 0x3518 6679#define regL2TLB_PERFCOUNTER_LO_BASE_IDX 1 6680#define regL2TLB_PERFCOUNTER_HI 0x3519 6681#define regL2TLB_PERFCOUNTER_HI_BASE_IDX 1 6682 6683 6684// addressBlock: gc_utcl2_vml2pfdec 6685// base address: 0xa100 6686#define regVM_L2_CNTL 0x0840 6687#define regVM_L2_CNTL_BASE_IDX 0 6688#define regVM_L2_CNTL2 0x0841 6689#define regVM_L2_CNTL2_BASE_IDX 0 6690#define regVM_L2_CNTL3 0x0842 6691#define regVM_L2_CNTL3_BASE_IDX 0 6692#define regVM_L2_STATUS 0x0843 6693#define regVM_L2_STATUS_BASE_IDX 0 6694#define regVM_DUMMY_PAGE_FAULT_CNTL 0x0844 6695#define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 6696#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845 6697#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 6698#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846 6699#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 6700#define regVM_L2_PROTECTION_FAULT_CNTL 0x0847 6701#define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 6702#define regVM_L2_PROTECTION_FAULT_CNTL2 0x0848 6703#define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 6704#define regVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849 6705#define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 6706#define regVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a 6707#define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 6708#define regVM_L2_PROTECTION_FAULT_STATUS 0x084b 6709#define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 6710#define regVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c 6711#define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 6712#define regVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d 6713#define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 6714#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e 6715#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 6716#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f 6717#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 6718#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851 6719#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 6720#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852 6721#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 6722#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853 6723#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 6724#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854 6725#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 6726#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855 6727#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 6728#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856 6729#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 6730#define regVM_L2_CNTL4 0x0857 6731#define regVM_L2_CNTL4_BASE_IDX 0 6732#define regVM_L2_MM_GROUP_RT_CLASSES 0x0858 6733#define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 6734#define regVM_L2_BANK_SELECT_RESERVED_CID 0x0859 6735#define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 6736#define regVM_L2_BANK_SELECT_RESERVED_CID2 0x085a 6737#define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 6738#define regVM_L2_CACHE_PARITY_CNTL 0x085b 6739#define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 6740#define regVM_L2_CGTT_CLK_CTRL 0x085e 6741#define regVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 6742#define regVM_L2_CGTT_BUSY_CTRL 0x085f 6743#define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 6744#define regVML2_MEM_ECC_INDEX 0x0861 6745#define regVML2_MEM_ECC_INDEX_BASE_IDX 0 6746#define regVML2_WALKER_MEM_ECC_INDEX 0x0862 6747#define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0 6748#define regUTCL2_MEM_ECC_INDEX 0x0863 6749#define regUTCL2_MEM_ECC_INDEX_BASE_IDX 0 6750#define regVML2_MEM_ECC_CNTL 0x0864 6751#define regVML2_MEM_ECC_CNTL_BASE_IDX 0 6752#define regVML2_WALKER_MEM_ECC_CNTL 0x0865 6753#define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0 6754#define regUTCL2_MEM_ECC_CNTL 0x0866 6755#define regUTCL2_MEM_ECC_CNTL_BASE_IDX 0 6756#define regVML2_MEM_ECC_STATUS 0x0867 6757#define regVML2_MEM_ECC_STATUS_BASE_IDX 0 6758#define regVML2_WALKER_MEM_ECC_STATUS 0x0868 6759#define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX 0 6760#define regUTCL2_MEM_ECC_STATUS 0x0869 6761#define regUTCL2_MEM_ECC_STATUS_BASE_IDX 0 6762#define regUTCL2_EDC_MODE 0x086a 6763#define regUTCL2_EDC_MODE_BASE_IDX 0 6764#define regUTCL2_EDC_CONFIG 0x086b 6765#define regUTCL2_EDC_CONFIG_BASE_IDX 0 6766 6767 6768// addressBlock: gc_utcl2_vml2pldec 6769// base address: 0x37530 6770#define regMC_VM_L2_PERFCOUNTER0_CFG 0x3d4c 6771#define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 6772#define regMC_VM_L2_PERFCOUNTER1_CFG 0x3d4d 6773#define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 6774#define regMC_VM_L2_PERFCOUNTER2_CFG 0x3d4e 6775#define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 6776#define regMC_VM_L2_PERFCOUNTER3_CFG 0x3d4f 6777#define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 6778#define regMC_VM_L2_PERFCOUNTER4_CFG 0x3d50 6779#define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 6780#define regMC_VM_L2_PERFCOUNTER5_CFG 0x3d51 6781#define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 6782#define regMC_VM_L2_PERFCOUNTER6_CFG 0x3d52 6783#define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 6784#define regMC_VM_L2_PERFCOUNTER7_CFG 0x3d53 6785#define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 6786#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d54 6787#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 6788 6789 6790// addressBlock: gc_utcl2_vml2prdec 6791// base address: 0x35420 6792#define regMC_VM_L2_PERFCOUNTER_LO 0x3508 6793#define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 6794#define regMC_VM_L2_PERFCOUNTER_HI 0x3509 6795#define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 6796 6797 6798// addressBlock: gc_utcl2_vml2vcdec 6799// base address: 0xa200 6800#define regVM_CONTEXT0_CNTL 0x0880 6801#define regVM_CONTEXT0_CNTL_BASE_IDX 0 6802#define regVM_CONTEXT1_CNTL 0x0881 6803#define regVM_CONTEXT1_CNTL_BASE_IDX 0 6804#define regVM_CONTEXT2_CNTL 0x0882 6805#define regVM_CONTEXT2_CNTL_BASE_IDX 0 6806#define regVM_CONTEXT3_CNTL 0x0883 6807#define regVM_CONTEXT3_CNTL_BASE_IDX 0 6808#define regVM_CONTEXT4_CNTL 0x0884 6809#define regVM_CONTEXT4_CNTL_BASE_IDX 0 6810#define regVM_CONTEXT5_CNTL 0x0885 6811#define regVM_CONTEXT5_CNTL_BASE_IDX 0 6812#define regVM_CONTEXT6_CNTL 0x0886 6813#define regVM_CONTEXT6_CNTL_BASE_IDX 0 6814#define regVM_CONTEXT7_CNTL 0x0887 6815#define regVM_CONTEXT7_CNTL_BASE_IDX 0 6816#define regVM_CONTEXT8_CNTL 0x0888 6817#define regVM_CONTEXT8_CNTL_BASE_IDX 0 6818#define regVM_CONTEXT9_CNTL 0x0889 6819#define regVM_CONTEXT9_CNTL_BASE_IDX 0 6820#define regVM_CONTEXT10_CNTL 0x088a 6821#define regVM_CONTEXT10_CNTL_BASE_IDX 0 6822#define regVM_CONTEXT11_CNTL 0x088b 6823#define regVM_CONTEXT11_CNTL_BASE_IDX 0 6824#define regVM_CONTEXT12_CNTL 0x088c 6825#define regVM_CONTEXT12_CNTL_BASE_IDX 0 6826#define regVM_CONTEXT13_CNTL 0x088d 6827#define regVM_CONTEXT13_CNTL_BASE_IDX 0 6828#define regVM_CONTEXT14_CNTL 0x088e 6829#define regVM_CONTEXT14_CNTL_BASE_IDX 0 6830#define regVM_CONTEXT15_CNTL 0x088f 6831#define regVM_CONTEXT15_CNTL_BASE_IDX 0 6832#define regVM_CONTEXTS_DISABLE 0x0890 6833#define regVM_CONTEXTS_DISABLE_BASE_IDX 0 6834#define regVM_INVALIDATE_ENG0_SEM 0x0891 6835#define regVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 6836#define regVM_INVALIDATE_ENG1_SEM 0x0892 6837#define regVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 6838#define regVM_INVALIDATE_ENG2_SEM 0x0893 6839#define regVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 6840#define regVM_INVALIDATE_ENG3_SEM 0x0894 6841#define regVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 6842#define regVM_INVALIDATE_ENG4_SEM 0x0895 6843#define regVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 6844#define regVM_INVALIDATE_ENG5_SEM 0x0896 6845#define regVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 6846#define regVM_INVALIDATE_ENG6_SEM 0x0897 6847#define regVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 6848#define regVM_INVALIDATE_ENG7_SEM 0x0898 6849#define regVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 6850#define regVM_INVALIDATE_ENG8_SEM 0x0899 6851#define regVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 6852#define regVM_INVALIDATE_ENG9_SEM 0x089a 6853#define regVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 6854#define regVM_INVALIDATE_ENG10_SEM 0x089b 6855#define regVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 6856#define regVM_INVALIDATE_ENG11_SEM 0x089c 6857#define regVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 6858#define regVM_INVALIDATE_ENG12_SEM 0x089d 6859#define regVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 6860#define regVM_INVALIDATE_ENG13_SEM 0x089e 6861#define regVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 6862#define regVM_INVALIDATE_ENG14_SEM 0x089f 6863#define regVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 6864#define regVM_INVALIDATE_ENG15_SEM 0x08a0 6865#define regVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 6866#define regVM_INVALIDATE_ENG16_SEM 0x08a1 6867#define regVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 6868#define regVM_INVALIDATE_ENG17_SEM 0x08a2 6869#define regVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 6870#define regVM_INVALIDATE_ENG0_REQ 0x08a3 6871#define regVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 6872#define regVM_INVALIDATE_ENG1_REQ 0x08a4 6873#define regVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 6874#define regVM_INVALIDATE_ENG2_REQ 0x08a5 6875#define regVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 6876#define regVM_INVALIDATE_ENG3_REQ 0x08a6 6877#define regVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 6878#define regVM_INVALIDATE_ENG4_REQ 0x08a7 6879#define regVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 6880#define regVM_INVALIDATE_ENG5_REQ 0x08a8 6881#define regVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 6882#define regVM_INVALIDATE_ENG6_REQ 0x08a9 6883#define regVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 6884#define regVM_INVALIDATE_ENG7_REQ 0x08aa 6885#define regVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 6886#define regVM_INVALIDATE_ENG8_REQ 0x08ab 6887#define regVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 6888#define regVM_INVALIDATE_ENG9_REQ 0x08ac 6889#define regVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 6890#define regVM_INVALIDATE_ENG10_REQ 0x08ad 6891#define regVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 6892#define regVM_INVALIDATE_ENG11_REQ 0x08ae 6893#define regVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 6894#define regVM_INVALIDATE_ENG12_REQ 0x08af 6895#define regVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 6896#define regVM_INVALIDATE_ENG13_REQ 0x08b0 6897#define regVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 6898#define regVM_INVALIDATE_ENG14_REQ 0x08b1 6899#define regVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 6900#define regVM_INVALIDATE_ENG15_REQ 0x08b2 6901#define regVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 6902#define regVM_INVALIDATE_ENG16_REQ 0x08b3 6903#define regVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 6904#define regVM_INVALIDATE_ENG17_REQ 0x08b4 6905#define regVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 6906#define regVM_INVALIDATE_ENG0_ACK 0x08b5 6907#define regVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 6908#define regVM_INVALIDATE_ENG1_ACK 0x08b6 6909#define regVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 6910#define regVM_INVALIDATE_ENG2_ACK 0x08b7 6911#define regVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 6912#define regVM_INVALIDATE_ENG3_ACK 0x08b8 6913#define regVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 6914#define regVM_INVALIDATE_ENG4_ACK 0x08b9 6915#define regVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 6916#define regVM_INVALIDATE_ENG5_ACK 0x08ba 6917#define regVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 6918#define regVM_INVALIDATE_ENG6_ACK 0x08bb 6919#define regVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 6920#define regVM_INVALIDATE_ENG7_ACK 0x08bc 6921#define regVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 6922#define regVM_INVALIDATE_ENG8_ACK 0x08bd 6923#define regVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 6924#define regVM_INVALIDATE_ENG9_ACK 0x08be 6925#define regVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 6926#define regVM_INVALIDATE_ENG10_ACK 0x08bf 6927#define regVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 6928#define regVM_INVALIDATE_ENG11_ACK 0x08c0 6929#define regVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 6930#define regVM_INVALIDATE_ENG12_ACK 0x08c1 6931#define regVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 6932#define regVM_INVALIDATE_ENG13_ACK 0x08c2 6933#define regVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 6934#define regVM_INVALIDATE_ENG14_ACK 0x08c3 6935#define regVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 6936#define regVM_INVALIDATE_ENG15_ACK 0x08c4 6937#define regVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 6938#define regVM_INVALIDATE_ENG16_ACK 0x08c5 6939#define regVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 6940#define regVM_INVALIDATE_ENG17_ACK 0x08c6 6941#define regVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 6942#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7 6943#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 6944#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8 6945#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 6946#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9 6947#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 6948#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca 6949#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 6950#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb 6951#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 6952#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc 6953#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 6954#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd 6955#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 6956#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce 6957#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 6958#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf 6959#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 6960#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0 6961#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 6962#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1 6963#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 6964#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2 6965#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 6966#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3 6967#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 6968#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4 6969#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 6970#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5 6971#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 6972#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6 6973#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 6974#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7 6975#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 6976#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8 6977#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 6978#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9 6979#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 6980#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da 6981#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 6982#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db 6983#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 6984#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc 6985#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 6986#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd 6987#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 6988#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de 6989#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 6990#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df 6991#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 6992#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0 6993#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 6994#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1 6995#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 6996#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2 6997#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 6998#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3 6999#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 7000#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4
7001#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 7002#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5 7003#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 7004#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6 7005#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 7006#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7 7007#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 7008#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8 7009#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 7010#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9 7011#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 7012#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea 7013#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 7014#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb 7015#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7016#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec 7017#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7018#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed 7019#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7020#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee 7021#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7022#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef 7023#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7024#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0 7025#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7026#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1 7027#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7028#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2 7029#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7030#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3 7031#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7032#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4 7033#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7034#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5 7035#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7036#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6 7037#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7038#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7 7039#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7040#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8 7041#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7042#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9 7043#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7044#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa 7045#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7046#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb 7047#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7048#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc 7049#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7050#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd 7051#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7052#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe 7053#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7054#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff 7055#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7056#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900 7057#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7058#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901 7059#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7060#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902 7061#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7062#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903 7063#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7064#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904 7065#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7066#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905 7067#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7068#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906 7069#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7070#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907 7071#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7072#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908 7073#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7074#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909 7075#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 7076#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a 7077#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 7078#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b 7079#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7080#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c 7081#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7082#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d 7083#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7084#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e 7085#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7086#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f 7087#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7088#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910 7089#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7090#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911 7091#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7092#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912 7093#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7094#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913 7095#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7096#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914 7097#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7098#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915 7099#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7100#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916 7101#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7102#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917 7103#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7104#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918 7105#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7106#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919 7107#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7108#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a 7109#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7110#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b 7111#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7112#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c 7113#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7114#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d 7115#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7116#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e 7117#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7118#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f 7119#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7120#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920 7121#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7122#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921 7123#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7124#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922 7125#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7126#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923 7127#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7128#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924 7129#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7130#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925 7131#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7132#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926 7133#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7134#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927 7135#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7136#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928 7137#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7138#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929 7139#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 7140#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a 7141#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 7142#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b 7143#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7144#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c 7145#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7146#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d 7147#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7148#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e 7149#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7150#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f 7151#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7152#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930 7153#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7154#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931 7155#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7156#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932 7157#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7158#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933 7159#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7160#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934 7161#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7162#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935 7163#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7164#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936 7165#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7166#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937 7167#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7168#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938 7169#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7170#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939 7171#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7172#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a 7173#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7174#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b 7175#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7176#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c 7177#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7178#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d 7179#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7180#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e 7181#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7182#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f 7183#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7184#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940 7185#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7186#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941 7187#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7188#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942 7189#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7190#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943 7191#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7192#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944 7193#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7194#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945 7195#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7196#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946 7197#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7198#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947 7199#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7200#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948 7201#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7202#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949 7203#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 7204#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a 7205#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 7206 7207 7208// addressBlock: gc_utcl2_vmsharedhvdec 7209// base address: 0x3ea00 7210#define regMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 7211#define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 7212#define regMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 7213#define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 7214#define regMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 7215#define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 7216#define regMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 7217#define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 7218#define regMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 7219#define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 7220#define regMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 7221#define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 7222#define regMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 7223#define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 7224#define regMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 7225#define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 7226#define regMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 7227#define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 7228#define regMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 7229#define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 7230#define regMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a 7231#define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 7232#define regMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b 7233#define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 7234#define regMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c 7235#define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 7236#define regMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d 7237#define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 7238#define regMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e 7239#define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 7240#define regMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f 7241#define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 7242#define regMC_VM_MARC_BASE_LO_0 0x5a91 7243#define regMC_VM_MARC_BASE_LO_0_BASE_IDX 1 7244#define regMC_VM_MARC_BASE_LO_1 0x5a92 7245#define regMC_VM_MARC_BASE_LO_1_BASE_IDX 1 7246#define regMC_VM_MARC_BASE_LO_2 0x5a93 7247#define regMC_VM_MARC_BASE_LO_2_BASE_IDX 1 7248#define regMC_VM_MARC_BASE_LO_3 0x5a94 7249#define regMC_VM_MARC_BASE_LO_3_BASE_IDX 1 7250#define regMC_VM_MARC_BASE_HI_0 0x5a95 7251#define regMC_VM_MARC_BASE_HI_0_BASE_IDX 1 7252#define regMC_VM_MARC_BASE_HI_1 0x5a96 7253#define regMC_VM_MARC_BASE_HI_1_BASE_IDX 1 7254#define regMC_VM_MARC_BASE_HI_2 0x5a97 7255#define regMC_VM_MARC_BASE_HI_2_BASE_IDX 1 7256#define regMC_VM_MARC_BASE_HI_3 0x5a98 7257#define regMC_VM_MARC_BASE_HI_3_BASE_IDX 1 7258#define regMC_VM_MARC_RELOC_LO_0 0x5a99 7259#define regMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 7260#define regMC_VM_MARC_RELOC_LO_1 0x5a9a 7261#define regMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 7262#define regMC_VM_MARC_RELOC_LO_2 0x5a9b 7263#define regMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 7264#define regMC_VM_MARC_RELOC_LO_3 0x5a9c 7265#define regMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 7266#define regMC_VM_MARC_RELOC_HI_0 0x5a9d 7267#define regMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 7268#define regMC_VM_MARC_RELOC_HI_1 0x5a9e 7269#define regMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 7270#define regMC_VM_MARC_RELOC_HI_2 0x5a9f 7271#define regMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 7272#define regMC_VM_MARC_RELOC_HI_3 0x5aa0 7273#define regMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 7274#define regMC_VM_MARC_LEN_LO_0 0x5aa1 7275#define regMC_VM_MARC_LEN_LO_0_BASE_IDX 1 7276#define regMC_VM_MARC_LEN_LO_1 0x5aa2 7277#define regMC_VM_MARC_LEN_LO_1_BASE_IDX 1 7278#define regMC_VM_MARC_LEN_LO_2 0x5aa3 7279#define regMC_VM_MARC_LEN_LO_2_BASE_IDX 1 7280#define regMC_VM_MARC_LEN_LO_3 0x5aa4 7281#define regMC_VM_MARC_LEN_LO_3_BASE_IDX 1 7282#define regMC_VM_MARC_LEN_HI_0 0x5aa5 7283#define regMC_VM_MARC_LEN_HI_0_BASE_IDX 1 7284#define regMC_VM_MARC_LEN_HI_1 0x5aa6 7285#define regMC_VM_MARC_LEN_HI_1_BASE_IDX 1 7286#define regMC_VM_MARC_LEN_HI_2 0x5aa7 7287#define regMC_VM_MARC_LEN_HI_2_BASE_IDX 1 7288#define regMC_VM_MARC_LEN_HI_3 0x5aa8 7289#define regMC_VM_MARC_LEN_HI_3_BASE_IDX 1 7290#define regVM_PCIE_ATS_CNTL 0x5aab 7291#define regVM_PCIE_ATS_CNTL_BASE_IDX 1 7292#define regVM_PCIE_ATS_CNTL_VF_0 0x5aac 7293#define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 7294#define regVM_PCIE_ATS_CNTL_VF_1 0x5aad 7295#define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 7296#define regVM_PCIE_ATS_CNTL_VF_2 0x5aae 7297#define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 7298#define regVM_PCIE_ATS_CNTL_VF_3 0x5aaf 7299#define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 7300#define regVM_PCIE_ATS_CNTL_VF_4 0x5ab0 7301#define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 7302#define regVM_PCIE_ATS_CNTL_VF_5 0x5ab1 7303#define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 7304#define regVM_PCIE_ATS_CNTL_VF_6 0x5ab2 7305#define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 7306#define regVM_PCIE_ATS_CNTL_VF_7 0x5ab3 7307#define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 7308#define regVM_PCIE_ATS_CNTL_VF_8 0x5ab4 7309#define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 7310#define regVM_PCIE_ATS_CNTL_VF_9 0x5ab5 7311#define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 7312#define regVM_PCIE_ATS_CNTL_VF_10 0x5ab6 7313#define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 7314#define regVM_PCIE_ATS_CNTL_VF_11 0x5ab7 7315#define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 7316#define regVM_PCIE_ATS_CNTL_VF_12 0x5ab8 7317#define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 7318#define regVM_PCIE_ATS_CNTL_VF_13 0x5ab9 7319#define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 7320#define regVM_PCIE_ATS_CNTL_VF_14 0x5aba 7321#define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 7322#define regVM_PCIE_ATS_CNTL_VF_15 0x5abb 7323#define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 7324#define regMC_SHARED_ACTIVE_FCN_ID 0x5abc 7325#define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 7326#define regMC_VM_XGMI_GPUIOV_ENABLE 0x5abd 7327#define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 7328 7329 7330// addressBlock: gc_utcl2_vmsharedpfdec 7331// base address: 0xa590 7332#define regMC_VM_FB_OFFSET 0x096b 7333#define regMC_VM_FB_OFFSET_BASE_IDX 0 7334#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c 7335#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 7336#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d 7337#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 7338#define regMC_VM_STEERING 0x096e 7339#define regMC_VM_STEERING_BASE_IDX 0 7340#define regMC_SHARED_VIRT_RESET_REQ 0x096f 7341#define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 7342#define regMC_MEM_POWER_LS 0x0970 7343#define regMC_MEM_POWER_LS_BASE_IDX 0 7344#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971 7345#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 7346#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972 7347#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 7348#define regMC_VM_APT_CNTL 0x0973 7349#define regMC_VM_APT_CNTL_BASE_IDX 0 7350#define regMC_VM_LOCAL_HBM_ADDRESS_START 0x0974 7351#define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 7352#define regMC_VM_LOCAL_HBM_ADDRESS_END 0x0975 7353#define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 7354#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976 7355#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 7356#define regUTCL2_CGTT_CLK_CTRL 0x0977 7357#define regUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 7358#define regMC_VM_XGMI_LFB_CNTL 0x0978 7359#define regMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 7360#define regMC_VM_XGMI_LFB_SIZE 0x0979 7361#define regMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 7362#define regMC_VM_CACHEABLE_DRAM_CNTL 0x097a 7363#define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 7364#define regMC_VM_HOST_MAPPING 0x097b 7365#define regMC_VM_HOST_MAPPING_BASE_IDX 0 7366 7367 7368// addressBlock: gc_utcl2_vmsharedvcdec 7369// base address: 0xa600 7370#define regMC_VM_FB_LOCATION_BASE 0x0980 7371#define regMC_VM_FB_LOCATION_BASE_BASE_IDX 0 7372#define regMC_VM_FB_LOCATION_TOP 0x0981 7373#define regMC_VM_FB_LOCATION_TOP_BASE_IDX 0 7374#define regMC_VM_AGP_TOP 0x0982 7375#define regMC_VM_AGP_TOP_BASE_IDX 0 7376#define regMC_VM_AGP_BOT 0x0983 7377#define regMC_VM_AGP_BOT_BASE_IDX 0 7378#define regMC_VM_AGP_BASE 0x0984 7379#define regMC_VM_AGP_BASE_BASE_IDX 0 7380#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985 7381#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 7382#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986 7383#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 7384#define regMC_VM_MX_L1_TLB_CNTL 0x0987 7385#define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 7386 7387 7388// addressBlock: gccacind 7389// base address: 0x0 7390#define ixGC_CAC_CNTL 0x0000 7391#define ixGC_CAC_OVR_SEL 0x0001 7392#define ixGC_CAC_OVR_VAL 0x0002 7393#define ixGC_CAC_WEIGHT_BCI_0 0x0003 7394#define ixGC_CAC_WEIGHT_CB_0 0x0004 7395#define ixGC_CAC_WEIGHT_CB_1 0x0005 7396#define ixGC_CAC_WEIGHT_CP_0 0x0008 7397#define ixGC_CAC_WEIGHT_CP_1 0x0009 7398#define ixGC_CAC_WEIGHT_DB_0 0x000a 7399#define ixGC_CAC_WEIGHT_DB_1 0x000b 7400#define ixGC_CAC_WEIGHT_GDS_0 0x000e 7401#define ixGC_CAC_WEIGHT_GDS_1 0x000f 7402#define ixGC_CAC_WEIGHT_IA_0 0x0010 7403#define ixGC_CAC_WEIGHT_LDS_0 0x0011 7404#define ixGC_CAC_WEIGHT_LDS_1 0x0012 7405#define ixGC_CAC_WEIGHT_PA_0 0x0013 7406#define ixGC_CAC_WEIGHT_PC_0 0x0014 7407#define ixGC_CAC_WEIGHT_SC_0 0x0015 7408#define ixGC_CAC_WEIGHT_SPI_0 0x0016 7409#define ixGC_CAC_WEIGHT_SPI_1 0x0017 7410#define ixGC_CAC_WEIGHT_SPI_2 0x0018 7411#define ixGC_CAC_WEIGHT_SQ_0 0x001a 7412#define ixGC_CAC_WEIGHT_SQ_1 0x001b 7413#define ixGC_CAC_WEIGHT_SQ_2 0x001c 7414#define ixGC_CAC_WEIGHT_SQ_3 0x001d 7415#define ixGC_CAC_WEIGHT_SQ_4 0x001e 7416#define ixGC_CAC_WEIGHT_SX_0 0x001f 7417#define ixGC_CAC_WEIGHT_SXRB_0 0x0020 7418#define ixGC_CAC_WEIGHT_TA_0 0x0021 7419#define ixGC_CAC_WEIGHT_TCC_0 0x0022 7420#define ixGC_CAC_WEIGHT_TCC_1 0x0023 7421#define ixGC_CAC_WEIGHT_TCC_2 0x0024 7422#define ixGC_CAC_WEIGHT_TCP_0 0x0025 7423#define ixGC_CAC_WEIGHT_TCP_1 0x0026 7424#define ixGC_CAC_WEIGHT_TCP_2 0x0027 7425#define ixGC_CAC_WEIGHT_TD_0 0x0028 7426#define ixGC_CAC_WEIGHT_TD_1 0x0029 7427#define ixGC_CAC_WEIGHT_TD_2 0x002a 7428#define ixGC_CAC_WEIGHT_VGT_0 0x002b 7429#define ixGC_CAC_WEIGHT_VGT_1 0x002c 7430#define ixGC_CAC_WEIGHT_WD_0 0x002d 7431#define ixGC_CAC_WEIGHT_CU_0 0x0032 7432#define ixGC_CAC_ACC_BCI0 0x0042 7433#define ixGC_CAC_ACC_CB0 0x0043 7434#define ixGC_CAC_ACC_CB1 0x0044 7435#define ixGC_CAC_ACC_CB2 0x0045 7436#define ixGC_CAC_ACC_CB3 0x0046 7437#define ixGC_CAC_ACC_CP0 0x004b 7438#define ixGC_CAC_ACC_CP1 0x004c 7439#define ixGC_CAC_ACC_CP2 0x004d 7440#define ixGC_CAC_ACC_DB0 0x004e 7441#define ixGC_CAC_ACC_DB1 0x004f 7442#define ixGC_CAC_ACC_DB2 0x0050 7443#define ixGC_CAC_ACC_DB3 0x0051 7444#define ixGC_CAC_ACC_GDS0 0x0056 7445#define ixGC_CAC_ACC_GDS1 0x0057 7446#define ixGC_CAC_ACC_GDS2 0x0058 7447#define ixGC_CAC_ACC_GDS3 0x0059 7448#define ixGC_CAC_ACC_IA0 0x005a 7449#define ixGC_CAC_ACC_LDS0 0x005b 7450#define ixGC_CAC_ACC_LDS1 0x005c 7451#define ixGC_CAC_ACC_LDS2 0x005d 7452#define ixGC_CAC_ACC_LDS3 0x005e 7453#define ixGC_CAC_ACC_PA0 0x005f 7454#define ixGC_CAC_ACC_PA1 0x0060 7455#define ixGC_CAC_ACC_PC0 0x0061 7456#define ixGC_CAC_ACC_SC0 0x0062 7457#define ixGC_CAC_ACC_SPI0 0x0063 7458#define ixGC_CAC_ACC_SPI1 0x0064 7459#define ixGC_CAC_ACC_SPI2 0x0065 7460#define ixGC_CAC_ACC_SPI3 0x0066 7461#define ixGC_CAC_ACC_SPI4 0x0067 7462#define ixGC_CAC_ACC_SPI5 0x0068 7463#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x006f 7464#define ixGC_CAC_ACC_EA0 0x0070 7465#define ixGC_CAC_ACC_EA1 0x0071 7466#define ixGC_CAC_ACC_EA2 0x0072 7467#define ixGC_CAC_ACC_EA3 0x0073 7468#define ixGC_CAC_ACC_UTCL2_ATCL20 0x0074 7469#define ixGC_CAC_OVRD_EA 0x0075 7470#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0076 7471#define ixGC_CAC_WEIGHT_EA_0 0x0077 7472#define ixGC_CAC_WEIGHT_EA_1 0x0078 7473#define ixGC_CAC_WEIGHT_RMI_0 0x0079 7474#define ixGC_CAC_ACC_RMI0 0x007a 7475#define ixGC_CAC_OVRD_RMI 0x007b 7476#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x007c 7477#define ixGC_CAC_ACC_UTCL2_ATCL21 0x007d 7478#define ixGC_CAC_ACC_UTCL2_ATCL22 0x007e 7479#define ixGC_CAC_ACC_UTCL2_ATCL23 0x007f 7480#define ixGC_CAC_ACC_EA4 0x0080 7481#define ixGC_CAC_ACC_EA5 0x0081 7482#define ixGC_CAC_WEIGHT_EA_2 0x0082 7483#define ixGC_CAC_ACC_SQ0_LOWER 0x0089 7484#define ixGC_CAC_ACC_SQ0_UPPER 0x008a 7485#define ixGC_CAC_ACC_SQ1_LOWER 0x008b 7486#define ixGC_CAC_ACC_SQ1_UPPER 0x008c 7487#define ixGC_CAC_ACC_SQ2_LOWER 0x008d 7488#define ixGC_CAC_ACC_SQ2_UPPER 0x008e 7489#define ixGC_CAC_ACC_SQ3_LOWER 0x008f 7490#define ixGC_CAC_ACC_SQ3_UPPER 0x0090 7491#define ixGC_CAC_ACC_SQ4_LOWER 0x0091 7492#define ixGC_CAC_ACC_SQ4_UPPER 0x0092 7493#define ixGC_CAC_ACC_SQ5_LOWER 0x0093 7494#define ixGC_CAC_ACC_SQ5_UPPER 0x0094 7495#define ixGC_CAC_ACC_SQ6_LOWER 0x0095 7496#define ixGC_CAC_ACC_SQ6_UPPER 0x0096 7497#define ixGC_CAC_ACC_SQ7_LOWER 0x0097 7498#define ixGC_CAC_ACC_SQ7_UPPER 0x0098 7499#define ixGC_CAC_ACC_SQ8_LOWER 0x0099 7500#define ixGC_CAC_ACC_SQ8_UPPER 0x009a 7501#define ixGC_CAC_ACC_SX0 0x009b 7502#define ixGC_CAC_ACC_SXRB0 0x009c 7503#define ixGC_CAC_ACC_SXRB1 0x009d 7504#define ixGC_CAC_ACC_TA0 0x009e 7505#define ixGC_CAC_ACC_TCC0 0x009f 7506#define ixGC_CAC_ACC_TCC1 0x00a0 7507#define ixGC_CAC_ACC_TCC2 0x00a1 7508#define ixGC_CAC_ACC_TCC3 0x00a2 7509#define ixGC_CAC_ACC_TCC4 0x00a3 7510#define ixGC_CAC_ACC_TCP0 0x00a4 7511#define ixGC_CAC_ACC_TCP1 0x00a5 7512#define ixGC_CAC_ACC_TCP2 0x00a6 7513#define ixGC_CAC_ACC_TCP3 0x00a7 7514#define ixGC_CAC_ACC_TCP4 0x00a8 7515#define ixGC_CAC_ACC_TD0 0x00a9 7516#define ixGC_CAC_ACC_TD1 0x00aa 7517#define ixGC_CAC_ACC_TD2 0x00ab 7518#define ixGC_CAC_ACC_TD3 0x00ac 7519#define ixGC_CAC_ACC_TD4 0x00ad 7520#define ixGC_CAC_ACC_TD5 0x00ae 7521#define ixGC_CAC_ACC_VGT0 0x00af 7522#define ixGC_CAC_ACC_VGT1 0x00b0 7523#define ixGC_CAC_ACC_VGT2 0x00b1 7524#define ixGC_CAC_ACC_WD0 0x00b2 7525#define ixGC_CAC_ACC_CU0 0x00ba 7526#define ixGC_CAC_ACC_CU1 0x00bb 7527#define ixGC_CAC_ACC_CU2 0x00bc 7528#define ixGC_CAC_ACC_CU3 0x00bd 7529#define ixGC_CAC_ACC_CU4 0x00be 7530#define ixGC_CAC_ACC_CU5 0x00bf 7531#define ixGC_CAC_ACC_CU6 0x00c0 7532#define ixGC_CAC_ACC_CU7 0x00c1 7533#define ixGC_CAC_ACC_CU8 0x00c2 7534#define ixGC_CAC_ACC_CU9 0x00c3 7535#define ixGC_CAC_ACC_CU10 0x00c4 7536#define ixGC_CAC_ACC_CU11 0x00c5 7537#define ixGC_CAC_ACC_CU12 0x00c6 7538#define ixGC_CAC_ACC_CU13 0x00c7 7539#define ixGC_CAC_OVRD_BCI 0x00da 7540#define ixGC_CAC_OVRD_CB 0x00db 7541#define ixGC_CAC_OVRD_CP 0x00dd 7542#define ixGC_CAC_OVRD_DB 0x00de 7543#define ixGC_CAC_OVRD_GDS 0x00e0 7544#define ixGC_CAC_OVRD_IA 0x00e1 7545#define ixGC_CAC_OVRD_LDS 0x00e2 7546#define ixGC_CAC_OVRD_PA 0x00e3 7547#define ixGC_CAC_OVRD_PC 0x00e4 7548#define ixGC_CAC_OVRD_SC 0x00e5 7549#define ixGC_CAC_OVRD_SPI 0x00e6 7550#define ixGC_CAC_OVRD_CU 0x00e7 7551#define ixGC_CAC_OVRD_SQ 0x00e8 7552#define ixGC_CAC_OVRD_SX 0x00e9 7553#define ixGC_CAC_OVRD_SXRB 0x00ea 7554#define ixGC_CAC_OVRD_TA 0x00eb 7555#define ixGC_CAC_OVRD_TCC 0x00ec 7556#define ixGC_CAC_OVRD_TCP 0x00ed 7557#define ixGC_CAC_OVRD_TD 0x00ee 7558#define ixGC_CAC_OVRD_VGT 0x00ef 7559#define ixGC_CAC_OVRD_WD 0x00f0 7560#define ixGC_CAC_ACC_BCI1 0x00ff 7561#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x0100 7562#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x0101 7563#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x0102 7564#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0103 7565#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0104 7566#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0105 7567#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0106 7568#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0107 7569#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0108 7570#define ixGC_CAC_ACC_UTCL2_ATCL24 0x0109 7571#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x010a 7572#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x010b 7573#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x010c 7574#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x010d 7575#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x010e 7576#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x010f 7577#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x0110 7578#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0111 7579#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0112 7580#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0113 7581#define ixGC_CAC_ACC_UTCL2_VML20 0x0114 7582#define ixGC_CAC_ACC_UTCL2_VML21 0x0115 7583#define ixGC_CAC_ACC_UTCL2_VML22 0x0116 7584#define ixGC_CAC_ACC_UTCL2_VML23 0x0117 7585#define ixGC_CAC_ACC_UTCL2_VML24 0x0118 7586#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0119 7587#define ixGC_CAC_OVRD_UTCL2_VML2 0x011a 7588#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x011b 7589#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x011c 7590#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x011d 7591#define ixGC_CAC_ACC_UTCL2_WALKER0 0x011e 7592#define ixGC_CAC_ACC_UTCL2_WALKER1 0x011f 7593#define ixGC_CAC_ACC_UTCL2_WALKER2 0x0120 7594#define ixGC_CAC_ACC_UTCL2_WALKER3 0x0121 7595#define ixGC_CAC_ACC_UTCL2_WALKER4 0x0122 7596#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0123 7597#define ixEDC_STALL_PATTERN_1_2 0x0130 7598#define ixEDC_STALL_PATTERN_3_4 0x0131 7599#define ixEDC_STALL_PATTERN_5_6 0x0132 7600#define ixEDC_STALL_PATTERN_7 0x0133 7601#define ixPCC_STALL_PATTERN_1_2 0x0134 7602#define ixPCC_STALL_PATTERN_3_4 0x0135 7603#define ixPCC_STALL_PATTERN_5_6 0x0136 7604#define ixPCC_STALL_PATTERN_7 0x0137 7605#define ixPCC_THROT_REINCR_FIRST_PATN_1_8 0x0138 7606#define ixPCC_THROT_REINCR_FIRST_PATN_9_16 0x0139 7607#define ixPCC_THROT_REINCR_FIRST_PATN_17_20 0x0140 7608#define ixPCC_THROT_DECR_FIRST_PATN_1_4 0x0141 7609#define ixPCC_THROT_DECR_FIRST_PATN_5_7 0x0142 7610#define ixPWRBRK_STALL_PATTERN_CTRL 0x0143 7611#define ixPWRBRK_STALL_PATTERN_1_2 0x0144 7612#define ixPWRBRK_STALL_PATTERN_3_4 0x0145 7613#define ixPWRBRK_STALL_PATTERN_5_6 0x0146 7614#define ixPWRBRK_STALL_PATTERN_7 0x0147 7615#define ixPCC_PWRBRK_HYSTERESIS_CTRL 0x0148 7616#define ixFIXED_PATTERN_PERF_COUNTER_CTRL 0x015f 7617#define ixFIXED_PATTERN_PERF_COUNTER_1 0x0160 7618#define ixFIXED_PATTERN_PERF_COUNTER_2 0x0161 7619#define ixFIXED_PATTERN_PERF_COUNTER_3 0x0162 7620#define ixFIXED_PATTERN_PERF_COUNTER_4 0x0163 7621#define ixFIXED_PATTERN_PERF_COUNTER_5 0x0164 7622#define ixFIXED_PATTERN_PERF_COUNTER_6 0x0165 7623#define ixFIXED_PATTERN_PERF_COUNTER_7 0x0166 7624#define ixFIXED_PATTERN_PERF_COUNTER_8 0x0167 7625#define ixFIXED_PATTERN_PERF_COUNTER_9 0x0168 7626#define ixFIXED_PATTERN_PERF_COUNTER_10 0x0169 7627 7628 7629// addressBlock: secacind 7630// base address: 0x0 7631#define ixSE_CAC_CNTL 0x0000 7632#define ixSE_CAC_OVR_SEL 0x0001 7633#define ixSE_CAC_OVR_VAL 0x0002 7634 7635 7636// addressBlock: sqind 7637// base address: 0x0 7638#define ixSQ_DEBUG_STS_LOCAL 0x0008 7639#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 7640#define ixSQ_WAVE_VALID_AND_IDLE 0x000a 7641#define ixSQ_WAVE_MODE 0x0011 7642#define ixSQ_WAVE_STATUS 0x0012 7643#define ixSQ_WAVE_TRAPSTS 0x0013 7644#define ixSQ_WAVE_HW_ID 0x0014 7645#define ixSQ_WAVE_GPR_ALLOC 0x0015 7646#define ixSQ_WAVE_LDS_ALLOC 0x0016 7647#define ixSQ_WAVE_IB_STS 0x0017 7648#define ixSQ_WAVE_PC_LO 0x0018 7649#define ixSQ_WAVE_PC_HI 0x0019 7650#define ixSQ_WAVE_INST_DW0 0x001a 7651#define ixSQ_WAVE_INST_DW1 0x001b 7652#define ixSQ_WAVE_IB_DBG0 0x001c 7653#define ixSQ_WAVE_IB_DBG1 0x001d 7654#define ixSQ_WAVE_FLUSH_IB 0x001e 7655#define ixSQ_WAVE_TTMP0 0x026c 7656#define ixSQ_WAVE_TTMP1 0x026d 7657#define ixSQ_WAVE_TTMP3 0x026f 7658#define ixSQ_WAVE_TTMP4 0x0270 7659#define ixSQ_WAVE_TTMP5 0x0271 7660#define ixSQ_WAVE_TTMP6 0x0272 7661#define ixSQ_WAVE_TTMP7 0x0273 7662#define ixSQ_WAVE_TTMP8 0x0274 7663#define ixSQ_WAVE_TTMP9 0x0275 7664#define ixSQ_WAVE_TTMP10 0x0276 7665#define ixSQ_WAVE_TTMP11 0x0277 7666#define ixSQ_WAVE_TTMP12 0x0278 7667#define ixSQ_WAVE_TTMP13 0x0279 7668#define ixSQ_WAVE_TTMP14 0x027a 7669#define ixSQ_WAVE_TTMP15 0x027b 7670#define ixSQ_WAVE_M0 0x027c 7671#define ixSQ_WAVE_EXEC_LO 0x027e 7672#define ixSQ_WAVE_EXEC_HI 0x027f 7673#define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0 7674#define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0 7675#define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0 7676#define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0 7677#define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0 7678#define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0 7679#define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0 7680#define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0 7681 7682 7683#endif 7684