LXR linux/drivers/gpu/drm/i915/display/g4x

   1// SPDX-License-Identifier: MIT
   2/*
   3 * Copyright © 2020 Intel Corporation
   4 *
   5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
   6 */
   7
   8#include "g4x_hdmi.h"
   9#include "intel_audio.h"
  10#include "intel_connector.h"
  11#include "intel_display_types.h"
  12#include "intel_dpio_phy.h"
  13#include "intel_fifo_underrun.h"
  14#include "intel_hdmi.h"
  15#include "intel_hotplug.h"
  16#include "intel_sideband.h"
  17#include "intel_sdvo.h"
  18
  19static void intel_hdmi_prepare(struct intel_encoder *encoder,
  20                               const struct intel_crtc_state *crtc_state)
  21{
  22        struct drm_device *dev = encoder->base.dev;
  23        struct drm_i915_private *dev_priv = to_i915(dev);
  24        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
  25        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  26        const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
  27        u32 hdmi_val;
  28
  29        intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
  30
  31        hdmi_val = SDVO_ENCODING_HDMI;
  32        if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
  33                hdmi_val |= HDMI_COLOR_RANGE_16_235;
  34        if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  35                hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
  36        if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  37                hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
  38
  39        if (crtc_state->pipe_bpp > 24)
  40                hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
  41        else
  42                hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
  43
  44        if (crtc_state->has_hdmi_sink)
  45                hdmi_val |= HDMI_MODE_SELECT_HDMI;
  46
  47        if (HAS_PCH_CPT(dev_priv))
  48                hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
  49        else if (IS_CHERRYVIEW(dev_priv))
  50                hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
  51        else
  52                hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
  53
  54        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
  55        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
  56}
  57
  58static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
  59                                    enum pipe *pipe)
  60{
  61        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  62        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  63        intel_wakeref_t wakeref;
  64        bool ret;
  65
  66        wakeref = intel_display_power_get_if_enabled(dev_priv,
  67                                                     encoder->power_domain);
  68        if (!wakeref)
  69                return false;
  70
  71        ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
  72
  73        intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
  74
  75        return ret;
  76}
  77
  78static void intel_hdmi_get_config(struct intel_encoder *encoder,
  79                                  struct intel_crtc_state *pipe_config)
  80{
  81        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  82        struct drm_device *dev = encoder->base.dev;
  83        struct drm_i915_private *dev_priv = to_i915(dev);
  84        u32 tmp, flags = 0;
  85        int dotclock;
  86
  87        pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
  88
  89        tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
  90
  91        if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
  92                flags |= DRM_MODE_FLAG_PHSYNC;
  93        else
  94                flags |= DRM_MODE_FLAG_NHSYNC;
  95
  96        if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
  97                flags |= DRM_MODE_FLAG_PVSYNC;
  98        else
  99                flags |= DRM_MODE_FLAG_NVSYNC;
 100
 101        if (tmp & HDMI_MODE_SELECT_HDMI)
 102                pipe_config->has_hdmi_sink = true;
 103
 104        pipe_config->infoframes.enable |=
 105                intel_hdmi_infoframes_enabled(encoder, pipe_config);
 106
 107        if (pipe_config->infoframes.enable)
 108                pipe_config->has_infoframe = true;
 109
 110        if (tmp & HDMI_AUDIO_ENABLE)
 111                pipe_config->has_audio = true;
 112
 113        if (!HAS_PCH_SPLIT(dev_priv) &&
 114            tmp & HDMI_COLOR_RANGE_16_235)
 115                pipe_config->limited_color_range = true;
 116
 117        pipe_config->hw.adjusted_mode.flags |= flags;
 118
 119        if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 120                dotclock = pipe_config->port_clock * 2 / 3;
 121        else
 122                dotclock = pipe_config->port_clock;
 123
 124        if (pipe_config->pixel_multiplier)
 125                dotclock /= pipe_config->pixel_multiplier;
 126
 127        pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 128
 129        pipe_config->lane_count = 4;
 130
 131        intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
 132
 133        intel_read_infoframe(encoder, pipe_config,
 134                             HDMI_INFOFRAME_TYPE_AVI,
 135                             &pipe_config->infoframes.avi);
 136        intel_read_infoframe(encoder, pipe_config,
 137                             HDMI_INFOFRAME_TYPE_SPD,
 138                             &pipe_config->infoframes.spd);
 139        intel_read_infoframe(encoder, pipe_config,
 140                             HDMI_INFOFRAME_TYPE_VENDOR,
 141                             &pipe_config->infoframes.hdmi);
 142}
 143
 144static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
 145                                    const struct intel_crtc_state *pipe_config,
 146                                    const struct drm_connector_state *conn_state)
 147{
 148        struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 149        struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 150
 151        drm_WARN_ON(&i915->drm, !pipe_config->has_hdmi_sink);
 152        drm_dbg_kms(&i915->drm, "Enabling HDMI audio on pipe %c\n",
 153                    pipe_name(crtc->pipe));
 154        intel_audio_codec_enable(encoder, pipe_config, conn_state);
 155}
 156
 157static void g4x_enable_hdmi(struct intel_atomic_state *state,
 158                            struct intel_encoder *encoder,
 159                            const struct intel_crtc_state *pipe_config,
 160                            const struct drm_connector_state *conn_state)
 161{
 162        struct drm_device *dev = encoder->base.dev;
 163        struct drm_i915_private *dev_priv = to_i915(dev);
 164        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 165        u32 temp;
 166
 167        temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 168
 169        temp |= SDVO_ENABLE;
 170        if (pipe_config->has_audio)
 171                temp |= HDMI_AUDIO_ENABLE;
 172
 173        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 174        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 175
 176        if (pipe_config->has_audio)
 177                intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
 178}
 179
 180static void ibx_enable_hdmi(struct intel_atomic_state *state,
 181                            struct intel_encoder *encoder,
 182                            const struct intel_crtc_state *pipe_config,
 183                            const struct drm_connector_state *conn_state)
 184{
 185        struct drm_device *dev = encoder->base.dev;
 186        struct drm_i915_private *dev_priv = to_i915(dev);
 187        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 188        u32 temp;
 189
 190        temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 191
 192        temp |= SDVO_ENABLE;
 193        if (pipe_config->has_audio)
 194                temp |= HDMI_AUDIO_ENABLE;
 195
 196        /*
 197         * HW workaround, need to write this twice for issue
 198         * that may result in first write getting masked.
 199         */
 200        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 201        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 202        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 203        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 204
 205        /*
 206         * HW workaround, need to toggle enable bit off and on
 207         * for 12bpc with pixel repeat.
 208         *
 209         * FIXME: BSpec says this should be done at the end of
 210         * the modeset sequence, so not sure if this isn't too soon.
 211         */
 212        if (pipe_config->pipe_bpp > 24 &&
 213            pipe_config->pixel_multiplier > 1) {
 214                intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
 215                               temp & ~SDVO_ENABLE);
 216                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 217
 218                /*
 219                 * HW workaround, need to write this twice for issue
 220                 * that may result in first write getting masked.
 221                 */
 222                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 223                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 224                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 225                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 226        }
 227
 228        if (pipe_config->has_audio)
 229                intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
 230}
 231
 232static void cpt_enable_hdmi(struct intel_atomic_state *state,
 233                            struct intel_encoder *encoder,
 234                            const struct intel_crtc_state *pipe_config,
 235                            const struct drm_connector_state *conn_state)
 236{
 237        struct drm_device *dev = encoder->base.dev;
 238        struct drm_i915_private *dev_priv = to_i915(dev);
 239        struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 240        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 241        enum pipe pipe = crtc->pipe;
 242        u32 temp;
 243
 244        temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 245
 246        temp |= SDVO_ENABLE;
 247        if (pipe_config->has_audio)
 248                temp |= HDMI_AUDIO_ENABLE;
 249
 250        /*
 251         * WaEnableHDMI8bpcBefore12bpc:snb,ivb
 252         *
 253         * The procedure for 12bpc is as follows:
 254         * 1. disable HDMI clock gating
 255         * 2. enable HDMI with 8bpc
 256         * 3. enable HDMI with 12bpc
 257         * 4. enable HDMI clock gating
 258         */
 259
 260        if (pipe_config->pipe_bpp > 24) {
 261                intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
 262                               intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
 263
 264                temp &= ~SDVO_COLOR_FORMAT_MASK;
 265                temp |= SDVO_COLOR_FORMAT_8bpc;
 266        }
 267
 268        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 269        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 270
 271        if (pipe_config->pipe_bpp > 24) {
 272                temp &= ~SDVO_COLOR_FORMAT_MASK;
 273                temp |= HDMI_COLOR_FORMAT_12bpc;
 274
 275                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 276                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 277
 278                intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
 279                               intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
 280        }
 281
 282        if (pipe_config->has_audio)
 283                intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
 284}
 285
 286static void vlv_enable_hdmi(struct intel_atomic_state *state,
 287                            struct intel_encoder *encoder,
 288                            const struct intel_crtc_state *pipe_config,
 289                            const struct drm_connector_state *conn_state)
 290{
 291}
 292
 293static void intel_disable_hdmi(struct intel_atomic_state *state,
 294                               struct intel_encoder *encoder,
 295                               const struct intel_crtc_state *old_crtc_state,
 296                               const struct drm_connector_state *old_conn_state)
 297{
 298        struct drm_device *dev = encoder->base.dev;
 299        struct drm_i915_private *dev_priv = to_i915(dev);
 300        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 301        struct intel_digital_port *dig_port =
 302                hdmi_to_dig_port(intel_hdmi);
 303        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 304        u32 temp;
 305
 306        temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 307
 308        temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
 309        intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 310        intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 311
 312        /*
 313         * HW workaround for IBX, we need to move the port
 314         * to transcoder A after disabling it to allow the
 315         * matching DP port to be enabled on transcoder A.
 316         */
 317        if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
 318                /*
 319                 * We get CPU/PCH FIFO underruns on the other pipe when
 320                 * doing the workaround. Sweep them under the rug.
 321                 */
 322                intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 323                intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 324
 325                temp &= ~SDVO_PIPE_SEL_MASK;
 326                temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
 327                /*
 328                 * HW workaround, need to write this twice for issue
 329                 * that may result in first write getting masked.
 330                 */
 331                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 332                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 333                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 334                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 335
 336                temp &= ~SDVO_ENABLE;
 337                intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 338                intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 339
 340                intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
 341                intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 342                intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 343        }
 344
 345        dig_port->set_infoframes(encoder,
 346                                       false,
 347                                       old_crtc_state, old_conn_state);
 348
 349        intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
 350}
 351
 352static void g4x_disable_hdmi(struct intel_atomic_state *state,
 353                             struct intel_encoder *encoder,
 354                             const struct intel_crtc_state *old_crtc_state,
 355                             const struct drm_connector_state *old_conn_state)
 356{
 357        if (old_crtc_state->has_audio)
 358                intel_audio_codec_disable(encoder,
 359                                          old_crtc_state, old_conn_state);
 360
 361        intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
 362}
 363
 364static void pch_disable_hdmi(struct intel_atomic_state *state,
 365                             struct intel_encoder *encoder,
 366                             const struct intel_crtc_state *old_crtc_state,
 367                             const struct drm_connector_state *old_conn_state)
 368{
 369        if (old_crtc_state->has_audio)
 370                intel_audio_codec_disable(encoder,
 371                                          old_crtc_state, old_conn_state);
 372}
 373
 374static void pch_post_disable_hdmi(struct intel_atomic_state *state,
 375                                  struct intel_encoder *encoder,
 376                                  const struct intel_crtc_state *old_crtc_state,
 377                                  const struct drm_connector_state *old_conn_state)
 378{
 379        intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
 380}
 381
 382static void intel_hdmi_pre_enable(struct intel_atomic_state *state,
 383                                  struct intel_encoder *encoder,
 384                                  const struct intel_crtc_state *pipe_config,
 385                                  const struct drm_connector_state *conn_state)
 386{
 387        struct intel_digital_port *dig_port =
 388                enc_to_dig_port(encoder);
 389
 390        intel_hdmi_prepare(encoder, pipe_config);
 391
 392        dig_port->set_infoframes(encoder,
 393                                       pipe_config->has_infoframe,
 394                                       pipe_config, conn_state);
 395}
 396
 397static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
 398                                struct intel_encoder *encoder,
 399                                const struct intel_crtc_state *pipe_config,
 400                                const struct drm_connector_state *conn_state)
 401{
 402        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 403        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 404
 405        vlv_phy_pre_encoder_enable(encoder, pipe_config);
 406
 407        /* HDMI 1.0V-2dB */
 408        vlv_set_phy_signal_level(encoder, pipe_config,
 409                                 0x2b245f5f, 0x00002000,
 410                                 0x5578b83a, 0x2b247878);
 411
 412        dig_port->set_infoframes(encoder,
 413                              pipe_config->has_infoframe,
 414                              pipe_config, conn_state);
 415
 416        g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
 417
 418        vlv_wait_port_ready(dev_priv, dig_port, 0x0);
 419}
 420
 421static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
 422                                    struct intel_encoder *encoder,
 423                                    const struct intel_crtc_state *pipe_config,
 424                                    const struct drm_connector_state *conn_state)
 425{
 426        intel_hdmi_prepare(encoder, pipe_config);
 427
 428        vlv_phy_pre_pll_enable(encoder, pipe_config);
 429}
 430
 431static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
 432                                    struct intel_encoder *encoder,
 433                                    const struct intel_crtc_state *pipe_config,
 434                                    const struct drm_connector_state *conn_state)
 435{
 436        intel_hdmi_prepare(encoder, pipe_config);
 437
 438        chv_phy_pre_pll_enable(encoder, pipe_config);
 439}
 440
 441static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state,
 442                                      struct intel_encoder *encoder,
 443                                      const struct intel_crtc_state *old_crtc_state,
 444                                      const struct drm_connector_state *old_conn_state)
 445{
 446        chv_phy_post_pll_disable(encoder, old_crtc_state);
 447}
 448
 449static void vlv_hdmi_post_disable(struct intel_atomic_state *state,
 450                                  struct intel_encoder *encoder,
 451                                  const struct intel_crtc_state *old_crtc_state,
 452                                  const struct drm_connector_state *old_conn_state)
 453{
 454        /* Reset lanes to avoid HDMI flicker (VLV w/a) */
 455        vlv_phy_reset_lanes(encoder, old_crtc_state);
 456}
 457
 458static void chv_hdmi_post_disable(struct intel_atomic_state *state,
 459                                  struct intel_encoder *encoder,
 460                                  const struct intel_crtc_state *old_crtc_state,
 461                                  const struct drm_connector_state *old_conn_state)
 462{
 463        struct drm_device *dev = encoder->base.dev;
 464        struct drm_i915_private *dev_priv = to_i915(dev);
 465
 466        vlv_dpio_get(dev_priv);
 467
 468        /* Assert data lane reset */
 469        chv_data_lane_soft_reset(encoder, old_crtc_state, true);
 470
 471        vlv_dpio_put(dev_priv);
 472}
 473
 474static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
 475                                struct intel_encoder *encoder,
 476                                const struct intel_crtc_state *pipe_config,
 477                                const struct drm_connector_state *conn_state)
 478{
 479        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 480        struct drm_device *dev = encoder->base.dev;
 481        struct drm_i915_private *dev_priv = to_i915(dev);
 482
 483        chv_phy_pre_encoder_enable(encoder, pipe_config);
 484
 485        /* FIXME: Program the support xxx V-dB */
 486        /* Use 800mV-0dB */
 487        chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
 488
 489        dig_port->set_infoframes(encoder,
 490                              pipe_config->has_infoframe,
 491                              pipe_config, conn_state);
 492
 493        g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
 494
 495        vlv_wait_port_ready(dev_priv, dig_port, 0x0);
 496
 497        /* Second common lane will stay alive on its own now */
 498        chv_phy_release_cl2_override(encoder);
 499}
 500
 501static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 502        .destroy = intel_encoder_destroy,
 503};
 504
 505static enum intel_hotplug_state
 506intel_hdmi_hotplug(struct intel_encoder *encoder,
 507                   struct intel_connector *connector)
 508{
 509        enum intel_hotplug_state state;
 510
 511        state = intel_encoder_hotplug(encoder, connector);
 512
 513        /*
 514         * On many platforms the HDMI live state signal is known to be
 515         * unreliable, so we can't use it to detect if a sink is connected or
 516         * not. Instead we detect if it's connected based on whether we can
 517         * read the EDID or not. That in turn has a problem during disconnect,
 518         * since the HPD interrupt may be raised before the DDC lines get
 519         * disconnected (due to how the required length of DDC vs. HPD
 520         * connector pins are specified) and so we'll still be able to get a
 521         * valid EDID. To solve this schedule another detection cycle if this
 522         * time around we didn't detect any change in the sink's connection
 523         * status.
 524         */
 525        if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
 526                state = INTEL_HOTPLUG_RETRY;
 527
 528        return state;
 529}
 530
 531void g4x_hdmi_init(struct drm_i915_private *dev_priv,
 532                   i915_reg_t hdmi_reg, enum port port)
 533{
 534        struct intel_digital_port *dig_port;
 535        struct intel_encoder *intel_encoder;
 536        struct intel_connector *intel_connector;
 537
 538        dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
 539        if (!dig_port)
 540                return;
 541
 542        intel_connector = intel_connector_alloc();
 543        if (!intel_connector) {
 544                kfree(dig_port);
 545                return;
 546        }
 547
 548        intel_encoder = &dig_port->base;
 549
 550        mutex_init(&dig_port->hdcp_mutex);
 551
 552        drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
 553                         &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
 554                         "HDMI %c", port_name(port));
 555
 556        intel_encoder->hotplug = intel_hdmi_hotplug;
 557        intel_encoder->compute_config = intel_hdmi_compute_config;
 558        if (HAS_PCH_SPLIT(dev_priv)) {
 559                intel_encoder->disable = pch_disable_hdmi;
 560                intel_encoder->post_disable = pch_post_disable_hdmi;
 561        } else {
 562                intel_encoder->disable = g4x_disable_hdmi;
 563        }
 564        intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
 565        intel_encoder->get_config = intel_hdmi_get_config;
 566        if (IS_CHERRYVIEW(dev_priv)) {
 567                intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
 568                intel_encoder->pre_enable = chv_hdmi_pre_enable;
 569                intel_encoder->enable = vlv_enable_hdmi;
 570                intel_encoder->post_disable = chv_hdmi_post_disable;
 571                intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
 572        } else if (IS_VALLEYVIEW(dev_priv)) {
 573                intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
 574                intel_encoder->pre_enable = vlv_hdmi_pre_enable;
 575                intel_encoder->enable = vlv_enable_hdmi;
 576                intel_encoder->post_disable = vlv_hdmi_post_disable;
 577        } else {
 578                intel_encoder->pre_enable = intel_hdmi_pre_enable;
 579                if (HAS_PCH_CPT(dev_priv))
 580                        intel_encoder->enable = cpt_enable_hdmi;
 581                else if (HAS_PCH_IBX(dev_priv))
 582                        intel_encoder->enable = ibx_enable_hdmi;
 583                else
 584                        intel_encoder->enable = g4x_enable_hdmi;
 585        }
 586
 587        intel_encoder->type = INTEL_OUTPUT_HDMI;
 588        intel_encoder->power_domain = intel_port_to_power_domain(port);
 589        intel_encoder->port = port;
 590        if (IS_CHERRYVIEW(dev_priv)) {
 591                if (port == PORT_D)
 592                        intel_encoder->pipe_mask = BIT(PIPE_C);
 593                else
 594                        intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
 595        } else {
 596                intel_encoder->pipe_mask = ~0;
 597        }
 598        intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
 599        intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
 600        /*
 601         * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
 602         * to work on real hardware. And since g4x can send infoframes to
 603         * only one port anyway, nothing is lost by allowing it.
 604         */
 605        if (IS_G4X(dev_priv))
 606                intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
 607
 608        dig_port->hdmi.hdmi_reg = hdmi_reg;
 609        dig_port->dp.output_reg = INVALID_MMIO_REG;
 610        dig_port->max_lanes = 4;
 611
 612        intel_infoframe_init(dig_port);
 613
 614        dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
 615        intel_hdmi_init_connector(dig_port, intel_connector);
 616}
 617