LXR linux/drivers/gpu/host1x/hw/host1x01

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Tegra host1x Register Offsets for Tegra20 and Tegra30
   4 *
   5 * Copyright (c) 2010-2013 NVIDIA Corporation.
   6 */
   7
   8#ifndef __HOST1X_HOST1X01_HARDWARE_H
   9#define __HOST1X_HOST1X01_HARDWARE_H
  10
  11#include <linux/types.h>
  12#include <linux/bitops.h>
  13
  14#include "hw_host1x01_channel.h"
  15#include "hw_host1x01_sync.h"
  16#include "hw_host1x01_uclass.h"
  17
  18static inline u32 host1x_class_host_wait_syncpt(
  19        unsigned indx, unsigned threshold)
  20{
  21        return host1x_uclass_wait_syncpt_indx_f(indx)
  22                | host1x_uclass_wait_syncpt_thresh_f(threshold);
  23}
  24
  25static inline u32 host1x_class_host_load_syncpt_base(
  26        unsigned indx, unsigned threshold)
  27{
  28        return host1x_uclass_load_syncpt_base_base_indx_f(indx)
  29                | host1x_uclass_load_syncpt_base_value_f(threshold);
  30}
  31
  32static inline u32 host1x_class_host_wait_syncpt_base(
  33        unsigned indx, unsigned base_indx, unsigned offset)
  34{
  35        return host1x_uclass_wait_syncpt_base_indx_f(indx)
  36                | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
  37                | host1x_uclass_wait_syncpt_base_offset_f(offset);
  38}
  39
  40static inline u32 host1x_class_host_incr_syncpt_base(
  41        unsigned base_indx, unsigned offset)
  42{
  43        return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
  44                | host1x_uclass_incr_syncpt_base_offset_f(offset);
  45}
  46
  47static inline u32 host1x_class_host_incr_syncpt(
  48        unsigned cond, unsigned indx)
  49{
  50        return host1x_uclass_incr_syncpt_cond_f(cond)
  51                | host1x_uclass_incr_syncpt_indx_f(indx);
  52}
  53
  54static inline u32 host1x_class_host_indoff_reg_write(
  55        unsigned mod_id, unsigned offset, bool auto_inc)
  56{
  57        u32 v = host1x_uclass_indoff_indbe_f(0xf)
  58                | host1x_uclass_indoff_indmodid_f(mod_id)
  59                | host1x_uclass_indoff_indroffset_f(offset);
  60        if (auto_inc)
  61                v |= host1x_uclass_indoff_autoinc_f(1);
  62        return v;
  63}
  64
  65static inline u32 host1x_class_host_indoff_reg_read(
  66        unsigned mod_id, unsigned offset, bool auto_inc)
  67{
  68        u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
  69                | host1x_uclass_indoff_indroffset_f(offset)
  70                | host1x_uclass_indoff_rwn_read_v();
  71        if (auto_inc)
  72                v |= host1x_uclass_indoff_autoinc_f(1);
  73        return v;
  74}
  75
  76
  77/* cdma opcodes */
  78static inline u32 host1x_opcode_setclass(
  79        unsigned class_id, unsigned offset, unsigned mask)
  80{
  81        return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
  82}
  83
  84static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
  85{
  86        return (1 << 28) | (offset << 16) | count;
  87}
  88
  89static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
  90{
  91        return (2 << 28) | (offset << 16) | count;
  92}
  93
  94static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
  95{
  96        return (3 << 28) | (offset << 16) | mask;
  97}
  98
  99static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
 100{
 101        return (4 << 28) | (offset << 16) | value;
 102}
 103
 104static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
 105{
 106        return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
 107                host1x_class_host_incr_syncpt(cond, indx));
 108}
 109
 110static inline u32 host1x_opcode_restart(unsigned address)
 111{
 112        return (5 << 28) | (address >> 4);
 113}
 114
 115static inline u32 host1x_opcode_gather(unsigned count)
 116{
 117        return (6 << 28) | count;
 118}
 119
 120static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
 121{
 122        return (6 << 28) | (offset << 16) | BIT(15) | count;
 123}
 124
 125static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 126{
 127        return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 128}
 129
 130#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
 131
 132#endif
 133