1
2
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4
5
6#include <linux/module.h>
7#include <linux/slab.h>
8#include <linux/i2c.h>
9#include <linux/err.h>
10#include <linux/delay.h>
11#include <linux/sysfs.h>
12#include <linux/jiffies.h>
13#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/iio/iio.h>
16#include <linux/acpi.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/consumer.h>
19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include "inv_mpu_iio.h"
22#include "inv_mpu_magn.h"
23
24
25
26
27
28static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
29
30
31
32
33
34static const int accel_scale[] = {598, 1196, 2392, 4785};
35
36static const struct inv_mpu6050_reg_map reg_set_icm20602 = {
37 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
38 .lpf = INV_MPU6050_REG_CONFIG,
39 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
40 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
41 .fifo_en = INV_MPU6050_REG_FIFO_EN,
42 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
43 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
44 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
45 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
46 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
47 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
48 .temperature = INV_MPU6050_REG_TEMPERATURE,
49 .int_enable = INV_MPU6050_REG_INT_ENABLE,
50 .int_status = INV_MPU6050_REG_INT_STATUS,
51 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
52 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
53 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
54 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
55 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
56 .i2c_if = INV_ICM20602_REG_I2C_IF,
57};
58
59static const struct inv_mpu6050_reg_map reg_set_6500 = {
60 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
61 .lpf = INV_MPU6050_REG_CONFIG,
62 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
63 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
64 .fifo_en = INV_MPU6050_REG_FIFO_EN,
65 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
66 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
67 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
68 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
69 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
70 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
71 .temperature = INV_MPU6050_REG_TEMPERATURE,
72 .int_enable = INV_MPU6050_REG_INT_ENABLE,
73 .int_status = INV_MPU6050_REG_INT_STATUS,
74 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
75 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
76 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
77 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
78 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
79 .i2c_if = 0,
80};
81
82static const struct inv_mpu6050_reg_map reg_set_6050 = {
83 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
84 .lpf = INV_MPU6050_REG_CONFIG,
85 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
86 .fifo_en = INV_MPU6050_REG_FIFO_EN,
87 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
88 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
89 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
90 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
91 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
92 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
93 .temperature = INV_MPU6050_REG_TEMPERATURE,
94 .int_enable = INV_MPU6050_REG_INT_ENABLE,
95 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
96 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
97 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
98 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
99 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
100 .i2c_if = 0,
101};
102
103static const struct inv_mpu6050_chip_config chip_config_6050 = {
104 .clk = INV_CLK_INTERNAL,
105 .fsr = INV_MPU6050_FSR_2000DPS,
106 .lpf = INV_MPU6050_FILTER_20HZ,
107 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
108 .gyro_en = true,
109 .accl_en = true,
110 .temp_en = true,
111 .magn_en = false,
112 .gyro_fifo_enable = false,
113 .accl_fifo_enable = false,
114 .temp_fifo_enable = false,
115 .magn_fifo_enable = false,
116 .accl_fs = INV_MPU6050_FS_02G,
117 .user_ctrl = 0,
118};
119
120static const struct inv_mpu6050_chip_config chip_config_6500 = {
121 .clk = INV_CLK_PLL,
122 .fsr = INV_MPU6050_FSR_2000DPS,
123 .lpf = INV_MPU6050_FILTER_20HZ,
124 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
125 .gyro_en = true,
126 .accl_en = true,
127 .temp_en = true,
128 .magn_en = false,
129 .gyro_fifo_enable = false,
130 .accl_fifo_enable = false,
131 .temp_fifo_enable = false,
132 .magn_fifo_enable = false,
133 .accl_fs = INV_MPU6050_FS_02G,
134 .user_ctrl = 0,
135};
136
137
138static const struct inv_mpu6050_hw hw_info[] = {
139 {
140 .whoami = INV_MPU6050_WHOAMI_VALUE,
141 .name = "MPU6050",
142 .reg = ®_set_6050,
143 .config = &chip_config_6050,
144 .fifo_size = 1024,
145 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
146 },
147 {
148 .whoami = INV_MPU6500_WHOAMI_VALUE,
149 .name = "MPU6500",
150 .reg = ®_set_6500,
151 .config = &chip_config_6500,
152 .fifo_size = 512,
153 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
154 },
155 {
156 .whoami = INV_MPU6515_WHOAMI_VALUE,
157 .name = "MPU6515",
158 .reg = ®_set_6500,
159 .config = &chip_config_6500,
160 .fifo_size = 512,
161 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
162 },
163 {
164 .whoami = INV_MPU6880_WHOAMI_VALUE,
165 .name = "MPU6880",
166 .reg = ®_set_6500,
167 .config = &chip_config_6500,
168 .fifo_size = 4096,
169 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
170 },
171 {
172 .whoami = INV_MPU6000_WHOAMI_VALUE,
173 .name = "MPU6000",
174 .reg = ®_set_6050,
175 .config = &chip_config_6050,
176 .fifo_size = 1024,
177 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
178 },
179 {
180 .whoami = INV_MPU9150_WHOAMI_VALUE,
181 .name = "MPU9150",
182 .reg = ®_set_6050,
183 .config = &chip_config_6050,
184 .fifo_size = 1024,
185 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
186 },
187 {
188 .whoami = INV_MPU9250_WHOAMI_VALUE,
189 .name = "MPU9250",
190 .reg = ®_set_6500,
191 .config = &chip_config_6500,
192 .fifo_size = 512,
193 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
194 },
195 {
196 .whoami = INV_MPU9255_WHOAMI_VALUE,
197 .name = "MPU9255",
198 .reg = ®_set_6500,
199 .config = &chip_config_6500,
200 .fifo_size = 512,
201 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
202 },
203 {
204 .whoami = INV_ICM20608_WHOAMI_VALUE,
205 .name = "ICM20608",
206 .reg = ®_set_6500,
207 .config = &chip_config_6500,
208 .fifo_size = 512,
209 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
210 },
211 {
212 .whoami = INV_ICM20609_WHOAMI_VALUE,
213 .name = "ICM20609",
214 .reg = ®_set_6500,
215 .config = &chip_config_6500,
216 .fifo_size = 4 * 1024,
217 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
218 },
219 {
220 .whoami = INV_ICM20689_WHOAMI_VALUE,
221 .name = "ICM20689",
222 .reg = ®_set_6500,
223 .config = &chip_config_6500,
224 .fifo_size = 4 * 1024,
225 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
226 },
227 {
228 .whoami = INV_ICM20602_WHOAMI_VALUE,
229 .name = "ICM20602",
230 .reg = ®_set_icm20602,
231 .config = &chip_config_6500,
232 .fifo_size = 1008,
233 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
234 },
235 {
236 .whoami = INV_ICM20690_WHOAMI_VALUE,
237 .name = "ICM20690",
238 .reg = ®_set_6500,
239 .config = &chip_config_6500,
240 .fifo_size = 1024,
241 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
242 },
243 {
244 .whoami = INV_IAM20680_WHOAMI_VALUE,
245 .name = "IAM20680",
246 .reg = ®_set_6500,
247 .config = &chip_config_6500,
248 .fifo_size = 512,
249 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
250 },
251};
252
253static int inv_mpu6050_pwr_mgmt_1_write(struct inv_mpu6050_state *st, bool sleep,
254 int clock, int temp_dis)
255{
256 u8 val;
257
258 if (clock < 0)
259 clock = st->chip_config.clk;
260 if (temp_dis < 0)
261 temp_dis = !st->chip_config.temp_en;
262
263 val = clock & INV_MPU6050_BIT_CLK_MASK;
264 if (temp_dis)
265 val |= INV_MPU6050_BIT_TEMP_DIS;
266 if (sleep)
267 val |= INV_MPU6050_BIT_SLEEP;
268
269 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_1: 0x%x\n", val);
270 return regmap_write(st->map, st->reg->pwr_mgmt_1, val);
271}
272
273static int inv_mpu6050_clock_switch(struct inv_mpu6050_state *st,
274 unsigned int clock)
275{
276 int ret;
277
278 switch (st->chip_type) {
279 case INV_MPU6050:
280 case INV_MPU6000:
281 case INV_MPU9150:
282
283 ret = inv_mpu6050_pwr_mgmt_1_write(st, false, clock, -1);
284 if (ret)
285 return ret;
286 st->chip_config.clk = clock;
287 break;
288 default:
289
290 break;
291 }
292
293 return 0;
294}
295
296int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
297 unsigned int mask)
298{
299 unsigned int sleep;
300 u8 pwr_mgmt2, user_ctrl;
301 int ret;
302
303
304 if (mask & INV_MPU6050_SENSOR_ACCL && en == st->chip_config.accl_en)
305 mask &= ~INV_MPU6050_SENSOR_ACCL;
306 if (mask & INV_MPU6050_SENSOR_GYRO && en == st->chip_config.gyro_en)
307 mask &= ~INV_MPU6050_SENSOR_GYRO;
308 if (mask & INV_MPU6050_SENSOR_TEMP && en == st->chip_config.temp_en)
309 mask &= ~INV_MPU6050_SENSOR_TEMP;
310 if (mask & INV_MPU6050_SENSOR_MAGN && en == st->chip_config.magn_en)
311 mask &= ~INV_MPU6050_SENSOR_MAGN;
312 if (mask == 0)
313 return 0;
314
315
316 if (mask & INV_MPU6050_SENSOR_TEMP) {
317 ret = inv_mpu6050_pwr_mgmt_1_write(st, false, -1, !en);
318 if (ret)
319 return ret;
320 st->chip_config.temp_en = en;
321 }
322
323
324 if (mask & INV_MPU6050_SENSOR_MAGN) {
325 user_ctrl = st->chip_config.user_ctrl;
326 if (en)
327 user_ctrl |= INV_MPU6050_BIT_I2C_MST_EN;
328 else
329 user_ctrl &= ~INV_MPU6050_BIT_I2C_MST_EN;
330 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl);
331 if (ret)
332 return ret;
333 st->chip_config.user_ctrl = user_ctrl;
334 st->chip_config.magn_en = en;
335 }
336
337
338 if (mask & (INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO)) {
339
340 pwr_mgmt2 = 0;
341 if (!st->chip_config.accl_en)
342 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_ACCL_STBY;
343 if (!st->chip_config.gyro_en)
344 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_GYRO_STBY;
345
346
347 if (mask & INV_MPU6050_SENSOR_ACCL) {
348 if (en)
349 pwr_mgmt2 &= ~INV_MPU6050_BIT_PWR_ACCL_STBY;
350 else
351 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_ACCL_STBY;
352 }
353 if (mask & INV_MPU6050_SENSOR_GYRO) {
354 if (en)
355 pwr_mgmt2 &= ~INV_MPU6050_BIT_PWR_GYRO_STBY;
356 else
357 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_GYRO_STBY;
358 }
359
360
361 if (mask & INV_MPU6050_SENSOR_GYRO && !en) {
362 ret = inv_mpu6050_clock_switch(st, INV_CLK_INTERNAL);
363 if (ret)
364 return ret;
365 }
366
367
368 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_2: 0x%x\n",
369 pwr_mgmt2);
370 ret = regmap_write(st->map, st->reg->pwr_mgmt_2, pwr_mgmt2);
371 if (ret)
372 return ret;
373 if (mask & INV_MPU6050_SENSOR_ACCL)
374 st->chip_config.accl_en = en;
375 if (mask & INV_MPU6050_SENSOR_GYRO)
376 st->chip_config.gyro_en = en;
377
378
379 sleep = 0;
380 if (en) {
381 if (mask & INV_MPU6050_SENSOR_ACCL) {
382 if (sleep < INV_MPU6050_ACCEL_UP_TIME)
383 sleep = INV_MPU6050_ACCEL_UP_TIME;
384 }
385 if (mask & INV_MPU6050_SENSOR_GYRO) {
386 if (sleep < INV_MPU6050_GYRO_UP_TIME)
387 sleep = INV_MPU6050_GYRO_UP_TIME;
388 }
389 } else {
390 if (mask & INV_MPU6050_SENSOR_GYRO) {
391 if (sleep < INV_MPU6050_GYRO_DOWN_TIME)
392 sleep = INV_MPU6050_GYRO_DOWN_TIME;
393 }
394 }
395 if (sleep)
396 msleep(sleep);
397
398
399 if (mask & INV_MPU6050_SENSOR_GYRO && en) {
400 ret = inv_mpu6050_clock_switch(st, INV_CLK_PLL);
401 if (ret)
402 return ret;
403 }
404 }
405
406 return 0;
407}
408
409static int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st,
410 bool power_on)
411{
412 int result;
413
414 result = inv_mpu6050_pwr_mgmt_1_write(st, !power_on, -1, -1);
415 if (result)
416 return result;
417
418 if (power_on)
419 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
420 INV_MPU6050_REG_UP_TIME_MAX);
421
422 return 0;
423}
424
425static int inv_mpu6050_set_gyro_fsr(struct inv_mpu6050_state *st,
426 enum inv_mpu6050_fsr_e val)
427{
428 unsigned int gyro_shift;
429 u8 data;
430
431 switch (st->chip_type) {
432 case INV_ICM20690:
433 gyro_shift = INV_ICM20690_GYRO_CONFIG_FSR_SHIFT;
434 break;
435 default:
436 gyro_shift = INV_MPU6050_GYRO_CONFIG_FSR_SHIFT;
437 break;
438 }
439
440 data = val << gyro_shift;
441 return regmap_write(st->map, st->reg->gyro_config, data);
442}
443
444
445
446
447
448
449
450static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
451 enum inv_mpu6050_filter_e val)
452{
453 int result;
454
455 result = regmap_write(st->map, st->reg->lpf, val);
456 if (result)
457 return result;
458
459
460 switch (st->chip_type) {
461 case INV_MPU6050:
462 case INV_MPU6000:
463 case INV_MPU9150:
464
465 return 0;
466 case INV_ICM20689:
467 case INV_ICM20690:
468
469 val |= INV_ICM20689_BITS_FIFO_SIZE_MAX;
470 break;
471 default:
472 break;
473 }
474
475 return regmap_write(st->map, st->reg->accel_lpf, val);
476}
477
478
479
480
481
482
483
484
485
486
487static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
488{
489 int result;
490 u8 d;
491 struct inv_mpu6050_state *st = iio_priv(indio_dev);
492
493 result = inv_mpu6050_set_gyro_fsr(st, st->chip_config.fsr);
494 if (result)
495 return result;
496
497 result = inv_mpu6050_set_lpf_regs(st, st->chip_config.lpf);
498 if (result)
499 return result;
500
501 d = st->chip_config.divider;
502 result = regmap_write(st->map, st->reg->sample_rate_div, d);
503 if (result)
504 return result;
505
506 d = (st->chip_config.accl_fs << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
507 result = regmap_write(st->map, st->reg->accl_config, d);
508 if (result)
509 return result;
510
511 result = regmap_write(st->map, st->reg->int_pin_cfg, st->irq_mask);
512 if (result)
513 return result;
514
515
516
517
518
519
520 st->chip_period = NSEC_PER_MSEC;
521
522
523 result = inv_mpu_magn_probe(st);
524 if (result)
525 return result;
526
527 return 0;
528}
529
530static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
531 int axis, int val)
532{
533 int ind, result;
534 __be16 d = cpu_to_be16(val);
535
536 ind = (axis - IIO_MOD_X) * 2;
537 result = regmap_bulk_write(st->map, reg + ind, &d, sizeof(d));
538 if (result)
539 return -EINVAL;
540
541 return 0;
542}
543
544static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
545 int axis, int *val)
546{
547 int ind, result;
548 __be16 d;
549
550 ind = (axis - IIO_MOD_X) * 2;
551 result = regmap_bulk_read(st->map, reg + ind, &d, sizeof(d));
552 if (result)
553 return -EINVAL;
554 *val = (short)be16_to_cpup(&d);
555
556 return IIO_VAL_INT;
557}
558
559static int inv_mpu6050_read_channel_data(struct iio_dev *indio_dev,
560 struct iio_chan_spec const *chan,
561 int *val)
562{
563 struct inv_mpu6050_state *st = iio_priv(indio_dev);
564 struct device *pdev = regmap_get_device(st->map);
565 unsigned int freq_hz, period_us, min_sleep_us, max_sleep_us;
566 int result;
567 int ret;
568
569
570 freq_hz = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
571 period_us = 1000000 / freq_hz;
572
573 result = pm_runtime_get_sync(pdev);
574 if (result < 0) {
575 pm_runtime_put_noidle(pdev);
576 return result;
577 }
578
579 switch (chan->type) {
580 case IIO_ANGL_VEL:
581 if (!st->chip_config.gyro_en) {
582 result = inv_mpu6050_switch_engine(st, true,
583 INV_MPU6050_SENSOR_GYRO);
584 if (result)
585 goto error_power_off;
586
587 min_sleep_us = 2 * period_us;
588 max_sleep_us = 2 * (period_us + period_us / 2);
589 usleep_range(min_sleep_us, max_sleep_us);
590 }
591 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
592 chan->channel2, val);
593 break;
594 case IIO_ACCEL:
595 if (!st->chip_config.accl_en) {
596 result = inv_mpu6050_switch_engine(st, true,
597 INV_MPU6050_SENSOR_ACCL);
598 if (result)
599 goto error_power_off;
600
601 min_sleep_us = period_us;
602 max_sleep_us = period_us + period_us / 2;
603 usleep_range(min_sleep_us, max_sleep_us);
604 }
605 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
606 chan->channel2, val);
607 break;
608 case IIO_TEMP:
609
610 if (!st->chip_config.accl_en && !st->chip_config.gyro_en) {
611 result = -EBUSY;
612 goto error_power_off;
613 }
614 if (!st->chip_config.temp_en) {
615 result = inv_mpu6050_switch_engine(st, true,
616 INV_MPU6050_SENSOR_TEMP);
617 if (result)
618 goto error_power_off;
619
620 min_sleep_us = period_us;
621 max_sleep_us = period_us + period_us / 2;
622 usleep_range(min_sleep_us, max_sleep_us);
623 }
624 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
625 IIO_MOD_X, val);
626 break;
627 case IIO_MAGN:
628 if (!st->chip_config.magn_en) {
629 result = inv_mpu6050_switch_engine(st, true,
630 INV_MPU6050_SENSOR_MAGN);
631 if (result)
632 goto error_power_off;
633
634 if (freq_hz > INV_MPU_MAGN_FREQ_HZ_MAX) {
635 freq_hz = INV_MPU_MAGN_FREQ_HZ_MAX;
636 period_us = 1000000 / freq_hz;
637 }
638
639 min_sleep_us = 2 * period_us;
640 max_sleep_us = 2 * (period_us + period_us / 2);
641 usleep_range(min_sleep_us, max_sleep_us);
642 }
643 ret = inv_mpu_magn_read(st, chan->channel2, val);
644 break;
645 default:
646 ret = -EINVAL;
647 break;
648 }
649
650 pm_runtime_mark_last_busy(pdev);
651 pm_runtime_put_autosuspend(pdev);
652
653 return ret;
654
655error_power_off:
656 pm_runtime_put_autosuspend(pdev);
657 return result;
658}
659
660static int
661inv_mpu6050_read_raw(struct iio_dev *indio_dev,
662 struct iio_chan_spec const *chan,
663 int *val, int *val2, long mask)
664{
665 struct inv_mpu6050_state *st = iio_priv(indio_dev);
666 int ret = 0;
667
668 switch (mask) {
669 case IIO_CHAN_INFO_RAW:
670 ret = iio_device_claim_direct_mode(indio_dev);
671 if (ret)
672 return ret;
673 mutex_lock(&st->lock);
674 ret = inv_mpu6050_read_channel_data(indio_dev, chan, val);
675 mutex_unlock(&st->lock);
676 iio_device_release_direct_mode(indio_dev);
677 return ret;
678 case IIO_CHAN_INFO_SCALE:
679 switch (chan->type) {
680 case IIO_ANGL_VEL:
681 mutex_lock(&st->lock);
682 *val = 0;
683 *val2 = gyro_scale_6050[st->chip_config.fsr];
684 mutex_unlock(&st->lock);
685
686 return IIO_VAL_INT_PLUS_NANO;
687 case IIO_ACCEL:
688 mutex_lock(&st->lock);
689 *val = 0;
690 *val2 = accel_scale[st->chip_config.accl_fs];
691 mutex_unlock(&st->lock);
692
693 return IIO_VAL_INT_PLUS_MICRO;
694 case IIO_TEMP:
695 *val = st->hw->temp.scale / 1000000;
696 *val2 = st->hw->temp.scale % 1000000;
697 return IIO_VAL_INT_PLUS_MICRO;
698 case IIO_MAGN:
699 return inv_mpu_magn_get_scale(st, chan, val, val2);
700 default:
701 return -EINVAL;
702 }
703 case IIO_CHAN_INFO_OFFSET:
704 switch (chan->type) {
705 case IIO_TEMP:
706 *val = st->hw->temp.offset;
707 return IIO_VAL_INT;
708 default:
709 return -EINVAL;
710 }
711 case IIO_CHAN_INFO_CALIBBIAS:
712 switch (chan->type) {
713 case IIO_ANGL_VEL:
714 mutex_lock(&st->lock);
715 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
716 chan->channel2, val);
717 mutex_unlock(&st->lock);
718 return IIO_VAL_INT;
719 case IIO_ACCEL:
720 mutex_lock(&st->lock);
721 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
722 chan->channel2, val);
723 mutex_unlock(&st->lock);
724 return IIO_VAL_INT;
725
726 default:
727 return -EINVAL;
728 }
729 default:
730 return -EINVAL;
731 }
732}
733
734static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val,
735 int val2)
736{
737 int result, i;
738
739 if (val != 0)
740 return -EINVAL;
741
742 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
743 if (gyro_scale_6050[i] == val2) {
744 result = inv_mpu6050_set_gyro_fsr(st, i);
745 if (result)
746 return result;
747
748 st->chip_config.fsr = i;
749 return 0;
750 }
751 }
752
753 return -EINVAL;
754}
755
756static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
757 struct iio_chan_spec const *chan, long mask)
758{
759 switch (mask) {
760 case IIO_CHAN_INFO_SCALE:
761 switch (chan->type) {
762 case IIO_ANGL_VEL:
763 return IIO_VAL_INT_PLUS_NANO;
764 default:
765 return IIO_VAL_INT_PLUS_MICRO;
766 }
767 default:
768 return IIO_VAL_INT_PLUS_MICRO;
769 }
770
771 return -EINVAL;
772}
773
774static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val,
775 int val2)
776{
777 int result, i;
778 u8 d;
779
780 if (val != 0)
781 return -EINVAL;
782
783 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
784 if (accel_scale[i] == val2) {
785 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
786 result = regmap_write(st->map, st->reg->accl_config, d);
787 if (result)
788 return result;
789
790 st->chip_config.accl_fs = i;
791 return 0;
792 }
793 }
794
795 return -EINVAL;
796}
797
798static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
799 struct iio_chan_spec const *chan,
800 int val, int val2, long mask)
801{
802 struct inv_mpu6050_state *st = iio_priv(indio_dev);
803 struct device *pdev = regmap_get_device(st->map);
804 int result;
805
806
807
808
809
810 result = iio_device_claim_direct_mode(indio_dev);
811 if (result)
812 return result;
813
814 mutex_lock(&st->lock);
815 result = pm_runtime_get_sync(pdev);
816 if (result < 0) {
817 pm_runtime_put_noidle(pdev);
818 goto error_write_raw_unlock;
819 }
820
821 switch (mask) {
822 case IIO_CHAN_INFO_SCALE:
823 switch (chan->type) {
824 case IIO_ANGL_VEL:
825 result = inv_mpu6050_write_gyro_scale(st, val, val2);
826 break;
827 case IIO_ACCEL:
828 result = inv_mpu6050_write_accel_scale(st, val, val2);
829 break;
830 default:
831 result = -EINVAL;
832 break;
833 }
834 break;
835 case IIO_CHAN_INFO_CALIBBIAS:
836 switch (chan->type) {
837 case IIO_ANGL_VEL:
838 result = inv_mpu6050_sensor_set(st,
839 st->reg->gyro_offset,
840 chan->channel2, val);
841 break;
842 case IIO_ACCEL:
843 result = inv_mpu6050_sensor_set(st,
844 st->reg->accl_offset,
845 chan->channel2, val);
846 break;
847 default:
848 result = -EINVAL;
849 break;
850 }
851 break;
852 default:
853 result = -EINVAL;
854 break;
855 }
856
857 pm_runtime_mark_last_busy(pdev);
858 pm_runtime_put_autosuspend(pdev);
859error_write_raw_unlock:
860 mutex_unlock(&st->lock);
861 iio_device_release_direct_mode(indio_dev);
862
863 return result;
864}
865
866
867
868
869
870
871
872
873
874
875
876
877static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
878{
879 static const int hz[] = {400, 200, 90, 40, 20, 10};
880 static const int d[] = {
881 INV_MPU6050_FILTER_200HZ, INV_MPU6050_FILTER_100HZ,
882 INV_MPU6050_FILTER_45HZ, INV_MPU6050_FILTER_20HZ,
883 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ
884 };
885 int i, result;
886 u8 data;
887
888 data = INV_MPU6050_FILTER_5HZ;
889 for (i = 0; i < ARRAY_SIZE(hz); ++i) {
890 if (rate >= hz[i]) {
891 data = d[i];
892 break;
893 }
894 }
895 result = inv_mpu6050_set_lpf_regs(st, data);
896 if (result)
897 return result;
898 st->chip_config.lpf = data;
899
900 return 0;
901}
902
903
904
905
906static ssize_t
907inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
908 const char *buf, size_t count)
909{
910 int fifo_rate;
911 u8 d;
912 int result;
913 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
914 struct inv_mpu6050_state *st = iio_priv(indio_dev);
915 struct device *pdev = regmap_get_device(st->map);
916
917 if (kstrtoint(buf, 10, &fifo_rate))
918 return -EINVAL;
919 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
920 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
921 return -EINVAL;
922
923
924 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate);
925
926 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(d);
927
928 mutex_lock(&st->lock);
929 if (d == st->chip_config.divider) {
930 result = 0;
931 goto fifo_rate_fail_unlock;
932 }
933 result = pm_runtime_get_sync(pdev);
934 if (result < 0) {
935 pm_runtime_put_noidle(pdev);
936 goto fifo_rate_fail_unlock;
937 }
938
939 result = regmap_write(st->map, st->reg->sample_rate_div, d);
940 if (result)
941 goto fifo_rate_fail_power_off;
942 st->chip_config.divider = d;
943
944 result = inv_mpu6050_set_lpf(st, fifo_rate);
945 if (result)
946 goto fifo_rate_fail_power_off;
947
948
949 result = inv_mpu_magn_set_rate(st, fifo_rate);
950 if (result)
951 goto fifo_rate_fail_power_off;
952
953 pm_runtime_mark_last_busy(pdev);
954fifo_rate_fail_power_off:
955 pm_runtime_put_autosuspend(pdev);
956fifo_rate_fail_unlock:
957 mutex_unlock(&st->lock);
958 if (result)
959 return result;
960
961 return count;
962}
963
964
965
966
967static ssize_t
968inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
969 char *buf)
970{
971 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
972 unsigned fifo_rate;
973
974 mutex_lock(&st->lock);
975 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
976 mutex_unlock(&st->lock);
977
978 return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate);
979}
980
981
982
983
984
985
986
987
988
989static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
990 char *buf)
991{
992 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
993 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
994 s8 *m;
995
996 switch (this_attr->address) {
997
998
999
1000
1001 case ATTR_GYRO_MATRIX:
1002 case ATTR_ACCL_MATRIX:
1003 m = st->plat_data.orientation;
1004
1005 return scnprintf(buf, PAGE_SIZE,
1006 "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
1007 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
1008 default:
1009 return -EINVAL;
1010 }
1011}
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
1023 struct iio_trigger *trig)
1024{
1025 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1026
1027 if (st->trig != trig)
1028 return -EINVAL;
1029
1030 return 0;
1031}
1032
1033static const struct iio_mount_matrix *
1034inv_get_mount_matrix(const struct iio_dev *indio_dev,
1035 const struct iio_chan_spec *chan)
1036{
1037 struct inv_mpu6050_state *data = iio_priv(indio_dev);
1038 const struct iio_mount_matrix *matrix;
1039
1040 if (chan->type == IIO_MAGN)
1041 matrix = &data->magn_orient;
1042 else
1043 matrix = &data->orientation;
1044
1045 return matrix;
1046}
1047
1048static const struct iio_chan_spec_ext_info inv_ext_info[] = {
1049 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
1050 { }
1051};
1052
1053#define INV_MPU6050_CHAN(_type, _channel2, _index) \
1054 { \
1055 .type = _type, \
1056 .modified = 1, \
1057 .channel2 = _channel2, \
1058 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1059 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1060 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1061 .scan_index = _index, \
1062 .scan_type = { \
1063 .sign = 's', \
1064 .realbits = 16, \
1065 .storagebits = 16, \
1066 .shift = 0, \
1067 .endianness = IIO_BE, \
1068 }, \
1069 .ext_info = inv_ext_info, \
1070 }
1071
1072#define INV_MPU6050_TEMP_CHAN(_index) \
1073 { \
1074 .type = IIO_TEMP, \
1075 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1076 | BIT(IIO_CHAN_INFO_OFFSET) \
1077 | BIT(IIO_CHAN_INFO_SCALE), \
1078 .scan_index = _index, \
1079 .scan_type = { \
1080 .sign = 's', \
1081 .realbits = 16, \
1082 .storagebits = 16, \
1083 .shift = 0, \
1084 .endianness = IIO_BE, \
1085 }, \
1086 }
1087
1088static const struct iio_chan_spec inv_mpu_channels[] = {
1089 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
1090
1091 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1092
1093 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1094 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1095 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1096
1097 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1098 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1099 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1100};
1101
1102#define INV_MPU6050_SCAN_MASK_3AXIS_ACCEL \
1103 (BIT(INV_MPU6050_SCAN_ACCL_X) \
1104 | BIT(INV_MPU6050_SCAN_ACCL_Y) \
1105 | BIT(INV_MPU6050_SCAN_ACCL_Z))
1106
1107#define INV_MPU6050_SCAN_MASK_3AXIS_GYRO \
1108 (BIT(INV_MPU6050_SCAN_GYRO_X) \
1109 | BIT(INV_MPU6050_SCAN_GYRO_Y) \
1110 | BIT(INV_MPU6050_SCAN_GYRO_Z))
1111
1112#define INV_MPU6050_SCAN_MASK_TEMP (BIT(INV_MPU6050_SCAN_TEMP))
1113
1114static const unsigned long inv_mpu_scan_masks[] = {
1115
1116 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL,
1117 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1118
1119 INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1120 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1121
1122 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1123 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1124 | INV_MPU6050_SCAN_MASK_TEMP,
1125 0,
1126};
1127
1128#define INV_MPU9X50_MAGN_CHAN(_chan2, _bits, _index) \
1129 { \
1130 .type = IIO_MAGN, \
1131 .modified = 1, \
1132 .channel2 = _chan2, \
1133 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | \
1134 BIT(IIO_CHAN_INFO_RAW), \
1135 .scan_index = _index, \
1136 .scan_type = { \
1137 .sign = 's', \
1138 .realbits = _bits, \
1139 .storagebits = 16, \
1140 .shift = 0, \
1141 .endianness = IIO_BE, \
1142 }, \
1143 .ext_info = inv_ext_info, \
1144 }
1145
1146static const struct iio_chan_spec inv_mpu9150_channels[] = {
1147 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU9X50_SCAN_TIMESTAMP),
1148
1149 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1150
1151 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1152 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1153 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1154
1155 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1156 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1157 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1158
1159
1160 INV_MPU9X50_MAGN_CHAN(IIO_MOD_X, 13, INV_MPU9X50_SCAN_MAGN_X),
1161 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Y, 13, INV_MPU9X50_SCAN_MAGN_Y),
1162 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Z, 13, INV_MPU9X50_SCAN_MAGN_Z),
1163};
1164
1165static const struct iio_chan_spec inv_mpu9250_channels[] = {
1166 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU9X50_SCAN_TIMESTAMP),
1167
1168 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1169
1170 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1171 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1172 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1173
1174 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1175 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1176 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1177
1178
1179 INV_MPU9X50_MAGN_CHAN(IIO_MOD_X, 16, INV_MPU9X50_SCAN_MAGN_X),
1180 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Y, 16, INV_MPU9X50_SCAN_MAGN_Y),
1181 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Z, 16, INV_MPU9X50_SCAN_MAGN_Z),
1182};
1183
1184#define INV_MPU9X50_SCAN_MASK_3AXIS_MAGN \
1185 (BIT(INV_MPU9X50_SCAN_MAGN_X) \
1186 | BIT(INV_MPU9X50_SCAN_MAGN_Y) \
1187 | BIT(INV_MPU9X50_SCAN_MAGN_Z))
1188
1189static const unsigned long inv_mpu9x50_scan_masks[] = {
1190
1191 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL,
1192 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1193
1194 INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1195 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1196
1197 INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1198 INV_MPU9X50_SCAN_MASK_3AXIS_MAGN | INV_MPU6050_SCAN_MASK_TEMP,
1199
1200 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1201 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1202 | INV_MPU6050_SCAN_MASK_TEMP,
1203
1204 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1205 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1206 | INV_MPU6050_SCAN_MASK_TEMP,
1207
1208 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1209 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1210 | INV_MPU6050_SCAN_MASK_TEMP,
1211
1212 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1213 | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1214 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1215 | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1216 | INV_MPU6050_SCAN_MASK_TEMP,
1217 0,
1218};
1219
1220static const unsigned long inv_icm20602_scan_masks[] = {
1221
1222 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1223
1224 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1225
1226 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1227 | INV_MPU6050_SCAN_MASK_TEMP,
1228 0,
1229};
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
1240static IIO_CONST_ATTR(in_anglvel_scale_available,
1241 "0.000133090 0.000266181 0.000532362 0.001064724");
1242static IIO_CONST_ATTR(in_accel_scale_available,
1243 "0.000598 0.001196 0.002392 0.004785");
1244static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
1245 inv_mpu6050_fifo_rate_store);
1246
1247
1248static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
1249 ATTR_GYRO_MATRIX);
1250static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
1251 ATTR_ACCL_MATRIX);
1252
1253static struct attribute *inv_attributes[] = {
1254 &iio_dev_attr_in_gyro_matrix.dev_attr.attr,
1255 &iio_dev_attr_in_accel_matrix.dev_attr.attr,
1256 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1257 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1258 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
1259 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
1260 NULL,
1261};
1262
1263static const struct attribute_group inv_attribute_group = {
1264 .attrs = inv_attributes
1265};
1266
1267static int inv_mpu6050_reg_access(struct iio_dev *indio_dev,
1268 unsigned int reg,
1269 unsigned int writeval,
1270 unsigned int *readval)
1271{
1272 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1273 int ret;
1274
1275 mutex_lock(&st->lock);
1276 if (readval)
1277 ret = regmap_read(st->map, reg, readval);
1278 else
1279 ret = regmap_write(st->map, reg, writeval);
1280 mutex_unlock(&st->lock);
1281
1282 return ret;
1283}
1284
1285static const struct iio_info mpu_info = {
1286 .read_raw = &inv_mpu6050_read_raw,
1287 .write_raw = &inv_mpu6050_write_raw,
1288 .write_raw_get_fmt = &inv_write_raw_get_fmt,
1289 .attrs = &inv_attribute_group,
1290 .validate_trigger = inv_mpu6050_validate_trigger,
1291 .debugfs_reg_access = &inv_mpu6050_reg_access,
1292};
1293
1294
1295
1296
1297static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
1298{
1299 int result;
1300 unsigned int regval, mask;
1301 int i;
1302
1303 st->hw = &hw_info[st->chip_type];
1304 st->reg = hw_info[st->chip_type].reg;
1305 memcpy(&st->chip_config, hw_info[st->chip_type].config,
1306 sizeof(st->chip_config));
1307
1308
1309 result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val);
1310 if (result)
1311 return result;
1312 if (regval != st->hw->whoami) {
1313
1314 for (i = 0; i < INV_NUM_PARTS; ++i) {
1315 if (regval == hw_info[i].whoami) {
1316 dev_warn(regmap_get_device(st->map),
1317 "whoami mismatch got %#02x (%s)"
1318 "expected %#02hhx (%s)\n",
1319 regval, hw_info[i].name,
1320 st->hw->whoami, st->hw->name);
1321 break;
1322 }
1323 }
1324 if (i >= INV_NUM_PARTS) {
1325 dev_err(regmap_get_device(st->map),
1326 "invalid whoami %#02x expected %#02hhx (%s)\n",
1327 regval, st->hw->whoami, st->hw->name);
1328 return -ENODEV;
1329 }
1330 }
1331
1332
1333 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
1334 INV_MPU6050_BIT_H_RESET);
1335 if (result)
1336 return result;
1337 msleep(INV_MPU6050_POWER_UP_TIME);
1338 switch (st->chip_type) {
1339 case INV_MPU6000:
1340 case INV_MPU6500:
1341 case INV_MPU6515:
1342 case INV_MPU6880:
1343 case INV_MPU9250:
1344 case INV_MPU9255:
1345
1346 regval = INV_MPU6050_BIT_TEMP_RST | INV_MPU6050_BIT_ACCEL_RST |
1347 INV_MPU6050_BIT_GYRO_RST;
1348 result = regmap_write(st->map, INV_MPU6050_REG_SIGNAL_PATH_RESET,
1349 regval);
1350 if (result)
1351 return result;
1352 msleep(INV_MPU6050_POWER_UP_TIME);
1353 break;
1354 default:
1355 break;
1356 }
1357
1358
1359
1360
1361
1362
1363
1364 result = inv_mpu6050_set_power_itg(st, true);
1365 if (result)
1366 return result;
1367 mask = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO |
1368 INV_MPU6050_SENSOR_TEMP | INV_MPU6050_SENSOR_MAGN;
1369 result = inv_mpu6050_switch_engine(st, false, mask);
1370 if (result)
1371 goto error_power_off;
1372
1373 return 0;
1374
1375error_power_off:
1376 inv_mpu6050_set_power_itg(st, false);
1377 return result;
1378}
1379
1380static int inv_mpu_core_enable_regulator_vddio(struct inv_mpu6050_state *st)
1381{
1382 int result;
1383
1384 result = regulator_enable(st->vddio_supply);
1385 if (result) {
1386 dev_err(regmap_get_device(st->map),
1387 "Failed to enable vddio regulator: %d\n", result);
1388 } else {
1389
1390 usleep_range(3000, 5000);
1391 }
1392
1393 return result;
1394}
1395
1396static int inv_mpu_core_disable_regulator_vddio(struct inv_mpu6050_state *st)
1397{
1398 int result;
1399
1400 result = regulator_disable(st->vddio_supply);
1401 if (result)
1402 dev_err(regmap_get_device(st->map),
1403 "Failed to disable vddio regulator: %d\n", result);
1404
1405 return result;
1406}
1407
1408static void inv_mpu_core_disable_regulator_action(void *_data)
1409{
1410 struct inv_mpu6050_state *st = _data;
1411 int result;
1412
1413 result = regulator_disable(st->vdd_supply);
1414 if (result)
1415 dev_err(regmap_get_device(st->map),
1416 "Failed to disable vdd regulator: %d\n", result);
1417
1418 inv_mpu_core_disable_regulator_vddio(st);
1419}
1420
1421static void inv_mpu_pm_disable(void *data)
1422{
1423 struct device *dev = data;
1424
1425 pm_runtime_put_sync_suspend(dev);
1426 pm_runtime_disable(dev);
1427}
1428
1429int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
1430 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
1431{
1432 struct inv_mpu6050_state *st;
1433 struct iio_dev *indio_dev;
1434 struct inv_mpu6050_platform_data *pdata;
1435 struct device *dev = regmap_get_device(regmap);
1436 int result;
1437 struct irq_data *desc;
1438 int irq_type;
1439
1440 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1441 if (!indio_dev)
1442 return -ENOMEM;
1443
1444 BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
1445 if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
1446 dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
1447 chip_type, name);
1448 return -ENODEV;
1449 }
1450 st = iio_priv(indio_dev);
1451 mutex_init(&st->lock);
1452 st->chip_type = chip_type;
1453 st->irq = irq;
1454 st->map = regmap;
1455
1456 pdata = dev_get_platdata(dev);
1457 if (!pdata) {
1458 result = iio_read_mount_matrix(dev, "mount-matrix",
1459 &st->orientation);
1460 if (result) {
1461 dev_err(dev, "Failed to retrieve mounting matrix %d\n",
1462 result);
1463 return result;
1464 }
1465 } else {
1466 st->plat_data = *pdata;
1467 }
1468
1469 if (irq > 0) {
1470 desc = irq_get_irq_data(irq);
1471 if (!desc) {
1472 dev_err(dev, "Could not find IRQ %d\n", irq);
1473 return -EINVAL;
1474 }
1475
1476 irq_type = irqd_get_trigger_type(desc);
1477 if (!irq_type)
1478 irq_type = IRQF_TRIGGER_RISING;
1479 } else {
1480
1481 irq_type = IRQF_TRIGGER_RISING;
1482 }
1483
1484 if (irq_type & IRQF_TRIGGER_RISING)
1485 st->irq_mask = INV_MPU6050_ACTIVE_HIGH;
1486 else if (irq_type == IRQF_TRIGGER_FALLING)
1487 st->irq_mask = INV_MPU6050_ACTIVE_LOW;
1488 else if (irq_type == IRQF_TRIGGER_HIGH)
1489 st->irq_mask = INV_MPU6050_ACTIVE_HIGH |
1490 INV_MPU6050_LATCH_INT_EN;
1491 else if (irq_type == IRQF_TRIGGER_LOW)
1492 st->irq_mask = INV_MPU6050_ACTIVE_LOW |
1493 INV_MPU6050_LATCH_INT_EN;
1494 else {
1495 dev_err(dev, "Invalid interrupt type 0x%x specified\n",
1496 irq_type);
1497 return -EINVAL;
1498 }
1499
1500 st->vdd_supply = devm_regulator_get(dev, "vdd");
1501 if (IS_ERR(st->vdd_supply))
1502 return dev_err_probe(dev, PTR_ERR(st->vdd_supply),
1503 "Failed to get vdd regulator\n");
1504
1505 st->vddio_supply = devm_regulator_get(dev, "vddio");
1506 if (IS_ERR(st->vddio_supply))
1507 return dev_err_probe(dev, PTR_ERR(st->vddio_supply),
1508 "Failed to get vddio regulator\n");
1509
1510 result = regulator_enable(st->vdd_supply);
1511 if (result) {
1512 dev_err(dev, "Failed to enable vdd regulator: %d\n", result);
1513 return result;
1514 }
1515 msleep(INV_MPU6050_POWER_UP_TIME);
1516
1517 result = inv_mpu_core_enable_regulator_vddio(st);
1518 if (result) {
1519 regulator_disable(st->vdd_supply);
1520 return result;
1521 }
1522
1523 result = devm_add_action_or_reset(dev, inv_mpu_core_disable_regulator_action,
1524 st);
1525 if (result) {
1526 dev_err(dev, "Failed to setup regulator cleanup action %d\n",
1527 result);
1528 return result;
1529 }
1530
1531
1532 result = inv_mpu_magn_set_orient(st);
1533 if (result)
1534 return result;
1535
1536
1537 result = inv_check_and_setup_chip(st);
1538 if (result)
1539 return result;
1540
1541 result = inv_mpu6050_init_config(indio_dev);
1542 if (result) {
1543 dev_err(dev, "Could not initialize device.\n");
1544 goto error_power_off;
1545 }
1546
1547 dev_set_drvdata(dev, indio_dev);
1548
1549 if (name)
1550 indio_dev->name = name;
1551 else
1552 indio_dev->name = dev_name(dev);
1553
1554
1555 if (inv_mpu_bus_setup) {
1556 result = inv_mpu_bus_setup(indio_dev);
1557 if (result)
1558 goto error_power_off;
1559 }
1560
1561
1562 result = pm_runtime_set_active(dev);
1563 if (result)
1564 goto error_power_off;
1565 pm_runtime_get_noresume(dev);
1566 pm_runtime_enable(dev);
1567 pm_runtime_set_autosuspend_delay(dev, INV_MPU6050_SUSPEND_DELAY_MS);
1568 pm_runtime_use_autosuspend(dev);
1569 pm_runtime_put(dev);
1570 result = devm_add_action_or_reset(dev, inv_mpu_pm_disable, dev);
1571 if (result)
1572 return result;
1573
1574 switch (chip_type) {
1575 case INV_MPU9150:
1576 indio_dev->channels = inv_mpu9150_channels;
1577 indio_dev->num_channels = ARRAY_SIZE(inv_mpu9150_channels);
1578 indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
1579 break;
1580 case INV_MPU9250:
1581 case INV_MPU9255:
1582 indio_dev->channels = inv_mpu9250_channels;
1583 indio_dev->num_channels = ARRAY_SIZE(inv_mpu9250_channels);
1584 indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
1585 break;
1586 case INV_ICM20602:
1587 indio_dev->channels = inv_mpu_channels;
1588 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1589 indio_dev->available_scan_masks = inv_icm20602_scan_masks;
1590 break;
1591 default:
1592 indio_dev->channels = inv_mpu_channels;
1593 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1594 indio_dev->available_scan_masks = inv_mpu_scan_masks;
1595 break;
1596 }
1597
1598
1599
1600
1601 if (st->magn_disabled) {
1602 indio_dev->channels = inv_mpu_channels;
1603 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1604 indio_dev->available_scan_masks = inv_mpu_scan_masks;
1605 }
1606
1607 indio_dev->info = &mpu_info;
1608
1609 if (irq > 0) {
1610
1611
1612
1613
1614 result = devm_iio_triggered_buffer_setup(dev, indio_dev,
1615 iio_pollfunc_store_time,
1616 inv_mpu6050_read_fifo,
1617 NULL);
1618 if (result) {
1619 dev_err(dev, "configure buffer fail %d\n", result);
1620 return result;
1621 }
1622
1623 result = inv_mpu6050_probe_trigger(indio_dev, irq_type);
1624 if (result) {
1625 dev_err(dev, "trigger probe fail %d\n", result);
1626 return result;
1627 }
1628 }
1629
1630 result = devm_iio_device_register(dev, indio_dev);
1631 if (result) {
1632 dev_err(dev, "IIO register fail %d\n", result);
1633 return result;
1634 }
1635
1636 return 0;
1637
1638error_power_off:
1639 inv_mpu6050_set_power_itg(st, false);
1640 return result;
1641}
1642EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
1643
1644static int __maybe_unused inv_mpu_resume(struct device *dev)
1645{
1646 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1647 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1648 int result;
1649
1650 mutex_lock(&st->lock);
1651 result = inv_mpu_core_enable_regulator_vddio(st);
1652 if (result)
1653 goto out_unlock;
1654
1655 result = inv_mpu6050_set_power_itg(st, true);
1656 if (result)
1657 goto out_unlock;
1658
1659 pm_runtime_disable(dev);
1660 pm_runtime_set_active(dev);
1661 pm_runtime_enable(dev);
1662
1663 result = inv_mpu6050_switch_engine(st, true, st->suspended_sensors);
1664 if (result)
1665 goto out_unlock;
1666
1667 if (iio_buffer_enabled(indio_dev))
1668 result = inv_mpu6050_prepare_fifo(st, true);
1669
1670out_unlock:
1671 mutex_unlock(&st->lock);
1672
1673 return result;
1674}
1675
1676static int __maybe_unused inv_mpu_suspend(struct device *dev)
1677{
1678 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1679 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1680 int result;
1681
1682 mutex_lock(&st->lock);
1683
1684 st->suspended_sensors = 0;
1685 if (pm_runtime_suspended(dev)) {
1686 result = 0;
1687 goto out_unlock;
1688 }
1689
1690 if (iio_buffer_enabled(indio_dev)) {
1691 result = inv_mpu6050_prepare_fifo(st, false);
1692 if (result)
1693 goto out_unlock;
1694 }
1695
1696 if (st->chip_config.accl_en)
1697 st->suspended_sensors |= INV_MPU6050_SENSOR_ACCL;
1698 if (st->chip_config.gyro_en)
1699 st->suspended_sensors |= INV_MPU6050_SENSOR_GYRO;
1700 if (st->chip_config.temp_en)
1701 st->suspended_sensors |= INV_MPU6050_SENSOR_TEMP;
1702 if (st->chip_config.magn_en)
1703 st->suspended_sensors |= INV_MPU6050_SENSOR_MAGN;
1704 result = inv_mpu6050_switch_engine(st, false, st->suspended_sensors);
1705 if (result)
1706 goto out_unlock;
1707
1708 result = inv_mpu6050_set_power_itg(st, false);
1709 if (result)
1710 goto out_unlock;
1711
1712 inv_mpu_core_disable_regulator_vddio(st);
1713out_unlock:
1714 mutex_unlock(&st->lock);
1715
1716 return result;
1717}
1718
1719static int __maybe_unused inv_mpu_runtime_suspend(struct device *dev)
1720{
1721 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1722 unsigned int sensors;
1723 int ret;
1724
1725 mutex_lock(&st->lock);
1726
1727 sensors = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO |
1728 INV_MPU6050_SENSOR_TEMP | INV_MPU6050_SENSOR_MAGN;
1729 ret = inv_mpu6050_switch_engine(st, false, sensors);
1730 if (ret)
1731 goto out_unlock;
1732
1733 ret = inv_mpu6050_set_power_itg(st, false);
1734 if (ret)
1735 goto out_unlock;
1736
1737 inv_mpu_core_disable_regulator_vddio(st);
1738
1739out_unlock:
1740 mutex_unlock(&st->lock);
1741 return ret;
1742}
1743
1744static int __maybe_unused inv_mpu_runtime_resume(struct device *dev)
1745{
1746 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1747 int ret;
1748
1749 ret = inv_mpu_core_enable_regulator_vddio(st);
1750 if (ret)
1751 return ret;
1752
1753 return inv_mpu6050_set_power_itg(st, true);
1754}
1755
1756const struct dev_pm_ops inv_mpu_pmops = {
1757 SET_SYSTEM_SLEEP_PM_OPS(inv_mpu_suspend, inv_mpu_resume)
1758 SET_RUNTIME_PM_OPS(inv_mpu_runtime_suspend, inv_mpu_runtime_resume, NULL)
1759};
1760EXPORT_SYMBOL_GPL(inv_mpu_pmops);
1761
1762MODULE_AUTHOR("Invensense Corporation");
1763MODULE_DESCRIPTION("Invensense device MPU6050 driver");
1764MODULE_LICENSE("GPL");
1765
