1
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6
7#include <asm/unaligned.h>
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/i2c.h>
12#include <linux/module.h>
13#include <linux/pm_runtime.h>
14
15#include <media/v4l2-ctrls.h>
16#include <media/v4l2-fwnode.h>
17#include <media/v4l2-subdev.h>
18
19
20#define IMX334_REG_MODE_SELECT 0x3000
21#define IMX334_MODE_STANDBY 0x01
22#define IMX334_MODE_STREAMING 0x00
23
24
25#define IMX334_REG_LPFR 0x3030
26
27
28#define IMX334_REG_ID 0x3044
29#define IMX334_ID 0x1e
30
31
32#define IMX334_REG_SHUTTER 0x3058
33#define IMX334_EXPOSURE_MIN 1
34#define IMX334_EXPOSURE_OFFSET 5
35#define IMX334_EXPOSURE_STEP 1
36#define IMX334_EXPOSURE_DEFAULT 0x0648
37
38
39#define IMX334_REG_AGAIN 0x30e8
40#define IMX334_AGAIN_MIN 0
41#define IMX334_AGAIN_MAX 240
42#define IMX334_AGAIN_STEP 1
43#define IMX334_AGAIN_DEFAULT 0
44
45
46#define IMX334_REG_HOLD 0x3001
47
48
49#define IMX334_INCLK_RATE 24000000
50
51
52#define IMX334_LINK_FREQ 891000000
53#define IMX334_NUM_DATA_LANES 4
54
55#define IMX334_REG_MIN 0x00
56#define IMX334_REG_MAX 0xfffff
57
58
59
60
61
62
63struct imx334_reg {
64 u16 address;
65 u8 val;
66};
67
68
69
70
71
72
73struct imx334_reg_list {
74 u32 num_of_regs;
75 const struct imx334_reg *regs;
76};
77
78
79
80
81
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83
84
85
86
87
88
89
90
91struct imx334_mode {
92 u32 width;
93 u32 height;
94 u32 code;
95 u32 hblank;
96 u32 vblank;
97 u32 vblank_min;
98 u32 vblank_max;
99 u64 pclk;
100 u32 link_freq_idx;
101 struct imx334_reg_list reg_list;
102};
103
104
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122
123
124struct imx334 {
125 struct device *dev;
126 struct i2c_client *client;
127 struct v4l2_subdev sd;
128 struct media_pad pad;
129 struct gpio_desc *reset_gpio;
130 struct clk *inclk;
131 struct v4l2_ctrl_handler ctrl_handler;
132 struct v4l2_ctrl *link_freq_ctrl;
133 struct v4l2_ctrl *pclk_ctrl;
134 struct v4l2_ctrl *hblank_ctrl;
135 struct v4l2_ctrl *vblank_ctrl;
136 struct {
137 struct v4l2_ctrl *exp_ctrl;
138 struct v4l2_ctrl *again_ctrl;
139 };
140 u32 vblank;
141 const struct imx334_mode *cur_mode;
142 struct mutex mutex;
143 bool streaming;
144};
145
146static const s64 link_freq[] = {
147 IMX334_LINK_FREQ,
148};
149
150
151static const struct imx334_reg mode_3840x2160_regs[] = {
152 {0x3000, 0x01},
153 {0x3002, 0x00},
154 {0x3018, 0x04},
155 {0x37b0, 0x36},
156 {0x304c, 0x00},
157 {0x300c, 0x3b},
158 {0x300d, 0x2a},
159 {0x3034, 0x26},
160 {0x3035, 0x02},
161 {0x314c, 0x29},
162 {0x314d, 0x01},
163 {0x315a, 0x02},
164 {0x3168, 0xa0},
165 {0x316a, 0x7e},
166 {0x3288, 0x21},
167 {0x328a, 0x02},
168 {0x302c, 0x3c},
169 {0x302e, 0x00},
170 {0x302f, 0x0f},
171 {0x3076, 0x70},
172 {0x3077, 0x08},
173 {0x3090, 0x70},
174 {0x3091, 0x08},
175 {0x30d8, 0x20},
176 {0x30d9, 0x12},
177 {0x3308, 0x70},
178 {0x3309, 0x08},
179 {0x3414, 0x05},
180 {0x3416, 0x18},
181 {0x35ac, 0x0e},
182 {0x3648, 0x01},
183 {0x364a, 0x04},
184 {0x364c, 0x04},
185 {0x3678, 0x01},
186 {0x367c, 0x31},
187 {0x367e, 0x31},
188 {0x3708, 0x02},
189 {0x3714, 0x01},
190 {0x3715, 0x02},
191 {0x3716, 0x02},
192 {0x3717, 0x02},
193 {0x371c, 0x3d},
194 {0x371d, 0x3f},
195 {0x372c, 0x00},
196 {0x372d, 0x00},
197 {0x372e, 0x46},
198 {0x372f, 0x00},
199 {0x3730, 0x89},
200 {0x3731, 0x00},
201 {0x3732, 0x08},
202 {0x3733, 0x01},
203 {0x3734, 0xfe},
204 {0x3735, 0x05},
205 {0x375d, 0x00},
206 {0x375e, 0x00},
207 {0x375f, 0x61},
208 {0x3760, 0x06},
209 {0x3768, 0x1b},
210 {0x3769, 0x1b},
211 {0x376a, 0x1a},
212 {0x376b, 0x19},
213 {0x376c, 0x18},
214 {0x376d, 0x14},
215 {0x376e, 0x0f},
216 {0x3776, 0x00},
217 {0x3777, 0x00},
218 {0x3778, 0x46},
219 {0x3779, 0x00},
220 {0x377a, 0x08},
221 {0x377b, 0x01},
222 {0x377c, 0x45},
223 {0x377d, 0x01},
224 {0x377e, 0x23},
225 {0x377f, 0x02},
226 {0x3780, 0xd9},
227 {0x3781, 0x03},
228 {0x3782, 0xf5},
229 {0x3783, 0x06},
230 {0x3784, 0xa5},
231 {0x3788, 0x0f},
232 {0x378a, 0xd9},
233 {0x378b, 0x03},
234 {0x378c, 0xeb},
235 {0x378d, 0x05},
236 {0x378e, 0x87},
237 {0x378f, 0x06},
238 {0x3790, 0xf5},
239 {0x3792, 0x43},
240 {0x3794, 0x7a},
241 {0x3796, 0xa1},
242 {0x3e04, 0x0e},
243 {0x3a00, 0x01},
244};
245
246
247static const struct imx334_mode supported_mode = {
248 .width = 3840,
249 .height = 2160,
250 .hblank = 560,
251 .vblank = 2340,
252 .vblank_min = 90,
253 .vblank_max = 132840,
254 .pclk = 594000000,
255 .link_freq_idx = 0,
256 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
257 .reg_list = {
258 .num_of_regs = ARRAY_SIZE(mode_3840x2160_regs),
259 .regs = mode_3840x2160_regs,
260 },
261};
262
263
264
265
266
267
268
269static inline struct imx334 *to_imx334(struct v4l2_subdev *subdev)
270{
271 return container_of(subdev, struct imx334, sd);
272}
273
274
275
276
277
278
279
280
281
282
283
284
285static int imx334_read_reg(struct imx334 *imx334, u16 reg, u32 len, u32 *val)
286{
287 struct i2c_client *client = v4l2_get_subdevdata(&imx334->sd);
288 struct i2c_msg msgs[2] = {0};
289 u8 addr_buf[2] = {0};
290 u8 data_buf[4] = {0};
291 int ret;
292
293 if (WARN_ON(len > 4))
294 return -EINVAL;
295
296 put_unaligned_be16(reg, addr_buf);
297
298
299 msgs[0].addr = client->addr;
300 msgs[0].flags = 0;
301 msgs[0].len = ARRAY_SIZE(addr_buf);
302 msgs[0].buf = addr_buf;
303
304
305 msgs[1].addr = client->addr;
306 msgs[1].flags = I2C_M_RD;
307 msgs[1].len = len;
308 msgs[1].buf = data_buf;
309
310 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
311 if (ret != ARRAY_SIZE(msgs))
312 return -EIO;
313
314 *val = get_unaligned_le32(data_buf);
315
316 return 0;
317}
318
319
320
321
322
323
324
325
326
327
328
329
330static int imx334_write_reg(struct imx334 *imx334, u16 reg, u32 len, u32 val)
331{
332 struct i2c_client *client = v4l2_get_subdevdata(&imx334->sd);
333 u8 buf[6] = {0};
334
335 if (WARN_ON(len > 4))
336 return -EINVAL;
337
338 put_unaligned_be16(reg, buf);
339 put_unaligned_le32(val, buf + 2);
340 if (i2c_master_send(client, buf, len + 2) != len + 2)
341 return -EIO;
342
343 return 0;
344}
345
346
347
348
349
350
351
352
353
354static int imx334_write_regs(struct imx334 *imx334,
355 const struct imx334_reg *regs, u32 len)
356{
357 unsigned int i;
358 int ret;
359
360 for (i = 0; i < len; i++) {
361 ret = imx334_write_reg(imx334, regs[i].address, 1, regs[i].val);
362 if (ret)
363 return ret;
364 }
365
366 return 0;
367}
368
369
370
371
372
373
374
375
376static int imx334_update_controls(struct imx334 *imx334,
377 const struct imx334_mode *mode)
378{
379 int ret;
380
381 ret = __v4l2_ctrl_s_ctrl(imx334->link_freq_ctrl, mode->link_freq_idx);
382 if (ret)
383 return ret;
384
385 ret = __v4l2_ctrl_s_ctrl(imx334->hblank_ctrl, mode->hblank);
386 if (ret)
387 return ret;
388
389 return __v4l2_ctrl_modify_range(imx334->vblank_ctrl, mode->vblank_min,
390 mode->vblank_max, 1, mode->vblank);
391}
392
393
394
395
396
397
398
399
400
401static int imx334_update_exp_gain(struct imx334 *imx334, u32 exposure, u32 gain)
402{
403 u32 lpfr, shutter;
404 int ret;
405
406 lpfr = imx334->vblank + imx334->cur_mode->height;
407 shutter = lpfr - exposure;
408
409 dev_dbg(imx334->dev, "Set long exp %u analog gain %u sh0 %u lpfr %u",
410 exposure, gain, shutter, lpfr);
411
412 ret = imx334_write_reg(imx334, IMX334_REG_HOLD, 1, 1);
413 if (ret)
414 return ret;
415
416 ret = imx334_write_reg(imx334, IMX334_REG_LPFR, 3, lpfr);
417 if (ret)
418 goto error_release_group_hold;
419
420 ret = imx334_write_reg(imx334, IMX334_REG_SHUTTER, 3, shutter);
421 if (ret)
422 goto error_release_group_hold;
423
424 ret = imx334_write_reg(imx334, IMX334_REG_AGAIN, 1, gain);
425
426error_release_group_hold:
427 imx334_write_reg(imx334, IMX334_REG_HOLD, 1, 0);
428
429 return ret;
430}
431
432
433
434
435
436
437
438
439
440
441
442
443
444static int imx334_set_ctrl(struct v4l2_ctrl *ctrl)
445{
446 struct imx334 *imx334 =
447 container_of(ctrl->handler, struct imx334, ctrl_handler);
448 u32 analog_gain;
449 u32 exposure;
450 int ret;
451
452 switch (ctrl->id) {
453 case V4L2_CID_VBLANK:
454 imx334->vblank = imx334->vblank_ctrl->val;
455
456 dev_dbg(imx334->dev, "Received vblank %u, new lpfr %u",
457 imx334->vblank,
458 imx334->vblank + imx334->cur_mode->height);
459
460 ret = __v4l2_ctrl_modify_range(imx334->exp_ctrl,
461 IMX334_EXPOSURE_MIN,
462 imx334->vblank +
463 imx334->cur_mode->height -
464 IMX334_EXPOSURE_OFFSET,
465 1, IMX334_EXPOSURE_DEFAULT);
466 break;
467 case V4L2_CID_EXPOSURE:
468
469
470 if (!pm_runtime_get_if_in_use(imx334->dev))
471 return 0;
472
473 exposure = ctrl->val;
474 analog_gain = imx334->again_ctrl->val;
475
476 dev_dbg(imx334->dev, "Received exp %u analog gain %u",
477 exposure, analog_gain);
478
479 ret = imx334_update_exp_gain(imx334, exposure, analog_gain);
480
481 pm_runtime_put(imx334->dev);
482
483 break;
484 default:
485 dev_err(imx334->dev, "Invalid control %d", ctrl->id);
486 ret = -EINVAL;
487 }
488
489 return ret;
490}
491
492
493static const struct v4l2_ctrl_ops imx334_ctrl_ops = {
494 .s_ctrl = imx334_set_ctrl,
495};
496
497
498
499
500
501
502
503
504
505static int imx334_enum_mbus_code(struct v4l2_subdev *sd,
506 struct v4l2_subdev_pad_config *cfg,
507 struct v4l2_subdev_mbus_code_enum *code)
508{
509 if (code->index > 0)
510 return -EINVAL;
511
512 code->code = supported_mode.code;
513
514 return 0;
515}
516
517
518
519
520
521
522
523
524
525static int imx334_enum_frame_size(struct v4l2_subdev *sd,
526 struct v4l2_subdev_pad_config *cfg,
527 struct v4l2_subdev_frame_size_enum *fsize)
528{
529 if (fsize->index > 0)
530 return -EINVAL;
531
532 if (fsize->code != supported_mode.code)
533 return -EINVAL;
534
535 fsize->min_width = supported_mode.width;
536 fsize->max_width = fsize->min_width;
537 fsize->min_height = supported_mode.height;
538 fsize->max_height = fsize->min_height;
539
540 return 0;
541}
542
543
544
545
546
547
548
549
550static void imx334_fill_pad_format(struct imx334 *imx334,
551 const struct imx334_mode *mode,
552 struct v4l2_subdev_format *fmt)
553{
554 fmt->format.width = mode->width;
555 fmt->format.height = mode->height;
556 fmt->format.code = mode->code;
557 fmt->format.field = V4L2_FIELD_NONE;
558 fmt->format.colorspace = V4L2_COLORSPACE_RAW;
559 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
560 fmt->format.quantization = V4L2_QUANTIZATION_DEFAULT;
561 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
562}
563
564
565
566
567
568
569
570
571
572static int imx334_get_pad_format(struct v4l2_subdev *sd,
573 struct v4l2_subdev_pad_config *cfg,
574 struct v4l2_subdev_format *fmt)
575{
576 struct imx334 *imx334 = to_imx334(sd);
577
578 mutex_lock(&imx334->mutex);
579
580 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
581 struct v4l2_mbus_framefmt *framefmt;
582
583 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
584 fmt->format = *framefmt;
585 } else {
586 imx334_fill_pad_format(imx334, imx334->cur_mode, fmt);
587 }
588
589 mutex_unlock(&imx334->mutex);
590
591 return 0;
592}
593
594
595
596
597
598
599
600
601
602static int imx334_set_pad_format(struct v4l2_subdev *sd,
603 struct v4l2_subdev_pad_config *cfg,
604 struct v4l2_subdev_format *fmt)
605{
606 struct imx334 *imx334 = to_imx334(sd);
607 const struct imx334_mode *mode;
608 int ret = 0;
609
610 mutex_lock(&imx334->mutex);
611
612 mode = &supported_mode;
613 imx334_fill_pad_format(imx334, mode, fmt);
614
615 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
616 struct v4l2_mbus_framefmt *framefmt;
617
618 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
619 *framefmt = fmt->format;
620 } else {
621 ret = imx334_update_controls(imx334, mode);
622 if (!ret)
623 imx334->cur_mode = mode;
624 }
625
626 mutex_unlock(&imx334->mutex);
627
628 return ret;
629}
630
631
632
633
634
635
636
637
638static int imx334_init_pad_cfg(struct v4l2_subdev *sd,
639 struct v4l2_subdev_pad_config *cfg)
640{
641 struct imx334 *imx334 = to_imx334(sd);
642 struct v4l2_subdev_format fmt = { 0 };
643
644 fmt.which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
645 imx334_fill_pad_format(imx334, &supported_mode, &fmt);
646
647 return imx334_set_pad_format(sd, cfg, &fmt);
648}
649
650
651
652
653
654
655
656static int imx334_start_streaming(struct imx334 *imx334)
657{
658 const struct imx334_reg_list *reg_list;
659 int ret;
660
661
662 reg_list = &imx334->cur_mode->reg_list;
663 ret = imx334_write_regs(imx334, reg_list->regs,
664 reg_list->num_of_regs);
665 if (ret) {
666 dev_err(imx334->dev, "fail to write initial registers");
667 return ret;
668 }
669
670
671 ret = __v4l2_ctrl_handler_setup(imx334->sd.ctrl_handler);
672 if (ret) {
673 dev_err(imx334->dev, "fail to setup handler");
674 return ret;
675 }
676
677
678 ret = imx334_write_reg(imx334, IMX334_REG_MODE_SELECT,
679 1, IMX334_MODE_STREAMING);
680 if (ret) {
681 dev_err(imx334->dev, "fail to start streaming");
682 return ret;
683 }
684
685 return 0;
686}
687
688
689
690
691
692
693
694static int imx334_stop_streaming(struct imx334 *imx334)
695{
696 return imx334_write_reg(imx334, IMX334_REG_MODE_SELECT,
697 1, IMX334_MODE_STANDBY);
698}
699
700
701
702
703
704
705
706
707static int imx334_set_stream(struct v4l2_subdev *sd, int enable)
708{
709 struct imx334 *imx334 = to_imx334(sd);
710 int ret;
711
712 mutex_lock(&imx334->mutex);
713
714 if (imx334->streaming == enable) {
715 mutex_unlock(&imx334->mutex);
716 return 0;
717 }
718
719 if (enable) {
720 ret = pm_runtime_get_sync(imx334->dev);
721 if (ret)
722 goto error_power_off;
723
724 ret = imx334_start_streaming(imx334);
725 if (ret)
726 goto error_power_off;
727 } else {
728 imx334_stop_streaming(imx334);
729 pm_runtime_put(imx334->dev);
730 }
731
732 imx334->streaming = enable;
733
734 mutex_unlock(&imx334->mutex);
735
736 return 0;
737
738error_power_off:
739 pm_runtime_put(imx334->dev);
740 mutex_unlock(&imx334->mutex);
741
742 return ret;
743}
744
745
746
747
748
749
750
751static int imx334_detect(struct imx334 *imx334)
752{
753 int ret;
754 u32 val;
755
756 ret = imx334_read_reg(imx334, IMX334_REG_ID, 2, &val);
757 if (ret)
758 return ret;
759
760 if (val != IMX334_ID) {
761 dev_err(imx334->dev, "chip id mismatch: %x!=%x",
762 IMX334_ID, val);
763 return -ENXIO;
764 }
765
766 return 0;
767}
768
769
770
771
772
773
774
775static int imx334_parse_hw_config(struct imx334 *imx334)
776{
777 struct fwnode_handle *fwnode = dev_fwnode(imx334->dev);
778 struct v4l2_fwnode_endpoint bus_cfg = {
779 .bus_type = V4L2_MBUS_CSI2_DPHY
780 };
781 struct fwnode_handle *ep;
782 unsigned long rate;
783 int ret;
784 int i;
785
786 if (!fwnode)
787 return -ENXIO;
788
789
790 imx334->reset_gpio = devm_gpiod_get_optional(imx334->dev, "reset",
791 GPIOD_OUT_LOW);
792 if (IS_ERR(imx334->reset_gpio)) {
793 dev_err(imx334->dev, "failed to get reset gpio %ld",
794 PTR_ERR(imx334->reset_gpio));
795 return PTR_ERR(imx334->reset_gpio);
796 }
797
798
799 imx334->inclk = devm_clk_get(imx334->dev, NULL);
800 if (IS_ERR(imx334->inclk)) {
801 dev_err(imx334->dev, "could not get inclk");
802 return PTR_ERR(imx334->inclk);
803 }
804
805 rate = clk_get_rate(imx334->inclk);
806 if (rate != IMX334_INCLK_RATE) {
807 dev_err(imx334->dev, "inclk frequency mismatch");
808 return -EINVAL;
809 }
810
811 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
812 if (!ep)
813 return -ENXIO;
814
815 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
816 fwnode_handle_put(ep);
817 if (ret)
818 return ret;
819
820 if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX334_NUM_DATA_LANES) {
821 dev_err(imx334->dev,
822 "number of CSI2 data lanes %d is not supported",
823 bus_cfg.bus.mipi_csi2.num_data_lanes);
824 ret = -EINVAL;
825 goto done_endpoint_free;
826 }
827
828 if (!bus_cfg.nr_of_link_frequencies) {
829 dev_err(imx334->dev, "no link frequencies defined");
830 ret = -EINVAL;
831 goto done_endpoint_free;
832 }
833
834 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++)
835 if (bus_cfg.link_frequencies[i] == IMX334_LINK_FREQ)
836 goto done_endpoint_free;
837
838 ret = -EINVAL;
839
840done_endpoint_free:
841 v4l2_fwnode_endpoint_free(&bus_cfg);
842
843 return ret;
844}
845
846
847static const struct v4l2_subdev_video_ops imx334_video_ops = {
848 .s_stream = imx334_set_stream,
849};
850
851static const struct v4l2_subdev_pad_ops imx334_pad_ops = {
852 .init_cfg = imx334_init_pad_cfg,
853 .enum_mbus_code = imx334_enum_mbus_code,
854 .enum_frame_size = imx334_enum_frame_size,
855 .get_fmt = imx334_get_pad_format,
856 .set_fmt = imx334_set_pad_format,
857};
858
859static const struct v4l2_subdev_ops imx334_subdev_ops = {
860 .video = &imx334_video_ops,
861 .pad = &imx334_pad_ops,
862};
863
864
865
866
867
868
869
870static int imx334_power_on(struct device *dev)
871{
872 struct v4l2_subdev *sd = dev_get_drvdata(dev);
873 struct imx334 *imx334 = to_imx334(sd);
874 int ret;
875
876 gpiod_set_value_cansleep(imx334->reset_gpio, 1);
877
878 ret = clk_prepare_enable(imx334->inclk);
879 if (ret) {
880 dev_err(imx334->dev, "fail to enable inclk");
881 goto error_reset;
882 }
883
884 usleep_range(18000, 20000);
885
886 return 0;
887
888error_reset:
889 gpiod_set_value_cansleep(imx334->reset_gpio, 0);
890
891 return ret;
892}
893
894
895
896
897
898
899
900static int imx334_power_off(struct device *dev)
901{
902 struct v4l2_subdev *sd = dev_get_drvdata(dev);
903 struct imx334 *imx334 = to_imx334(sd);
904
905 gpiod_set_value_cansleep(imx334->reset_gpio, 0);
906
907 clk_disable_unprepare(imx334->inclk);
908
909 return 0;
910}
911
912
913
914
915
916
917
918static int imx334_init_controls(struct imx334 *imx334)
919{
920 struct v4l2_ctrl_handler *ctrl_hdlr = &imx334->ctrl_handler;
921 const struct imx334_mode *mode = imx334->cur_mode;
922 u32 lpfr;
923 int ret;
924
925 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 6);
926 if (ret)
927 return ret;
928
929
930 ctrl_hdlr->lock = &imx334->mutex;
931
932
933 lpfr = mode->vblank + mode->height;
934 imx334->exp_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
935 &imx334_ctrl_ops,
936 V4L2_CID_EXPOSURE,
937 IMX334_EXPOSURE_MIN,
938 lpfr - IMX334_EXPOSURE_OFFSET,
939 IMX334_EXPOSURE_STEP,
940 IMX334_EXPOSURE_DEFAULT);
941
942 imx334->again_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
943 &imx334_ctrl_ops,
944 V4L2_CID_ANALOGUE_GAIN,
945 IMX334_AGAIN_MIN,
946 IMX334_AGAIN_MAX,
947 IMX334_AGAIN_STEP,
948 IMX334_AGAIN_DEFAULT);
949
950 v4l2_ctrl_cluster(2, &imx334->exp_ctrl);
951
952 imx334->vblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
953 &imx334_ctrl_ops,
954 V4L2_CID_VBLANK,
955 mode->vblank_min,
956 mode->vblank_max,
957 1, mode->vblank);
958
959
960 imx334->pclk_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
961 &imx334_ctrl_ops,
962 V4L2_CID_PIXEL_RATE,
963 mode->pclk, mode->pclk,
964 1, mode->pclk);
965
966 imx334->link_freq_ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr,
967 &imx334_ctrl_ops,
968 V4L2_CID_LINK_FREQ,
969 ARRAY_SIZE(link_freq) -
970 1,
971 mode->link_freq_idx,
972 link_freq);
973 if (imx334->link_freq_ctrl)
974 imx334->link_freq_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
975
976 imx334->hblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
977 &imx334_ctrl_ops,
978 V4L2_CID_HBLANK,
979 IMX334_REG_MIN,
980 IMX334_REG_MAX,
981 1, mode->hblank);
982 if (imx334->hblank_ctrl)
983 imx334->hblank_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
984
985 if (ctrl_hdlr->error) {
986 dev_err(imx334->dev, "control init failed: %d",
987 ctrl_hdlr->error);
988 v4l2_ctrl_handler_free(ctrl_hdlr);
989 return ctrl_hdlr->error;
990 }
991
992 imx334->sd.ctrl_handler = ctrl_hdlr;
993
994 return 0;
995}
996
997
998
999
1000
1001
1002
1003static int imx334_probe(struct i2c_client *client)
1004{
1005 struct imx334 *imx334;
1006 int ret;
1007
1008 imx334 = devm_kzalloc(&client->dev, sizeof(*imx334), GFP_KERNEL);
1009 if (!imx334)
1010 return -ENOMEM;
1011
1012 imx334->dev = &client->dev;
1013
1014
1015 v4l2_i2c_subdev_init(&imx334->sd, client, &imx334_subdev_ops);
1016
1017 ret = imx334_parse_hw_config(imx334);
1018 if (ret) {
1019 dev_err(imx334->dev, "HW configuration is not supported");
1020 return ret;
1021 }
1022
1023 mutex_init(&imx334->mutex);
1024
1025 ret = imx334_power_on(imx334->dev);
1026 if (ret) {
1027 dev_err(imx334->dev, "failed to power-on the sensor");
1028 goto error_mutex_destroy;
1029 }
1030
1031
1032 ret = imx334_detect(imx334);
1033 if (ret) {
1034 dev_err(imx334->dev, "failed to find sensor: %d", ret);
1035 goto error_power_off;
1036 }
1037
1038
1039 imx334->cur_mode = &supported_mode;
1040 imx334->vblank = imx334->cur_mode->vblank;
1041
1042 ret = imx334_init_controls(imx334);
1043 if (ret) {
1044 dev_err(imx334->dev, "failed to init controls: %d", ret);
1045 goto error_power_off;
1046 }
1047
1048
1049 imx334->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1050 imx334->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1051
1052
1053 imx334->pad.flags = MEDIA_PAD_FL_SOURCE;
1054 ret = media_entity_pads_init(&imx334->sd.entity, 1, &imx334->pad);
1055 if (ret) {
1056 dev_err(imx334->dev, "failed to init entity pads: %d", ret);
1057 goto error_handler_free;
1058 }
1059
1060 ret = v4l2_async_register_subdev_sensor(&imx334->sd);
1061 if (ret < 0) {
1062 dev_err(imx334->dev,
1063 "failed to register async subdev: %d", ret);
1064 goto error_media_entity;
1065 }
1066
1067 pm_runtime_set_active(imx334->dev);
1068 pm_runtime_enable(imx334->dev);
1069 pm_runtime_idle(imx334->dev);
1070
1071 return 0;
1072
1073error_media_entity:
1074 media_entity_cleanup(&imx334->sd.entity);
1075error_handler_free:
1076 v4l2_ctrl_handler_free(imx334->sd.ctrl_handler);
1077error_power_off:
1078 imx334_power_off(imx334->dev);
1079error_mutex_destroy:
1080 mutex_destroy(&imx334->mutex);
1081
1082 return ret;
1083}
1084
1085
1086
1087
1088
1089
1090
1091static int imx334_remove(struct i2c_client *client)
1092{
1093 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1094 struct imx334 *imx334 = to_imx334(sd);
1095
1096 v4l2_async_unregister_subdev(sd);
1097 media_entity_cleanup(&sd->entity);
1098 v4l2_ctrl_handler_free(sd->ctrl_handler);
1099
1100 pm_runtime_disable(&client->dev);
1101 pm_runtime_suspended(&client->dev);
1102
1103 mutex_destroy(&imx334->mutex);
1104
1105 return 0;
1106}
1107
1108static const struct dev_pm_ops imx334_pm_ops = {
1109 SET_RUNTIME_PM_OPS(imx334_power_off, imx334_power_on, NULL)
1110};
1111
1112static const struct of_device_id imx334_of_match[] = {
1113 { .compatible = "sony,imx334" },
1114 { }
1115};
1116
1117MODULE_DEVICE_TABLE(of, imx334_of_match);
1118
1119static struct i2c_driver imx334_driver = {
1120 .probe_new = imx334_probe,
1121 .remove = imx334_remove,
1122 .driver = {
1123 .name = "imx334",
1124 .pm = &imx334_pm_ops,
1125 .of_match_table = imx334_of_match,
1126 },
1127};
1128
1129module_i2c_driver(imx334_driver);
1130
1131MODULE_DESCRIPTION("Sony imx334 sensor driver");
1132MODULE_LICENSE("GPL");
1133