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10#include <linux/clk.h>
11#include <linux/completion.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <linux/kernel.h>
16#include <linux/mutex.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <media/media-entity.h>
20#include <media/v4l2-device.h>
21#include <media/v4l2-subdev.h>
22
23#include "camss-ispif.h"
24#include "camss.h"
25
26#define MSM_ISPIF_NAME "msm_ispif"
27
28#define ISPIF_RST_CMD_0 0x008
29#define ISPIF_RST_CMD_1 0x00c
30#define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0)
31#define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1)
32#define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2)
33#define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST (1 << 3)
34#define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST (1 << 4)
35#define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST (1 << 5)
36#define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST (1 << 6)
37#define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST (1 << 7)
38#define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST (1 << 8)
39#define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST (1 << 9)
40#define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST (1 << 10)
41#define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST (1 << 11)
42#define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST (1 << 12)
43#define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST (1 << 16)
44#define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST (1 << 17)
45#define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST (1 << 18)
46#define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST (1 << 19)
47#define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c
48#define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))
49#define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6)
50#define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))
51#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE 0x00001249
52#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK 0x00001fff
53#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE 0x02492000
54#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK 0x03ffe000
55#define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))
56#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE 0x00001249
57#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK 0x00001fff
58#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE 0x02492000
59#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK 0x03ffe000
60#define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))
61#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE 0x00001249
62#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK 0x00001fff
63#define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))
64#define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW (1 << 12)
65#define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW (1 << 25)
66#define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))
67#define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW (1 << 12)
68#define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW (1 << 25)
69#define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))
70#define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW (1 << 12)
71#define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))
72#define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m))
73#define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m))
74#define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m))
75#define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m))
76#define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m))
77#define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) \
78 (0x254 + 0x200 * (m) + 0x4 * (n))
79#define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) \
80 (0x264 + 0x200 * (m) + 0x4 * (n))
81
82#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n) \
83 (0x270 + 0x200 * (m) + 0x4 * (n))
84#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n) \
85 (0x27c + 0x200 * (m) + 0x4 * (n))
86#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c) \
87 (1 << ((cid % 8) * 4))
88#define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) \
89 (0x2c0 + 0x200 * (m) + 0x4 * (n))
90#define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) \
91 (0x2d0 + 0x200 * (m) + 0x4 * (n))
92
93#define CSI_PIX_CLK_MUX_SEL 0x000
94#define CSI_RDI_CLK_MUX_SEL 0x008
95
96#define ISPIF_TIMEOUT_SLEEP_US 1000
97#define ISPIF_TIMEOUT_ALL_US 1000000
98#define ISPIF_RESET_TIMEOUT_MS 500
99
100enum ispif_intf_cmd {
101 CMD_DISABLE_FRAME_BOUNDARY = 0x0,
102 CMD_ENABLE_FRAME_BOUNDARY = 0x1,
103 CMD_DISABLE_IMMEDIATELY = 0x2,
104 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa,
105 CMD_ALL_NO_CHANGE = 0xffffffff,
106};
107
108static const u32 ispif_formats_8x16[] = {
109 MEDIA_BUS_FMT_UYVY8_2X8,
110 MEDIA_BUS_FMT_VYUY8_2X8,
111 MEDIA_BUS_FMT_YUYV8_2X8,
112 MEDIA_BUS_FMT_YVYU8_2X8,
113 MEDIA_BUS_FMT_SBGGR8_1X8,
114 MEDIA_BUS_FMT_SGBRG8_1X8,
115 MEDIA_BUS_FMT_SGRBG8_1X8,
116 MEDIA_BUS_FMT_SRGGB8_1X8,
117 MEDIA_BUS_FMT_SBGGR10_1X10,
118 MEDIA_BUS_FMT_SGBRG10_1X10,
119 MEDIA_BUS_FMT_SGRBG10_1X10,
120 MEDIA_BUS_FMT_SRGGB10_1X10,
121 MEDIA_BUS_FMT_SBGGR12_1X12,
122 MEDIA_BUS_FMT_SGBRG12_1X12,
123 MEDIA_BUS_FMT_SGRBG12_1X12,
124 MEDIA_BUS_FMT_SRGGB12_1X12,
125 MEDIA_BUS_FMT_Y10_1X10,
126};
127
128static const u32 ispif_formats_8x96[] = {
129 MEDIA_BUS_FMT_UYVY8_2X8,
130 MEDIA_BUS_FMT_VYUY8_2X8,
131 MEDIA_BUS_FMT_YUYV8_2X8,
132 MEDIA_BUS_FMT_YVYU8_2X8,
133 MEDIA_BUS_FMT_SBGGR8_1X8,
134 MEDIA_BUS_FMT_SGBRG8_1X8,
135 MEDIA_BUS_FMT_SGRBG8_1X8,
136 MEDIA_BUS_FMT_SRGGB8_1X8,
137 MEDIA_BUS_FMT_SBGGR10_1X10,
138 MEDIA_BUS_FMT_SGBRG10_1X10,
139 MEDIA_BUS_FMT_SGRBG10_1X10,
140 MEDIA_BUS_FMT_SRGGB10_1X10,
141 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
142 MEDIA_BUS_FMT_SBGGR12_1X12,
143 MEDIA_BUS_FMT_SGBRG12_1X12,
144 MEDIA_BUS_FMT_SGRBG12_1X12,
145 MEDIA_BUS_FMT_SRGGB12_1X12,
146 MEDIA_BUS_FMT_SBGGR14_1X14,
147 MEDIA_BUS_FMT_SGBRG14_1X14,
148 MEDIA_BUS_FMT_SGRBG14_1X14,
149 MEDIA_BUS_FMT_SRGGB14_1X14,
150 MEDIA_BUS_FMT_Y10_1X10,
151 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE,
152};
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159
160
161static irqreturn_t ispif_isr_8x96(int irq, void *dev)
162{
163 struct ispif_device *ispif = dev;
164 struct camss *camss = ispif->camss;
165 u32 value0, value1, value2, value3, value4, value5;
166
167 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
168 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
169 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
170 value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1));
171 value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1));
172 value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1));
173
174 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
175 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
176 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
177 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));
178 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));
179 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));
180
181 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
182
183 if ((value0 >> 27) & 0x1)
184 complete(&ispif->reset_complete[0]);
185
186 if ((value3 >> 27) & 0x1)
187 complete(&ispif->reset_complete[1]);
188
189 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
190 dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");
191
192 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
193 dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");
194
195 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
196 dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");
197
198 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
199 dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");
200
201 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
202 dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");
203
204 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
205 dev_err_ratelimited(camss->dev, "VFE1 pix0 overflow\n");
206
207 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
208 dev_err_ratelimited(camss->dev, "VFE1 rdi0 overflow\n");
209
210 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
211 dev_err_ratelimited(camss->dev, "VFE1 pix1 overflow\n");
212
213 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
214 dev_err_ratelimited(camss->dev, "VFE1 rdi1 overflow\n");
215
216 if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
217 dev_err_ratelimited(camss->dev, "VFE1 rdi2 overflow\n");
218
219 return IRQ_HANDLED;
220}
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227
228
229static irqreturn_t ispif_isr_8x16(int irq, void *dev)
230{
231 struct ispif_device *ispif = dev;
232 struct camss *camss = ispif->camss;
233 u32 value0, value1, value2;
234
235 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
236 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
237 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
238
239 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
240 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
241 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
242
243 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
244
245 if ((value0 >> 27) & 0x1)
246 complete(&ispif->reset_complete[0]);
247
248 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
249 dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");
250
251 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
252 dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");
253
254 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
255 dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");
256
257 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
258 dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");
259
260 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
261 dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");
262
263 return IRQ_HANDLED;
264}
265
266static int ispif_vfe_reset(struct ispif_device *ispif, u8 vfe_id)
267{
268 struct camss *camss = ispif->camss;
269
270 unsigned long time;
271 u32 val;
272
273 if (vfe_id > (camss->vfe_num - 1)) {
274 dev_err(camss->dev,
275 "Error: asked reset for invalid VFE%d\n", vfe_id);
276 return -ENOENT;
277 }
278
279 reinit_completion(&ispif->reset_complete[vfe_id]);
280
281 val = ISPIF_RST_CMD_0_STROBED_RST_EN |
282 ISPIF_RST_CMD_0_MISC_LOGIC_RST |
283 ISPIF_RST_CMD_0_SW_REG_RST |
284 ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST |
285 ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST |
286 ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST |
287 ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST |
288 ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST |
289 ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST |
290 ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST |
291 ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST |
292 ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST |
293 ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST |
294 ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST |
295 ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST |
296 ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST |
297 ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST;
298
299 if (vfe_id == 1)
300 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_1);
301 else
302 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
303
304 time = wait_for_completion_timeout(&ispif->reset_complete[vfe_id],
305 msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS));
306 if (!time) {
307 dev_err(camss->dev,
308 "ISPIF for VFE%d reset timeout\n", vfe_id);
309 return -EIO;
310 }
311
312 return 0;
313}
314
315
316
317
318
319
320
321static int ispif_reset(struct ispif_device *ispif, u8 vfe_id)
322{
323 struct camss *camss = ispif->camss;
324 int ret;
325
326 ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE0);
327 if (ret < 0)
328 return ret;
329
330 ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE1);
331 if (ret < 0)
332 return ret;
333
334 ret = camss_enable_clocks(ispif->nclocks_for_reset,
335 ispif->clock_for_reset,
336 camss->dev);
337 if (ret < 0)
338 return ret;
339
340 ret = ispif_vfe_reset(ispif, vfe_id);
341 if (ret)
342 dev_dbg(camss->dev, "ISPIF Reset failed\n");
343
344 camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset);
345
346 camss_pm_domain_off(camss, PM_DOMAIN_VFE0);
347 camss_pm_domain_off(camss, PM_DOMAIN_VFE1);
348
349 return ret;
350}
351
352
353
354
355
356
357
358
359static int ispif_set_power(struct v4l2_subdev *sd, int on)
360{
361 struct ispif_line *line = v4l2_get_subdevdata(sd);
362 struct ispif_device *ispif = line->ispif;
363 struct device *dev = ispif->camss->dev;
364 int ret = 0;
365
366 mutex_lock(&ispif->power_lock);
367
368 if (on) {
369 if (ispif->power_count) {
370
371 ispif->power_count++;
372 goto exit;
373 }
374
375 ret = pm_runtime_get_sync(dev);
376 if (ret < 0) {
377 pm_runtime_put_sync(dev);
378 goto exit;
379 }
380
381 ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev);
382 if (ret < 0) {
383 pm_runtime_put_sync(dev);
384 goto exit;
385 }
386
387 ret = ispif_reset(ispif, line->vfe_id);
388 if (ret < 0) {
389 pm_runtime_put_sync(dev);
390 camss_disable_clocks(ispif->nclocks, ispif->clock);
391 goto exit;
392 }
393
394 ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE;
395 ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE;
396
397 ispif->power_count++;
398 } else {
399 if (ispif->power_count == 0) {
400 dev_err(dev, "ispif power off on power_count == 0\n");
401 goto exit;
402 } else if (ispif->power_count == 1) {
403 camss_disable_clocks(ispif->nclocks, ispif->clock);
404 pm_runtime_put_sync(dev);
405 }
406
407 ispif->power_count--;
408 }
409
410exit:
411 mutex_unlock(&ispif->power_lock);
412
413 return ret;
414}
415
416
417
418
419
420
421
422
423
424static void ispif_select_clk_mux(struct ispif_device *ispif,
425 enum ispif_intf intf, u8 csid,
426 u8 vfe, u8 enable)
427{
428 u32 val;
429
430 switch (intf) {
431 case PIX0:
432 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
433 val &= ~(0xf << (vfe * 8));
434 if (enable)
435 val |= (csid << (vfe * 8));
436 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
437 break;
438
439 case RDI0:
440 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
441 val &= ~(0xf << (vfe * 12));
442 if (enable)
443 val |= (csid << (vfe * 12));
444 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
445 break;
446
447 case PIX1:
448 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
449 val &= ~(0xf << (4 + (vfe * 8)));
450 if (enable)
451 val |= (csid << (4 + (vfe * 8)));
452 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
453 break;
454
455 case RDI1:
456 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
457 val &= ~(0xf << (4 + (vfe * 12)));
458 if (enable)
459 val |= (csid << (4 + (vfe * 12)));
460 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
461 break;
462
463 case RDI2:
464 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
465 val &= ~(0xf << (8 + (vfe * 12)));
466 if (enable)
467 val |= (csid << (8 + (vfe * 12)));
468 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
469 break;
470 }
471
472 mb();
473}
474
475
476
477
478
479
480
481
482
483static int ispif_validate_intf_status(struct ispif_device *ispif,
484 enum ispif_intf intf, u8 vfe)
485{
486 int ret = 0;
487 u32 val = 0;
488
489 switch (intf) {
490 case PIX0:
491 val = readl_relaxed(ispif->base +
492 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));
493 break;
494 case RDI0:
495 val = readl_relaxed(ispif->base +
496 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));
497 break;
498 case PIX1:
499 val = readl_relaxed(ispif->base +
500 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));
501 break;
502 case RDI1:
503 val = readl_relaxed(ispif->base +
504 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));
505 break;
506 case RDI2:
507 val = readl_relaxed(ispif->base +
508 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));
509 break;
510 }
511
512 if ((val & 0xf) != 0xf) {
513 dev_err(ispif->camss->dev, "%s: ispif is busy: 0x%x\n",
514 __func__, val);
515 ret = -EBUSY;
516 }
517
518 return ret;
519}
520
521
522
523
524
525
526
527
528
529static int ispif_wait_for_stop(struct ispif_device *ispif,
530 enum ispif_intf intf, u8 vfe)
531{
532 u32 addr = 0;
533 u32 stop_flag = 0;
534 int ret;
535
536 switch (intf) {
537 case PIX0:
538 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0);
539 break;
540 case RDI0:
541 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0);
542 break;
543 case PIX1:
544 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1);
545 break;
546 case RDI1:
547 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1);
548 break;
549 case RDI2:
550 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2);
551 break;
552 }
553
554 ret = readl_poll_timeout(ispif->base + addr,
555 stop_flag,
556 (stop_flag & 0xf) == 0xf,
557 ISPIF_TIMEOUT_SLEEP_US,
558 ISPIF_TIMEOUT_ALL_US);
559 if (ret < 0)
560 dev_err(ispif->camss->dev, "%s: ispif stop timeout\n",
561 __func__);
562
563 return ret;
564}
565
566
567
568
569
570
571
572
573
574static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf,
575 u8 csid, u8 vfe, u8 enable)
576{
577 u32 val;
578
579 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
580 switch (intf) {
581 case PIX0:
582 val &= ~(BIT(1) | BIT(0));
583 if (enable)
584 val |= csid;
585 break;
586 case RDI0:
587 val &= ~(BIT(5) | BIT(4));
588 if (enable)
589 val |= (csid << 4);
590 break;
591 case PIX1:
592 val &= ~(BIT(9) | BIT(8));
593 if (enable)
594 val |= (csid << 8);
595 break;
596 case RDI1:
597 val &= ~(BIT(13) | BIT(12));
598 if (enable)
599 val |= (csid << 12);
600 break;
601 case RDI2:
602 val &= ~(BIT(21) | BIT(20));
603 if (enable)
604 val |= (csid << 20);
605 break;
606 }
607
608 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
609}
610
611
612
613
614
615
616
617
618
619static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf,
620 u8 cid, u8 vfe, u8 enable)
621{
622 u32 cid_mask = 1 << cid;
623 u32 addr = 0;
624 u32 val;
625
626 switch (intf) {
627 case PIX0:
628 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);
629 break;
630 case RDI0:
631 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);
632 break;
633 case PIX1:
634 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);
635 break;
636 case RDI1:
637 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);
638 break;
639 case RDI2:
640 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);
641 break;
642 }
643
644 val = readl_relaxed(ispif->base + addr);
645 if (enable)
646 val |= cid_mask;
647 else
648 val &= ~cid_mask;
649
650 writel(val, ispif->base + addr);
651}
652
653
654
655
656
657
658
659
660static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf,
661 u8 vfe, u8 enable)
662{
663 u32 val;
664
665 switch (intf) {
666 case PIX0:
667 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
668 val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK;
669 if (enable)
670 val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE;
671 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
672 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,
673 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
674 break;
675 case RDI0:
676 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
677 val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK;
678 if (enable)
679 val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE;
680 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
681 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,
682 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
683 break;
684 case PIX1:
685 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
686 val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK;
687 if (enable)
688 val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE;
689 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
690 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,
691 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
692 break;
693 case RDI1:
694 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
695 val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK;
696 if (enable)
697 val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE;
698 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
699 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,
700 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
701 break;
702 case RDI2:
703 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
704 val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK;
705 if (enable)
706 val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE;
707 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
708 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,
709 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));
710 break;
711 }
712
713 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
714}
715
716
717
718
719
720
721
722
723
724
725static void ispif_config_pack(struct ispif_device *ispif, u32 code,
726 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)
727{
728 u32 addr, val;
729
730 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE &&
731 code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE)
732 return;
733
734 switch (intf) {
735 case RDI0:
736 if (cid < 8)
737 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);
738 else
739 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);
740 break;
741 case RDI1:
742 if (cid < 8)
743 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);
744 else
745 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);
746 break;
747 case RDI2:
748 if (cid < 8)
749 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);
750 else
751 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);
752 break;
753 default:
754 return;
755 }
756
757 if (enable)
758 val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid);
759 else
760 val = 0;
761
762 writel_relaxed(val, ispif->base + addr);
763}
764
765
766
767
768
769
770
771
772
773static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd,
774 enum ispif_intf intf, u8 vfe, u8 vc)
775{
776 u32 *val;
777
778 if (intf == RDI2) {
779 val = &ispif->intf_cmd[vfe].cmd_1;
780 *val &= ~(0x3 << (vc * 2 + 8));
781 *val |= (cmd << (vc * 2 + 8));
782 wmb();
783 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
784 wmb();
785 } else {
786 val = &ispif->intf_cmd[vfe].cmd_0;
787 *val &= ~(0x3 << (vc * 2 + intf * 8));
788 *val |= (cmd << (vc * 2 + intf * 8));
789 wmb();
790 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
791 wmb();
792 }
793}
794
795
796
797
798
799
800
801
802
803
804static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
805{
806 struct ispif_line *line = v4l2_get_subdevdata(sd);
807 struct ispif_device *ispif = line->ispif;
808 struct camss *camss = ispif->camss;
809 enum ispif_intf intf = line->interface;
810 u8 csid = line->csid_id;
811 u8 vfe = line->vfe_id;
812 u8 vc = 0;
813 u8 cid = vc * 4;
814 int ret;
815
816 if (enable) {
817 if (!media_entity_remote_pad(&line->pads[MSM_ISPIF_PAD_SINK]))
818 return -ENOLINK;
819
820
821
822 mutex_lock(&ispif->config_lock);
823 ispif_select_clk_mux(ispif, intf, csid, vfe, 1);
824
825 ret = ispif_validate_intf_status(ispif, intf, vfe);
826 if (ret < 0) {
827 mutex_unlock(&ispif->config_lock);
828 return ret;
829 }
830
831 ispif_select_csid(ispif, intf, csid, vfe, 1);
832 ispif_select_cid(ispif, intf, cid, vfe, 1);
833 ispif_config_irq(ispif, intf, vfe, 1);
834 if (camss->version == CAMSS_8x96 ||
835 camss->version == CAMSS_660)
836 ispif_config_pack(ispif,
837 line->fmt[MSM_ISPIF_PAD_SINK].code,
838 intf, cid, vfe, 1);
839 ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,
840 intf, vfe, vc);
841 } else {
842 mutex_lock(&ispif->config_lock);
843 ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY,
844 intf, vfe, vc);
845 mutex_unlock(&ispif->config_lock);
846
847 ret = ispif_wait_for_stop(ispif, intf, vfe);
848 if (ret < 0)
849 return ret;
850
851 mutex_lock(&ispif->config_lock);
852 if (camss->version == CAMSS_8x96 ||
853 camss->version == CAMSS_660)
854 ispif_config_pack(ispif,
855 line->fmt[MSM_ISPIF_PAD_SINK].code,
856 intf, cid, vfe, 0);
857 ispif_config_irq(ispif, intf, vfe, 0);
858 ispif_select_cid(ispif, intf, cid, vfe, 0);
859 ispif_select_csid(ispif, intf, csid, vfe, 0);
860 ispif_select_clk_mux(ispif, intf, csid, vfe, 0);
861 }
862
863 mutex_unlock(&ispif->config_lock);
864
865 return 0;
866}
867
868
869
870
871
872
873
874
875
876
877static struct v4l2_mbus_framefmt *
878__ispif_get_format(struct ispif_line *line,
879 struct v4l2_subdev_pad_config *cfg,
880 unsigned int pad,
881 enum v4l2_subdev_format_whence which)
882{
883 if (which == V4L2_SUBDEV_FORMAT_TRY)
884 return v4l2_subdev_get_try_format(&line->subdev, cfg, pad);
885
886 return &line->fmt[pad];
887}
888
889
890
891
892
893
894
895
896
897static void ispif_try_format(struct ispif_line *line,
898 struct v4l2_subdev_pad_config *cfg,
899 unsigned int pad,
900 struct v4l2_mbus_framefmt *fmt,
901 enum v4l2_subdev_format_whence which)
902{
903 unsigned int i;
904
905 switch (pad) {
906 case MSM_ISPIF_PAD_SINK:
907
908
909 for (i = 0; i < line->nformats; i++)
910 if (fmt->code == line->formats[i])
911 break;
912
913
914 if (i >= line->nformats)
915 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
916
917 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
918 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
919
920 fmt->field = V4L2_FIELD_NONE;
921 fmt->colorspace = V4L2_COLORSPACE_SRGB;
922
923 break;
924
925 case MSM_ISPIF_PAD_SRC:
926
927
928 *fmt = *__ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK,
929 which);
930
931 break;
932 }
933
934 fmt->colorspace = V4L2_COLORSPACE_SRGB;
935}
936
937
938
939
940
941
942
943
944static int ispif_enum_mbus_code(struct v4l2_subdev *sd,
945 struct v4l2_subdev_pad_config *cfg,
946 struct v4l2_subdev_mbus_code_enum *code)
947{
948 struct ispif_line *line = v4l2_get_subdevdata(sd);
949 struct v4l2_mbus_framefmt *format;
950
951 if (code->pad == MSM_ISPIF_PAD_SINK) {
952 if (code->index >= line->nformats)
953 return -EINVAL;
954
955 code->code = line->formats[code->index];
956 } else {
957 if (code->index > 0)
958 return -EINVAL;
959
960 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK,
961 code->which);
962
963 code->code = format->code;
964 }
965
966 return 0;
967}
968
969
970
971
972
973
974
975
976static int ispif_enum_frame_size(struct v4l2_subdev *sd,
977 struct v4l2_subdev_pad_config *cfg,
978 struct v4l2_subdev_frame_size_enum *fse)
979{
980 struct ispif_line *line = v4l2_get_subdevdata(sd);
981 struct v4l2_mbus_framefmt format;
982
983 if (fse->index != 0)
984 return -EINVAL;
985
986 format.code = fse->code;
987 format.width = 1;
988 format.height = 1;
989 ispif_try_format(line, cfg, fse->pad, &format, fse->which);
990 fse->min_width = format.width;
991 fse->min_height = format.height;
992
993 if (format.code != fse->code)
994 return -EINVAL;
995
996 format.code = fse->code;
997 format.width = -1;
998 format.height = -1;
999 ispif_try_format(line, cfg, fse->pad, &format, fse->which);
1000 fse->max_width = format.width;
1001 fse->max_height = format.height;
1002
1003 return 0;
1004}
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014static int ispif_get_format(struct v4l2_subdev *sd,
1015 struct v4l2_subdev_pad_config *cfg,
1016 struct v4l2_subdev_format *fmt)
1017{
1018 struct ispif_line *line = v4l2_get_subdevdata(sd);
1019 struct v4l2_mbus_framefmt *format;
1020
1021 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which);
1022 if (format == NULL)
1023 return -EINVAL;
1024
1025 fmt->format = *format;
1026
1027 return 0;
1028}
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038static int ispif_set_format(struct v4l2_subdev *sd,
1039 struct v4l2_subdev_pad_config *cfg,
1040 struct v4l2_subdev_format *fmt)
1041{
1042 struct ispif_line *line = v4l2_get_subdevdata(sd);
1043 struct v4l2_mbus_framefmt *format;
1044
1045 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which);
1046 if (format == NULL)
1047 return -EINVAL;
1048
1049 ispif_try_format(line, cfg, fmt->pad, &fmt->format, fmt->which);
1050 *format = fmt->format;
1051
1052
1053 if (fmt->pad == MSM_ISPIF_PAD_SINK) {
1054 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SRC,
1055 fmt->which);
1056
1057 *format = fmt->format;
1058 ispif_try_format(line, cfg, MSM_ISPIF_PAD_SRC, format,
1059 fmt->which);
1060 }
1061
1062 return 0;
1063}
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1075{
1076 struct v4l2_subdev_format format = {
1077 .pad = MSM_ISPIF_PAD_SINK,
1078 .which = fh ? V4L2_SUBDEV_FORMAT_TRY :
1079 V4L2_SUBDEV_FORMAT_ACTIVE,
1080 .format = {
1081 .code = MEDIA_BUS_FMT_UYVY8_2X8,
1082 .width = 1920,
1083 .height = 1080
1084 }
1085 };
1086
1087 return ispif_set_format(sd, fh ? fh->pad : NULL, &format);
1088}
1089
1090
1091
1092
1093
1094
1095
1096
1097int msm_ispif_subdev_init(struct camss *camss,
1098 const struct resources_ispif *res)
1099{
1100 struct device *dev = camss->dev;
1101 struct ispif_device *ispif = camss->ispif;
1102 struct platform_device *pdev = to_platform_device(dev);
1103 struct resource *r;
1104 int i;
1105 int ret;
1106
1107 if (!camss->ispif)
1108 return 0;
1109
1110 ispif->camss = camss;
1111
1112
1113 if (camss->version == CAMSS_8x16)
1114 ispif->line_num = 2;
1115 else if (camss->version == CAMSS_8x96 ||
1116 camss->version == CAMSS_660)
1117 ispif->line_num = 4;
1118 else
1119 return -EINVAL;
1120
1121 ispif->line = devm_kcalloc(dev, ispif->line_num,
1122 sizeof(*ispif->line), GFP_KERNEL);
1123 if (!ispif->line)
1124 return -ENOMEM;
1125
1126 for (i = 0; i < ispif->line_num; i++) {
1127 ispif->line[i].ispif = ispif;
1128 ispif->line[i].id = i;
1129
1130 if (camss->version == CAMSS_8x16) {
1131 ispif->line[i].formats = ispif_formats_8x16;
1132 ispif->line[i].nformats =
1133 ARRAY_SIZE(ispif_formats_8x16);
1134 } else if (camss->version == CAMSS_8x96 ||
1135 camss->version == CAMSS_660) {
1136 ispif->line[i].formats = ispif_formats_8x96;
1137 ispif->line[i].nformats =
1138 ARRAY_SIZE(ispif_formats_8x96);
1139 } else {
1140 return -EINVAL;
1141 }
1142 }
1143
1144
1145
1146 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]);
1147 ispif->base = devm_ioremap_resource(dev, r);
1148 if (IS_ERR(ispif->base))
1149 return PTR_ERR(ispif->base);
1150
1151 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]);
1152 ispif->base_clk_mux = devm_ioremap_resource(dev, r);
1153 if (IS_ERR(ispif->base_clk_mux))
1154 return PTR_ERR(ispif->base_clk_mux);
1155
1156
1157
1158 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res->interrupt);
1159
1160 if (!r) {
1161 dev_err(dev, "missing IRQ\n");
1162 return -EINVAL;
1163 }
1164
1165 ispif->irq = r->start;
1166 snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s",
1167 dev_name(dev), MSM_ISPIF_NAME);
1168 if (camss->version == CAMSS_8x16)
1169 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16,
1170 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1171 else if (camss->version == CAMSS_8x96 ||
1172 camss->version == CAMSS_660)
1173 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96,
1174 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1175 else
1176 ret = -EINVAL;
1177
1178 if (ret < 0) {
1179 dev_err(dev, "request_irq failed: %d\n", ret);
1180 return ret;
1181 }
1182
1183
1184
1185 ispif->nclocks = 0;
1186 while (res->clock[ispif->nclocks])
1187 ispif->nclocks++;
1188
1189 ispif->clock = devm_kcalloc(dev,
1190 ispif->nclocks, sizeof(*ispif->clock),
1191 GFP_KERNEL);
1192 if (!ispif->clock)
1193 return -ENOMEM;
1194
1195 for (i = 0; i < ispif->nclocks; i++) {
1196 struct camss_clock *clock = &ispif->clock[i];
1197
1198 clock->clk = devm_clk_get(dev, res->clock[i]);
1199 if (IS_ERR(clock->clk))
1200 return PTR_ERR(clock->clk);
1201
1202 clock->freq = NULL;
1203 clock->nfreqs = 0;
1204 }
1205
1206 ispif->nclocks_for_reset = 0;
1207 while (res->clock_for_reset[ispif->nclocks_for_reset])
1208 ispif->nclocks_for_reset++;
1209
1210 ispif->clock_for_reset = devm_kcalloc(dev,
1211 ispif->nclocks_for_reset,
1212 sizeof(*ispif->clock_for_reset),
1213 GFP_KERNEL);
1214 if (!ispif->clock_for_reset)
1215 return -ENOMEM;
1216
1217 for (i = 0; i < ispif->nclocks_for_reset; i++) {
1218 struct camss_clock *clock = &ispif->clock_for_reset[i];
1219
1220 clock->clk = devm_clk_get(dev, res->clock_for_reset[i]);
1221 if (IS_ERR(clock->clk))
1222 return PTR_ERR(clock->clk);
1223
1224 clock->freq = NULL;
1225 clock->nfreqs = 0;
1226 }
1227
1228 mutex_init(&ispif->power_lock);
1229 ispif->power_count = 0;
1230
1231 mutex_init(&ispif->config_lock);
1232
1233 for (i = 0; i < MSM_ISPIF_VFE_NUM; i++)
1234 init_completion(&ispif->reset_complete[i]);
1235
1236 return 0;
1237}
1238
1239
1240
1241
1242
1243
1244
1245static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id)
1246{
1247 switch (line_id) {
1248 case (VFE_LINE_RDI0):
1249 return RDI0;
1250 case (VFE_LINE_RDI1):
1251 return RDI1;
1252 case (VFE_LINE_RDI2):
1253 return RDI2;
1254 case (VFE_LINE_PIX):
1255 return PIX0;
1256 default:
1257 return RDI0;
1258 }
1259}
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270static int ispif_link_setup(struct media_entity *entity,
1271 const struct media_pad *local,
1272 const struct media_pad *remote, u32 flags)
1273{
1274 if (flags & MEDIA_LNK_FL_ENABLED) {
1275 if (media_entity_remote_pad(local))
1276 return -EBUSY;
1277
1278 if (local->flags & MEDIA_PAD_FL_SINK) {
1279 struct v4l2_subdev *sd;
1280 struct ispif_line *line;
1281
1282 sd = media_entity_to_v4l2_subdev(entity);
1283 line = v4l2_get_subdevdata(sd);
1284
1285 msm_csid_get_csid_id(remote->entity, &line->csid_id);
1286 } else {
1287 struct v4l2_subdev *sd;
1288 struct ispif_line *line;
1289 enum vfe_line_id id;
1290
1291 sd = media_entity_to_v4l2_subdev(entity);
1292 line = v4l2_get_subdevdata(sd);
1293
1294 msm_vfe_get_vfe_id(remote->entity, &line->vfe_id);
1295 msm_vfe_get_vfe_line_id(remote->entity, &id);
1296 line->interface = ispif_get_intf(id);
1297 }
1298 }
1299
1300 return 0;
1301}
1302
1303static const struct v4l2_subdev_core_ops ispif_core_ops = {
1304 .s_power = ispif_set_power,
1305};
1306
1307static const struct v4l2_subdev_video_ops ispif_video_ops = {
1308 .s_stream = ispif_set_stream,
1309};
1310
1311static const struct v4l2_subdev_pad_ops ispif_pad_ops = {
1312 .enum_mbus_code = ispif_enum_mbus_code,
1313 .enum_frame_size = ispif_enum_frame_size,
1314 .get_fmt = ispif_get_format,
1315 .set_fmt = ispif_set_format,
1316};
1317
1318static const struct v4l2_subdev_ops ispif_v4l2_ops = {
1319 .core = &ispif_core_ops,
1320 .video = &ispif_video_ops,
1321 .pad = &ispif_pad_ops,
1322};
1323
1324static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = {
1325 .open = ispif_init_formats,
1326};
1327
1328static const struct media_entity_operations ispif_media_ops = {
1329 .link_setup = ispif_link_setup,
1330 .link_validate = v4l2_subdev_link_validate,
1331};
1332
1333
1334
1335
1336
1337
1338
1339
1340int msm_ispif_register_entities(struct ispif_device *ispif,
1341 struct v4l2_device *v4l2_dev)
1342{
1343 struct camss *camss;
1344 int ret;
1345 int i;
1346
1347 if (!ispif)
1348 return 0;
1349
1350 camss = ispif->camss;
1351
1352 for (i = 0; i < ispif->line_num; i++) {
1353 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1354 struct media_pad *pads = ispif->line[i].pads;
1355
1356 v4l2_subdev_init(sd, &ispif_v4l2_ops);
1357 sd->internal_ops = &ispif_v4l2_internal_ops;
1358 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1359 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d",
1360 MSM_ISPIF_NAME, i);
1361 v4l2_set_subdevdata(sd, &ispif->line[i]);
1362
1363 ret = ispif_init_formats(sd, NULL);
1364 if (ret < 0) {
1365 dev_err(camss->dev, "Failed to init format: %d\n", ret);
1366 goto error;
1367 }
1368
1369 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1370 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
1371
1372 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1373 sd->entity.ops = &ispif_media_ops;
1374 ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM,
1375 pads);
1376 if (ret < 0) {
1377 dev_err(camss->dev, "Failed to init media entity: %d\n",
1378 ret);
1379 goto error;
1380 }
1381
1382 ret = v4l2_device_register_subdev(v4l2_dev, sd);
1383 if (ret < 0) {
1384 dev_err(camss->dev, "Failed to register subdev: %d\n",
1385 ret);
1386 media_entity_cleanup(&sd->entity);
1387 goto error;
1388 }
1389 }
1390
1391 return 0;
1392
1393error:
1394 for (i--; i >= 0; i--) {
1395 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1396
1397 v4l2_device_unregister_subdev(sd);
1398 media_entity_cleanup(&sd->entity);
1399 }
1400
1401 return ret;
1402}
1403
1404
1405
1406
1407
1408void msm_ispif_unregister_entities(struct ispif_device *ispif)
1409{
1410 int i;
1411
1412 if (!ispif)
1413 return;
1414
1415 mutex_destroy(&ispif->power_lock);
1416 mutex_destroy(&ispif->config_lock);
1417
1418 for (i = 0; i < ispif->line_num; i++) {
1419 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1420
1421 v4l2_device_unregister_subdev(sd);
1422 media_entity_cleanup(&sd->entity);
1423 }
1424}
1425
