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12#include <linux/clk.h>
13#include <linux/clk/tegra.h>
14#include <linux/debugfs.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/interconnect-provider.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/iopoll.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/mutex.h>
24#include <linux/of_platform.h>
25#include <linux/platform_device.h>
26#include <linux/pm_opp.h>
27#include <linux/slab.h>
28#include <linux/sort.h>
29#include <linux/types.h>
30
31#include <soc/tegra/common.h>
32#include <soc/tegra/fuse.h>
33
34#include "mc.h"
35
36#define EMC_INTSTATUS 0x000
37#define EMC_INTMASK 0x004
38#define EMC_DBG 0x008
39#define EMC_CFG 0x00c
40#define EMC_REFCTRL 0x020
41#define EMC_TIMING_CONTROL 0x028
42#define EMC_RC 0x02c
43#define EMC_RFC 0x030
44#define EMC_RAS 0x034
45#define EMC_RP 0x038
46#define EMC_R2W 0x03c
47#define EMC_W2R 0x040
48#define EMC_R2P 0x044
49#define EMC_W2P 0x048
50#define EMC_RD_RCD 0x04c
51#define EMC_WR_RCD 0x050
52#define EMC_RRD 0x054
53#define EMC_REXT 0x058
54#define EMC_WDV 0x05c
55#define EMC_QUSE 0x060
56#define EMC_QRST 0x064
57#define EMC_QSAFE 0x068
58#define EMC_RDV 0x06c
59#define EMC_REFRESH 0x070
60#define EMC_BURST_REFRESH_NUM 0x074
61#define EMC_PDEX2WR 0x078
62#define EMC_PDEX2RD 0x07c
63#define EMC_PCHG2PDEN 0x080
64#define EMC_ACT2PDEN 0x084
65#define EMC_AR2PDEN 0x088
66#define EMC_RW2PDEN 0x08c
67#define EMC_TXSR 0x090
68#define EMC_TCKE 0x094
69#define EMC_TFAW 0x098
70#define EMC_TRPAB 0x09c
71#define EMC_TCLKSTABLE 0x0a0
72#define EMC_TCLKSTOP 0x0a4
73#define EMC_TREFBW 0x0a8
74#define EMC_QUSE_EXTRA 0x0ac
75#define EMC_ODT_WRITE 0x0b0
76#define EMC_ODT_READ 0x0b4
77#define EMC_WEXT 0x0b8
78#define EMC_CTT 0x0bc
79#define EMC_MRS_WAIT_CNT 0x0c8
80#define EMC_MRS 0x0cc
81#define EMC_EMRS 0x0d0
82#define EMC_SELF_REF 0x0e0
83#define EMC_MRW 0x0e8
84#define EMC_XM2DQSPADCTRL3 0x0f8
85#define EMC_FBIO_SPARE 0x100
86#define EMC_FBIO_CFG5 0x104
87#define EMC_FBIO_CFG6 0x114
88#define EMC_CFG_RSV 0x120
89#define EMC_AUTO_CAL_CONFIG 0x2a4
90#define EMC_AUTO_CAL_INTERVAL 0x2a8
91#define EMC_AUTO_CAL_STATUS 0x2ac
92#define EMC_STATUS 0x2b4
93#define EMC_CFG_2 0x2b8
94#define EMC_CFG_DIG_DLL 0x2bc
95#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
96#define EMC_CTT_DURATION 0x2d8
97#define EMC_CTT_TERM_CTRL 0x2dc
98#define EMC_ZCAL_INTERVAL 0x2e0
99#define EMC_ZCAL_WAIT_CNT 0x2e4
100#define EMC_ZQ_CAL 0x2ec
101#define EMC_XM2CMDPADCTRL 0x2f0
102#define EMC_XM2DQSPADCTRL2 0x2fc
103#define EMC_XM2DQPADCTRL2 0x304
104#define EMC_XM2CLKPADCTRL 0x308
105#define EMC_XM2COMPPADCTRL 0x30c
106#define EMC_XM2VTTGENPADCTRL 0x310
107#define EMC_XM2VTTGENPADCTRL2 0x314
108#define EMC_XM2QUSEPADCTRL 0x318
109#define EMC_DLL_XFORM_DQS0 0x328
110#define EMC_DLL_XFORM_DQS1 0x32c
111#define EMC_DLL_XFORM_DQS2 0x330
112#define EMC_DLL_XFORM_DQS3 0x334
113#define EMC_DLL_XFORM_DQS4 0x338
114#define EMC_DLL_XFORM_DQS5 0x33c
115#define EMC_DLL_XFORM_DQS6 0x340
116#define EMC_DLL_XFORM_DQS7 0x344
117#define EMC_DLL_XFORM_QUSE0 0x348
118#define EMC_DLL_XFORM_QUSE1 0x34c
119#define EMC_DLL_XFORM_QUSE2 0x350
120#define EMC_DLL_XFORM_QUSE3 0x354
121#define EMC_DLL_XFORM_QUSE4 0x358
122#define EMC_DLL_XFORM_QUSE5 0x35c
123#define EMC_DLL_XFORM_QUSE6 0x360
124#define EMC_DLL_XFORM_QUSE7 0x364
125#define EMC_DLL_XFORM_DQ0 0x368
126#define EMC_DLL_XFORM_DQ1 0x36c
127#define EMC_DLL_XFORM_DQ2 0x370
128#define EMC_DLL_XFORM_DQ3 0x374
129#define EMC_DLI_TRIM_TXDQS0 0x3a8
130#define EMC_DLI_TRIM_TXDQS1 0x3ac
131#define EMC_DLI_TRIM_TXDQS2 0x3b0
132#define EMC_DLI_TRIM_TXDQS3 0x3b4
133#define EMC_DLI_TRIM_TXDQS4 0x3b8
134#define EMC_DLI_TRIM_TXDQS5 0x3bc
135#define EMC_DLI_TRIM_TXDQS6 0x3c0
136#define EMC_DLI_TRIM_TXDQS7 0x3c4
137#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8
138#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
139#define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0
140#define EMC_SEL_DPD_CTRL 0x3d8
141#define EMC_PRE_REFRESH_REQ_CNT 0x3dc
142#define EMC_DYN_SELF_REF_CONTROL 0x3e0
143#define EMC_TXSRDLL 0x3e4
144
145#define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
146
147#define EMC_MODE_SET_DLL_RESET BIT(8)
148#define EMC_MODE_SET_LONG_CNT BIT(26)
149
150#define EMC_SELF_REF_CMD_ENABLED BIT(0)
151
152#define DRAM_DEV_SEL_ALL (0 << 30)
153#define DRAM_DEV_SEL_0 (2 << 30)
154#define DRAM_DEV_SEL_1 (1 << 30)
155#define DRAM_BROADCAST(num) \
156 ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
157
158#define EMC_ZQ_CAL_CMD BIT(0)
159#define EMC_ZQ_CAL_LONG BIT(4)
160#define EMC_ZQ_CAL_LONG_CMD_DEV0 \
161 (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
162#define EMC_ZQ_CAL_LONG_CMD_DEV1 \
163 (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
164
165#define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
166#define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
167#define EMC_DBG_FORCE_UPDATE BIT(2)
168#define EMC_DBG_CFG_PRIORITY BIT(24)
169
170#define EMC_CFG5_QUSE_MODE_SHIFT 13
171#define EMC_CFG5_QUSE_MODE_MASK (7 << EMC_CFG5_QUSE_MODE_SHIFT)
172
173#define EMC_CFG5_QUSE_MODE_INTERNAL_LPBK 2
174#define EMC_CFG5_QUSE_MODE_PULSE_INTERN 3
175
176#define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE BIT(9)
177
178#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE BIT(10)
179
180#define EMC_XM2QUSEPADCTRL_IVREF_ENABLE BIT(4)
181
182#define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5)
183#define EMC_XM2DQSPADCTRL3_VREF_ENABLE BIT(5)
184
185#define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31)
186
187#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
188
189#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK 0x3ff
190#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
191#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
192 (0x3ff << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
193
194#define EMC_REFCTRL_DEV_SEL_MASK 0x3
195#define EMC_REFCTRL_ENABLE BIT(31)
196#define EMC_REFCTRL_ENABLE_ALL(num) \
197 (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
198#define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2)
199
200#define EMC_CFG_PERIODIC_QRST BIT(21)
201#define EMC_CFG_DYN_SREF_ENABLE BIT(28)
202
203#define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
204#define EMC_CLKCHANGE_PD_ENABLE BIT(1)
205#define EMC_CLKCHANGE_SR_ENABLE BIT(2)
206
207#define EMC_TIMING_UPDATE BIT(0)
208
209#define EMC_REFRESH_OVERFLOW_INT BIT(3)
210#define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
211
212enum emc_dram_type {
213 DRAM_TYPE_DDR3,
214 DRAM_TYPE_DDR1,
215 DRAM_TYPE_LPDDR2,
216 DRAM_TYPE_DDR2,
217};
218
219enum emc_dll_change {
220 DLL_CHANGE_NONE,
221 DLL_CHANGE_ON,
222 DLL_CHANGE_OFF
223};
224
225static const u16 emc_timing_registers[] = {
226 [0] = EMC_RC,
227 [1] = EMC_RFC,
228 [2] = EMC_RAS,
229 [3] = EMC_RP,
230 [4] = EMC_R2W,
231 [5] = EMC_W2R,
232 [6] = EMC_R2P,
233 [7] = EMC_W2P,
234 [8] = EMC_RD_RCD,
235 [9] = EMC_WR_RCD,
236 [10] = EMC_RRD,
237 [11] = EMC_REXT,
238 [12] = EMC_WEXT,
239 [13] = EMC_WDV,
240 [14] = EMC_QUSE,
241 [15] = EMC_QRST,
242 [16] = EMC_QSAFE,
243 [17] = EMC_RDV,
244 [18] = EMC_REFRESH,
245 [19] = EMC_BURST_REFRESH_NUM,
246 [20] = EMC_PRE_REFRESH_REQ_CNT,
247 [21] = EMC_PDEX2WR,
248 [22] = EMC_PDEX2RD,
249 [23] = EMC_PCHG2PDEN,
250 [24] = EMC_ACT2PDEN,
251 [25] = EMC_AR2PDEN,
252 [26] = EMC_RW2PDEN,
253 [27] = EMC_TXSR,
254 [28] = EMC_TXSRDLL,
255 [29] = EMC_TCKE,
256 [30] = EMC_TFAW,
257 [31] = EMC_TRPAB,
258 [32] = EMC_TCLKSTABLE,
259 [33] = EMC_TCLKSTOP,
260 [34] = EMC_TREFBW,
261 [35] = EMC_QUSE_EXTRA,
262 [36] = EMC_FBIO_CFG6,
263 [37] = EMC_ODT_WRITE,
264 [38] = EMC_ODT_READ,
265 [39] = EMC_FBIO_CFG5,
266 [40] = EMC_CFG_DIG_DLL,
267 [41] = EMC_CFG_DIG_DLL_PERIOD,
268 [42] = EMC_DLL_XFORM_DQS0,
269 [43] = EMC_DLL_XFORM_DQS1,
270 [44] = EMC_DLL_XFORM_DQS2,
271 [45] = EMC_DLL_XFORM_DQS3,
272 [46] = EMC_DLL_XFORM_DQS4,
273 [47] = EMC_DLL_XFORM_DQS5,
274 [48] = EMC_DLL_XFORM_DQS6,
275 [49] = EMC_DLL_XFORM_DQS7,
276 [50] = EMC_DLL_XFORM_QUSE0,
277 [51] = EMC_DLL_XFORM_QUSE1,
278 [52] = EMC_DLL_XFORM_QUSE2,
279 [53] = EMC_DLL_XFORM_QUSE3,
280 [54] = EMC_DLL_XFORM_QUSE4,
281 [55] = EMC_DLL_XFORM_QUSE5,
282 [56] = EMC_DLL_XFORM_QUSE6,
283 [57] = EMC_DLL_XFORM_QUSE7,
284 [58] = EMC_DLI_TRIM_TXDQS0,
285 [59] = EMC_DLI_TRIM_TXDQS1,
286 [60] = EMC_DLI_TRIM_TXDQS2,
287 [61] = EMC_DLI_TRIM_TXDQS3,
288 [62] = EMC_DLI_TRIM_TXDQS4,
289 [63] = EMC_DLI_TRIM_TXDQS5,
290 [64] = EMC_DLI_TRIM_TXDQS6,
291 [65] = EMC_DLI_TRIM_TXDQS7,
292 [66] = EMC_DLL_XFORM_DQ0,
293 [67] = EMC_DLL_XFORM_DQ1,
294 [68] = EMC_DLL_XFORM_DQ2,
295 [69] = EMC_DLL_XFORM_DQ3,
296 [70] = EMC_XM2CMDPADCTRL,
297 [71] = EMC_XM2DQSPADCTRL2,
298 [72] = EMC_XM2DQPADCTRL2,
299 [73] = EMC_XM2CLKPADCTRL,
300 [74] = EMC_XM2COMPPADCTRL,
301 [75] = EMC_XM2VTTGENPADCTRL,
302 [76] = EMC_XM2VTTGENPADCTRL2,
303 [77] = EMC_XM2QUSEPADCTRL,
304 [78] = EMC_XM2DQSPADCTRL3,
305 [79] = EMC_CTT_TERM_CTRL,
306 [80] = EMC_ZCAL_INTERVAL,
307 [81] = EMC_ZCAL_WAIT_CNT,
308 [82] = EMC_MRS_WAIT_CNT,
309 [83] = EMC_AUTO_CAL_CONFIG,
310 [84] = EMC_CTT,
311 [85] = EMC_CTT_DURATION,
312 [86] = EMC_DYN_SELF_REF_CONTROL,
313 [87] = EMC_FBIO_SPARE,
314 [88] = EMC_CFG_RSV,
315};
316
317struct emc_timing {
318 unsigned long rate;
319
320 u32 data[ARRAY_SIZE(emc_timing_registers)];
321
322 u32 emc_auto_cal_interval;
323 u32 emc_mode_1;
324 u32 emc_mode_2;
325 u32 emc_mode_reset;
326 u32 emc_zcal_cnt_long;
327 bool emc_cfg_periodic_qrst;
328 bool emc_cfg_dyn_self_ref;
329};
330
331enum emc_rate_request_type {
332 EMC_RATE_DEBUG,
333 EMC_RATE_ICC,
334 EMC_RATE_TYPE_MAX,
335};
336
337struct emc_rate_request {
338 unsigned long min_rate;
339 unsigned long max_rate;
340};
341
342struct tegra_emc {
343 struct device *dev;
344 struct tegra_mc *mc;
345 struct icc_provider provider;
346 struct notifier_block clk_nb;
347 struct clk *clk;
348 void __iomem *regs;
349 unsigned int irq;
350 bool bad_state;
351
352 struct emc_timing *new_timing;
353 struct emc_timing *timings;
354 unsigned int num_timings;
355
356 u32 mc_override;
357 u32 emc_cfg;
358
359 u32 emc_mode_1;
360 u32 emc_mode_2;
361 u32 emc_mode_reset;
362
363 bool vref_cal_toggle : 1;
364 bool zcal_long : 1;
365 bool dll_on : 1;
366
367 struct {
368 struct dentry *root;
369 unsigned long min_rate;
370 unsigned long max_rate;
371 } debugfs;
372
373
374
375
376
377 struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
378
379
380 struct mutex rate_lock;
381};
382
383static int emc_seq_update_timing(struct tegra_emc *emc)
384{
385 u32 val;
386 int err;
387
388 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL);
389
390 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val,
391 !(val & EMC_STATUS_TIMING_UPDATE_STALLED),
392 1, 200);
393 if (err) {
394 dev_err(emc->dev, "failed to update timing: %d\n", err);
395 return err;
396 }
397
398 return 0;
399}
400
401static irqreturn_t tegra_emc_isr(int irq, void *data)
402{
403 struct tegra_emc *emc = data;
404 u32 intmask = EMC_REFRESH_OVERFLOW_INT;
405 u32 status;
406
407 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
408 if (!status)
409 return IRQ_NONE;
410
411
412 if (status & EMC_REFRESH_OVERFLOW_INT)
413 dev_err_ratelimited(emc->dev,
414 "refresh request overflow timeout\n");
415
416
417 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
418
419 return IRQ_HANDLED;
420}
421
422static struct emc_timing *emc_find_timing(struct tegra_emc *emc,
423 unsigned long rate)
424{
425 struct emc_timing *timing = NULL;
426 unsigned int i;
427
428 for (i = 0; i < emc->num_timings; i++) {
429 if (emc->timings[i].rate >= rate) {
430 timing = &emc->timings[i];
431 break;
432 }
433 }
434
435 if (!timing) {
436 dev_err(emc->dev, "no timing for rate %lu\n", rate);
437 return NULL;
438 }
439
440 return timing;
441}
442
443static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing,
444 bool *schmitt_to_vref)
445{
446 bool preset = false;
447 u32 val;
448
449 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) {
450 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2);
451
452 if (!(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
453 val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
454 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2);
455
456 preset = true;
457 }
458 }
459
460 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) {
461 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3);
462
463 if (!(val & EMC_XM2DQSPADCTRL3_VREF_ENABLE)) {
464 val |= EMC_XM2DQSPADCTRL3_VREF_ENABLE;
465 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3);
466
467 preset = true;
468 }
469 }
470
471 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) {
472 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL);
473
474 if (!(val & EMC_XM2QUSEPADCTRL_IVREF_ENABLE)) {
475 val |= EMC_XM2QUSEPADCTRL_IVREF_ENABLE;
476 writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL);
477
478 *schmitt_to_vref = true;
479 preset = true;
480 }
481 }
482
483 return preset;
484}
485
486static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate)
487{
488 struct tegra_mc *mc = emc->mc;
489 unsigned int misc0_index = 16;
490 unsigned int i;
491 bool same;
492
493 for (i = 0; i < mc->num_timings; i++) {
494 if (mc->timings[i].rate != rate)
495 continue;
496
497 if (mc->timings[i].emem_data[misc0_index] & BIT(27))
498 same = true;
499 else
500 same = false;
501
502 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same);
503 }
504
505 return -EINVAL;
506}
507
508static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
509{
510 struct emc_timing *timing = emc_find_timing(emc, rate);
511 enum emc_dll_change dll_change;
512 enum emc_dram_type dram_type;
513 bool schmitt_to_vref = false;
514 unsigned int pre_wait = 0;
515 bool qrst_used = false;
516 unsigned int dram_num;
517 unsigned int i;
518 u32 fbio_cfg5;
519 u32 emc_dbg;
520 u32 val;
521 int err;
522
523 if (!timing || emc->bad_state)
524 return -EINVAL;
525
526 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
527 __func__, timing->rate, rate);
528
529 emc->bad_state = true;
530
531 err = emc_prepare_mc_clk_cfg(emc, rate);
532 if (err) {
533 dev_err(emc->dev, "mc clock preparation failed: %d\n", err);
534 return err;
535 }
536
537 emc->vref_cal_toggle = false;
538 emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
539 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG);
540 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
541
542 if (emc->dll_on == !!(timing->emc_mode_1 & 0x1))
543 dll_change = DLL_CHANGE_NONE;
544 else if (timing->emc_mode_1 & 0x1)
545 dll_change = DLL_CHANGE_ON;
546 else
547 dll_change = DLL_CHANGE_OFF;
548
549 emc->dll_on = !!(timing->emc_mode_1 & 0x1);
550
551 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL))
552 emc->zcal_long = true;
553 else
554 emc->zcal_long = false;
555
556 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
557 dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
558
559 dram_num = tegra_mc_get_emem_device_count(emc->mc);
560
561
562 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) {
563 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE;
564 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
565
566 pre_wait = 5;
567 }
568
569
570 val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ);
571 if (!(val & MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE) ||
572 ((val & MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK) > 0x50)) {
573
574 val = MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE |
575 MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE | 0x50;
576 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ);
577 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
578 }
579
580 if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK)
581 mc_writel(emc->mc,
582 emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK,
583 MC_EMEM_ARB_OVERRIDE);
584
585
586 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) {
587 if (pre_wait < 3)
588 pre_wait = 3;
589 }
590
591 if (pre_wait) {
592 err = emc_seq_update_timing(emc);
593 if (err)
594 return err;
595
596 udelay(pre_wait);
597 }
598
599
600 if (timing->emc_auto_cal_interval) {
601 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL);
602 val ^= timing->data[74];
603
604 if (val & EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE) {
605 writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
606
607 err = readl_relaxed_poll_timeout_atomic(
608 emc->regs + EMC_AUTO_CAL_STATUS, val,
609 !(val & EMC_AUTO_CAL_STATUS_ACTIVE), 1, 300);
610 if (err) {
611 dev_err(emc->dev,
612 "auto-cal finish timeout: %d\n", err);
613 return err;
614 }
615
616 emc->vref_cal_toggle = true;
617 }
618 }
619
620
621 for (i = 0; i < ARRAY_SIZE(timing->data); i++) {
622
623 if (i != 73)
624 writel_relaxed(timing->data[i],
625 emc->regs + emc_timing_registers[i]);
626 }
627
628 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);
629 if (err)
630 return err;
631
632
633 if (dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) {
634 u32 cnt = 512;
635
636 if (emc->zcal_long)
637 cnt -= dram_num * 256;
638
639 val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK;
640 if (cnt < val)
641 cnt = val;
642
643 val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
644 val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) &
645 EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
646
647 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT);
648 }
649
650
651 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL);
652
653 if (!(val & EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE) && schmitt_to_vref) {
654 u32 cur_mode, new_mode;
655
656 cur_mode = fbio_cfg5 & EMC_CFG5_QUSE_MODE_MASK;
657 cur_mode >>= EMC_CFG5_QUSE_MODE_SHIFT;
658
659 new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK;
660 new_mode >>= EMC_CFG5_QUSE_MODE_SHIFT;
661
662 if ((cur_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN &&
663 cur_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK) ||
664 (new_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN &&
665 new_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK))
666 qrst_used = true;
667 }
668
669
670 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE);
671
672
673 if (qrst_used) {
674 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,
675 emc->regs + EMC_DBG);
676 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST,
677 emc->regs + EMC_CFG);
678 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
679 }
680
681
682 writel_relaxed(EMC_REFCTRL_DISABLE_ALL(dram_num),
683 emc->regs + EMC_REFCTRL);
684
685
686 if (dram_type == DRAM_TYPE_DDR3) {
687 if (dll_change == DLL_CHANGE_OFF)
688 writel_relaxed(timing->emc_mode_1,
689 emc->regs + EMC_EMRS);
690
691 writel_relaxed(DRAM_BROADCAST(dram_num) |
692 EMC_SELF_REF_CMD_ENABLED,
693 emc->regs + EMC_SELF_REF);
694 }
695
696
697 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
698
699
700 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG);
701 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
702
703
704 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST);
705 if (qrst_used || timing->emc_cfg_periodic_qrst != val) {
706 if (timing->emc_cfg_periodic_qrst)
707 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST;
708 else
709 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST;
710
711 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
712 }
713 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
714
715
716 if (dram_type == DRAM_TYPE_DDR3)
717 writel_relaxed(DRAM_BROADCAST(dram_num),
718 emc->regs + EMC_SELF_REF);
719
720
721 if (dram_type == DRAM_TYPE_DDR3) {
722 if (timing->emc_mode_1 != emc->emc_mode_1)
723 writel_relaxed(timing->emc_mode_1,
724 emc->regs + EMC_EMRS);
725
726 if (timing->emc_mode_2 != emc->emc_mode_2)
727 writel_relaxed(timing->emc_mode_2,
728 emc->regs + EMC_EMRS);
729
730 if (timing->emc_mode_reset != emc->emc_mode_reset ||
731 dll_change == DLL_CHANGE_ON) {
732 val = timing->emc_mode_reset;
733 if (dll_change == DLL_CHANGE_ON) {
734 val |= EMC_MODE_SET_DLL_RESET;
735 val |= EMC_MODE_SET_LONG_CNT;
736 } else {
737 val &= ~EMC_MODE_SET_DLL_RESET;
738 }
739 writel_relaxed(val, emc->regs + EMC_MRS);
740 }
741 } else {
742 if (timing->emc_mode_2 != emc->emc_mode_2)
743 writel_relaxed(timing->emc_mode_2,
744 emc->regs + EMC_MRW);
745
746 if (timing->emc_mode_1 != emc->emc_mode_1)
747 writel_relaxed(timing->emc_mode_1,
748 emc->regs + EMC_MRW);
749 }
750
751 emc->emc_mode_1 = timing->emc_mode_1;
752 emc->emc_mode_2 = timing->emc_mode_2;
753 emc->emc_mode_reset = timing->emc_mode_reset;
754
755
756 if (emc->zcal_long) {
757 writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV0,
758 emc->regs + EMC_ZQ_CAL);
759
760 if (dram_num > 1)
761 writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV1,
762 emc->regs + EMC_ZQ_CAL);
763 }
764
765
766 writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE);
767
768
769
770
771
772 mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
773
774 return 0;
775}
776
777static int emc_complete_timing_change(struct tegra_emc *emc,
778 unsigned long rate)
779{
780 struct emc_timing *timing = emc_find_timing(emc, rate);
781 unsigned int dram_num;
782 int err;
783 u32 v;
784
785 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
786 v & EMC_CLKCHANGE_COMPLETE_INT,
787 1, 100);
788 if (err) {
789 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
790 return err;
791 }
792
793
794 dram_num = tegra_mc_get_emem_device_count(emc->mc);
795 writel_relaxed(EMC_REFCTRL_ENABLE_ALL(dram_num),
796 emc->regs + EMC_REFCTRL);
797
798
799 if (emc->vref_cal_toggle)
800 writel_relaxed(timing->emc_auto_cal_interval,
801 emc->regs + EMC_AUTO_CAL_INTERVAL);
802
803
804 if (timing->emc_cfg_dyn_self_ref) {
805 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE;
806 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
807 }
808
809
810 if (emc->zcal_long)
811 writel_relaxed(timing->emc_zcal_cnt_long,
812 emc->regs + EMC_ZCAL_WAIT_CNT);
813
814
815 udelay(2);
816
817
818 err = emc_seq_update_timing(emc);
819 if (!err)
820 emc->bad_state = false;
821
822
823 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE);
824
825 return err;
826}
827
828static int emc_unprepare_timing_change(struct tegra_emc *emc,
829 unsigned long rate)
830{
831 if (!emc->bad_state) {
832
833 dev_err(emc->dev, "timing configuration can't be reverted\n");
834 emc->bad_state = true;
835 }
836
837 return 0;
838}
839
840static int emc_clk_change_notify(struct notifier_block *nb,
841 unsigned long msg, void *data)
842{
843 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
844 struct clk_notifier_data *cnd = data;
845 int err;
846
847 switch (msg) {
848 case PRE_RATE_CHANGE:
849
850
851
852
853 disable_irq(emc->irq);
854 err = emc_prepare_timing_change(emc, cnd->new_rate);
855 enable_irq(emc->irq);
856 break;
857
858 case ABORT_RATE_CHANGE:
859 err = emc_unprepare_timing_change(emc, cnd->old_rate);
860 break;
861
862 case POST_RATE_CHANGE:
863 err = emc_complete_timing_change(emc, cnd->new_rate);
864 break;
865
866 default:
867 return NOTIFY_DONE;
868 }
869
870 return notifier_from_errno(err);
871}
872
873static int load_one_timing_from_dt(struct tegra_emc *emc,
874 struct emc_timing *timing,
875 struct device_node *node)
876{
877 u32 value;
878 int err;
879
880 err = of_property_read_u32(node, "clock-frequency", &value);
881 if (err) {
882 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
883 node, err);
884 return err;
885 }
886
887 timing->rate = value;
888
889 err = of_property_read_u32_array(node, "nvidia,emc-configuration",
890 timing->data,
891 ARRAY_SIZE(emc_timing_registers));
892 if (err) {
893 dev_err(emc->dev,
894 "timing %pOF: failed to read emc timing data: %d\n",
895 node, err);
896 return err;
897 }
898
899#define EMC_READ_BOOL(prop, dtprop) \
900 timing->prop = of_property_read_bool(node, dtprop);
901
902#define EMC_READ_U32(prop, dtprop) \
903 err = of_property_read_u32(node, dtprop, &timing->prop); \
904 if (err) { \
905 dev_err(emc->dev, \
906 "timing %pOFn: failed to read " #prop ": %d\n", \
907 node, err); \
908 return err; \
909 }
910
911 EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
912 EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1")
913 EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2")
914 EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset")
915 EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
916 EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref")
917 EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst")
918
919#undef EMC_READ_U32
920#undef EMC_READ_BOOL
921
922 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate);
923
924 return 0;
925}
926
927static int cmp_timings(const void *_a, const void *_b)
928{
929 const struct emc_timing *a = _a;
930 const struct emc_timing *b = _b;
931
932 if (a->rate < b->rate)
933 return -1;
934
935 if (a->rate > b->rate)
936 return 1;
937
938 return 0;
939}
940
941static int emc_check_mc_timings(struct tegra_emc *emc)
942{
943 struct tegra_mc *mc = emc->mc;
944 unsigned int i;
945
946 if (emc->num_timings != mc->num_timings) {
947 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n",
948 emc->num_timings, mc->num_timings);
949 return -EINVAL;
950 }
951
952 for (i = 0; i < mc->num_timings; i++) {
953 if (emc->timings[i].rate != mc->timings[i].rate) {
954 dev_err(emc->dev,
955 "emc/mc timing rate mismatch: %lu %lu\n",
956 emc->timings[i].rate, mc->timings[i].rate);
957 return -EINVAL;
958 }
959 }
960
961 return 0;
962}
963
964static int emc_load_timings_from_dt(struct tegra_emc *emc,
965 struct device_node *node)
966{
967 struct device_node *child;
968 struct emc_timing *timing;
969 int child_count;
970 int err;
971
972 child_count = of_get_child_count(node);
973 if (!child_count) {
974 dev_err(emc->dev, "no memory timings in: %pOF\n", node);
975 return -EINVAL;
976 }
977
978 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
979 GFP_KERNEL);
980 if (!emc->timings)
981 return -ENOMEM;
982
983 emc->num_timings = child_count;
984 timing = emc->timings;
985
986 for_each_child_of_node(node, child) {
987 err = load_one_timing_from_dt(emc, timing++, child);
988 if (err) {
989 of_node_put(child);
990 return err;
991 }
992 }
993
994 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
995 NULL);
996
997 err = emc_check_mc_timings(emc);
998 if (err)
999 return err;
1000
1001 dev_info_once(emc->dev,
1002 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
1003 emc->num_timings,
1004 tegra_read_ram_code(),
1005 emc->timings[0].rate / 1000000,
1006 emc->timings[emc->num_timings - 1].rate / 1000000);
1007
1008 return 0;
1009}
1010
1011static struct device_node *emc_find_node_by_ram_code(struct device *dev)
1012{
1013 struct device_node *np;
1014 u32 value, ram_code;
1015 int err;
1016
1017 if (of_get_child_count(dev->of_node) == 0) {
1018 dev_info_once(dev, "device-tree doesn't have memory timings\n");
1019 return NULL;
1020 }
1021
1022 ram_code = tegra_read_ram_code();
1023
1024 for_each_child_of_node(dev->of_node, np) {
1025 err = of_property_read_u32(np, "nvidia,ram-code", &value);
1026 if (err || value != ram_code)
1027 continue;
1028
1029 return np;
1030 }
1031
1032 dev_err(dev, "no memory timings for RAM code %u found in device-tree\n",
1033 ram_code);
1034
1035 return NULL;
1036}
1037
1038static int emc_setup_hw(struct tegra_emc *emc)
1039{
1040 u32 intmask = EMC_REFRESH_OVERFLOW_INT;
1041 u32 fbio_cfg5, emc_cfg, emc_dbg;
1042 enum emc_dram_type dram_type;
1043
1044 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
1045 dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
1046
1047 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
1048
1049
1050 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
1051
1052
1053 switch (dram_type) {
1054 case DRAM_TYPE_LPDDR2:
1055 emc_cfg |= EMC_CLKCHANGE_PD_ENABLE;
1056 emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;
1057 break;
1058
1059 default:
1060 emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;
1061 emc_cfg &= ~EMC_CLKCHANGE_PD_ENABLE;
1062 break;
1063 }
1064
1065 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
1066
1067
1068 writel_relaxed(intmask, emc->regs + EMC_INTMASK);
1069 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS);
1070
1071
1072 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
1073 emc_dbg |= EMC_DBG_CFG_PRIORITY;
1074 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
1075 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
1076 emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
1077 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
1078
1079 return 0;
1080}
1081
1082static long emc_round_rate(unsigned long rate,
1083 unsigned long min_rate,
1084 unsigned long max_rate,
1085 void *arg)
1086{
1087 struct emc_timing *timing = NULL;
1088 struct tegra_emc *emc = arg;
1089 unsigned int i;
1090
1091 if (!emc->num_timings)
1092 return clk_get_rate(emc->clk);
1093
1094 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
1095
1096 for (i = 0; i < emc->num_timings; i++) {
1097 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
1098 continue;
1099
1100 if (emc->timings[i].rate > max_rate) {
1101 i = max(i, 1u) - 1;
1102
1103 if (emc->timings[i].rate < min_rate)
1104 break;
1105 }
1106
1107 if (emc->timings[i].rate < min_rate)
1108 continue;
1109
1110 timing = &emc->timings[i];
1111 break;
1112 }
1113
1114 if (!timing) {
1115 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
1116 rate, min_rate, max_rate);
1117 return -EINVAL;
1118 }
1119
1120 return timing->rate;
1121}
1122
1123static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
1124{
1125 unsigned int i;
1126
1127 for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
1128 emc->requested_rate[i].min_rate = 0;
1129 emc->requested_rate[i].max_rate = ULONG_MAX;
1130 }
1131}
1132
1133static int emc_request_rate(struct tegra_emc *emc,
1134 unsigned long new_min_rate,
1135 unsigned long new_max_rate,
1136 enum emc_rate_request_type type)
1137{
1138 struct emc_rate_request *req = emc->requested_rate;
1139 unsigned long min_rate = 0, max_rate = ULONG_MAX;
1140 unsigned int i;
1141 int err;
1142
1143
1144 for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
1145 if (i == type) {
1146 min_rate = max(new_min_rate, min_rate);
1147 max_rate = min(new_max_rate, max_rate);
1148 } else {
1149 min_rate = max(req->min_rate, min_rate);
1150 max_rate = min(req->max_rate, max_rate);
1151 }
1152 }
1153
1154 if (min_rate > max_rate) {
1155 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
1156 __func__, type, min_rate, max_rate);
1157 return -ERANGE;
1158 }
1159
1160
1161
1162
1163
1164 err = dev_pm_opp_set_rate(emc->dev, min_rate);
1165 if (err)
1166 return err;
1167
1168 emc->requested_rate[type].min_rate = new_min_rate;
1169 emc->requested_rate[type].max_rate = new_max_rate;
1170
1171 return 0;
1172}
1173
1174static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
1175 enum emc_rate_request_type type)
1176{
1177 struct emc_rate_request *req = &emc->requested_rate[type];
1178 int ret;
1179
1180 mutex_lock(&emc->rate_lock);
1181 ret = emc_request_rate(emc, rate, req->max_rate, type);
1182 mutex_unlock(&emc->rate_lock);
1183
1184 return ret;
1185}
1186
1187static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
1188 enum emc_rate_request_type type)
1189{
1190 struct emc_rate_request *req = &emc->requested_rate[type];
1191 int ret;
1192
1193 mutex_lock(&emc->rate_lock);
1194 ret = emc_request_rate(emc, req->min_rate, rate, type);
1195 mutex_unlock(&emc->rate_lock);
1196
1197 return ret;
1198}
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
1226{
1227 unsigned int i;
1228
1229 for (i = 0; i < emc->num_timings; i++)
1230 if (rate == emc->timings[i].rate)
1231 return true;
1232
1233 return false;
1234}
1235
1236static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
1237{
1238 struct tegra_emc *emc = s->private;
1239 const char *prefix = "";
1240 unsigned int i;
1241
1242 for (i = 0; i < emc->num_timings; i++) {
1243 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
1244 prefix = " ";
1245 }
1246
1247 seq_puts(s, "\n");
1248
1249 return 0;
1250}
1251
1252static int tegra_emc_debug_available_rates_open(struct inode *inode,
1253 struct file *file)
1254{
1255 return single_open(file, tegra_emc_debug_available_rates_show,
1256 inode->i_private);
1257}
1258
1259static const struct file_operations tegra_emc_debug_available_rates_fops = {
1260 .open = tegra_emc_debug_available_rates_open,
1261 .read = seq_read,
1262 .llseek = seq_lseek,
1263 .release = single_release,
1264};
1265
1266static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
1267{
1268 struct tegra_emc *emc = data;
1269
1270 *rate = emc->debugfs.min_rate;
1271
1272 return 0;
1273}
1274
1275static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
1276{
1277 struct tegra_emc *emc = data;
1278 int err;
1279
1280 if (!tegra_emc_validate_rate(emc, rate))
1281 return -EINVAL;
1282
1283 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
1284 if (err < 0)
1285 return err;
1286
1287 emc->debugfs.min_rate = rate;
1288
1289 return 0;
1290}
1291
1292DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
1293 tegra_emc_debug_min_rate_get,
1294 tegra_emc_debug_min_rate_set, "%llu\n");
1295
1296static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
1297{
1298 struct tegra_emc *emc = data;
1299
1300 *rate = emc->debugfs.max_rate;
1301
1302 return 0;
1303}
1304
1305static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
1306{
1307 struct tegra_emc *emc = data;
1308 int err;
1309
1310 if (!tegra_emc_validate_rate(emc, rate))
1311 return -EINVAL;
1312
1313 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
1314 if (err < 0)
1315 return err;
1316
1317 emc->debugfs.max_rate = rate;
1318
1319 return 0;
1320}
1321
1322DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
1323 tegra_emc_debug_max_rate_get,
1324 tegra_emc_debug_max_rate_set, "%llu\n");
1325
1326static void tegra_emc_debugfs_init(struct tegra_emc *emc)
1327{
1328 struct device *dev = emc->dev;
1329 unsigned int i;
1330 int err;
1331
1332 emc->debugfs.min_rate = ULONG_MAX;
1333 emc->debugfs.max_rate = 0;
1334
1335 for (i = 0; i < emc->num_timings; i++) {
1336 if (emc->timings[i].rate < emc->debugfs.min_rate)
1337 emc->debugfs.min_rate = emc->timings[i].rate;
1338
1339 if (emc->timings[i].rate > emc->debugfs.max_rate)
1340 emc->debugfs.max_rate = emc->timings[i].rate;
1341 }
1342
1343 if (!emc->num_timings) {
1344 emc->debugfs.min_rate = clk_get_rate(emc->clk);
1345 emc->debugfs.max_rate = emc->debugfs.min_rate;
1346 }
1347
1348 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
1349 emc->debugfs.max_rate);
1350 if (err < 0) {
1351 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
1352 emc->debugfs.min_rate, emc->debugfs.max_rate,
1353 emc->clk);
1354 }
1355
1356 emc->debugfs.root = debugfs_create_dir("emc", NULL);
1357 if (!emc->debugfs.root) {
1358 dev_err(emc->dev, "failed to create debugfs directory\n");
1359 return;
1360 }
1361
1362 debugfs_create_file("available_rates", 0444, emc->debugfs.root,
1363 emc, &tegra_emc_debug_available_rates_fops);
1364 debugfs_create_file("min_rate", 0644, emc->debugfs.root,
1365 emc, &tegra_emc_debug_min_rate_fops);
1366 debugfs_create_file("max_rate", 0644, emc->debugfs.root,
1367 emc, &tegra_emc_debug_max_rate_fops);
1368}
1369
1370static inline struct tegra_emc *
1371to_tegra_emc_provider(struct icc_provider *provider)
1372{
1373 return container_of(provider, struct tegra_emc, provider);
1374}
1375
1376static struct icc_node_data *
1377emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1378{
1379 struct icc_provider *provider = data;
1380 struct icc_node_data *ndata;
1381 struct icc_node *node;
1382
1383
1384 list_for_each_entry(node, &provider->nodes, node_list) {
1385 if (node->id != TEGRA_ICC_EMEM)
1386 continue;
1387
1388 ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
1389 if (!ndata)
1390 return ERR_PTR(-ENOMEM);
1391
1392
1393
1394
1395
1396 ndata->tag = TEGRA_MC_ICC_TAG_ISO;
1397 ndata->node = node;
1398
1399 return ndata;
1400 }
1401
1402 return ERR_PTR(-EPROBE_DEFER);
1403}
1404
1405static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
1406{
1407 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
1408 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
1409 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
1410 unsigned long long rate = max(avg_bw, peak_bw);
1411 const unsigned int dram_data_bus_width_bytes = 4;
1412 const unsigned int ddr = 2;
1413 int err;
1414
1415
1416
1417
1418
1419
1420 do_div(rate, ddr * dram_data_bus_width_bytes);
1421 rate = min_t(u64, rate, U32_MAX);
1422
1423 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
1424 if (err)
1425 return err;
1426
1427 return 0;
1428}
1429
1430static int tegra_emc_interconnect_init(struct tegra_emc *emc)
1431{
1432 const struct tegra_mc_soc *soc = emc->mc->soc;
1433 struct icc_node *node;
1434 int err;
1435
1436 emc->provider.dev = emc->dev;
1437 emc->provider.set = emc_icc_set;
1438 emc->provider.data = &emc->provider;
1439 emc->provider.aggregate = soc->icc_ops->aggregate;
1440 emc->provider.xlate_extended = emc_of_icc_xlate_extended;
1441
1442 err = icc_provider_add(&emc->provider);
1443 if (err)
1444 goto err_msg;
1445
1446
1447 node = icc_node_create(TEGRA_ICC_EMC);
1448 if (IS_ERR(node)) {
1449 err = PTR_ERR(node);
1450 goto del_provider;
1451 }
1452
1453 node->name = "External Memory Controller";
1454 icc_node_add(node, &emc->provider);
1455
1456
1457 err = icc_link_create(node, TEGRA_ICC_EMEM);
1458 if (err)
1459 goto remove_nodes;
1460
1461
1462 node = icc_node_create(TEGRA_ICC_EMEM);
1463 if (IS_ERR(node)) {
1464 err = PTR_ERR(node);
1465 goto remove_nodes;
1466 }
1467
1468 node->name = "External Memory (DRAM)";
1469 icc_node_add(node, &emc->provider);
1470
1471 return 0;
1472
1473remove_nodes:
1474 icc_nodes_remove(&emc->provider);
1475del_provider:
1476 icc_provider_del(&emc->provider);
1477err_msg:
1478 dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
1479
1480 return err;
1481}
1482
1483static int tegra_emc_opp_table_init(struct tegra_emc *emc)
1484{
1485 u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
1486 struct opp_table *hw_opp_table;
1487 int err;
1488
1489 hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
1490 err = PTR_ERR_OR_ZERO(hw_opp_table);
1491 if (err) {
1492 dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
1493 return err;
1494 }
1495
1496 err = dev_pm_opp_of_add_table(emc->dev);
1497 if (err) {
1498 if (err == -ENODEV)
1499 dev_err(emc->dev, "OPP table not found, please update your device tree\n");
1500 else
1501 dev_err(emc->dev, "failed to add OPP table: %d\n", err);
1502
1503 goto put_hw_table;
1504 }
1505
1506 dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
1507 hw_version, clk_get_rate(emc->clk) / 1000000);
1508
1509
1510 err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
1511 if (err) {
1512 dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err);
1513 goto remove_table;
1514 }
1515
1516 return 0;
1517
1518remove_table:
1519 dev_pm_opp_of_remove_table(emc->dev);
1520put_hw_table:
1521 dev_pm_opp_put_supported_hw(hw_opp_table);
1522
1523 return err;
1524}
1525
1526static void devm_tegra_emc_unset_callback(void *data)
1527{
1528 tegra20_clk_set_emc_round_callback(NULL, NULL);
1529}
1530
1531static void devm_tegra_emc_unreg_clk_notifier(void *data)
1532{
1533 struct tegra_emc *emc = data;
1534
1535 clk_notifier_unregister(emc->clk, &emc->clk_nb);
1536}
1537
1538static int tegra_emc_init_clk(struct tegra_emc *emc)
1539{
1540 int err;
1541
1542 tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
1543
1544 err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback,
1545 NULL);
1546 if (err)
1547 return err;
1548
1549 emc->clk = devm_clk_get(emc->dev, NULL);
1550 if (IS_ERR(emc->clk)) {
1551 dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk);
1552 return PTR_ERR(emc->clk);
1553 }
1554
1555 err = clk_notifier_register(emc->clk, &emc->clk_nb);
1556 if (err) {
1557 dev_err(emc->dev, "failed to register clk notifier: %d\n", err);
1558 return err;
1559 }
1560
1561 err = devm_add_action_or_reset(emc->dev,
1562 devm_tegra_emc_unreg_clk_notifier, emc);
1563 if (err)
1564 return err;
1565
1566 return 0;
1567}
1568
1569static int tegra_emc_probe(struct platform_device *pdev)
1570{
1571 struct device_node *np;
1572 struct tegra_emc *emc;
1573 int err;
1574
1575 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1576 if (!emc)
1577 return -ENOMEM;
1578
1579 emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
1580 if (IS_ERR(emc->mc))
1581 return PTR_ERR(emc->mc);
1582
1583 mutex_init(&emc->rate_lock);
1584 emc->clk_nb.notifier_call = emc_clk_change_notify;
1585 emc->dev = &pdev->dev;
1586
1587 np = emc_find_node_by_ram_code(&pdev->dev);
1588 if (np) {
1589 err = emc_load_timings_from_dt(emc, np);
1590 of_node_put(np);
1591 if (err)
1592 return err;
1593 }
1594
1595 emc->regs = devm_platform_ioremap_resource(pdev, 0);
1596 if (IS_ERR(emc->regs))
1597 return PTR_ERR(emc->regs);
1598
1599 err = emc_setup_hw(emc);
1600 if (err)
1601 return err;
1602
1603 err = platform_get_irq(pdev, 0);
1604 if (err < 0)
1605 return err;
1606
1607 emc->irq = err;
1608
1609 err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0,
1610 dev_name(&pdev->dev), emc);
1611 if (err) {
1612 dev_err(&pdev->dev, "failed to request irq: %d\n", err);
1613 return err;
1614 }
1615
1616 err = tegra_emc_init_clk(emc);
1617 if (err)
1618 return err;
1619
1620 err = tegra_emc_opp_table_init(emc);
1621 if (err)
1622 return err;
1623
1624 platform_set_drvdata(pdev, emc);
1625 tegra_emc_rate_requests_init(emc);
1626 tegra_emc_debugfs_init(emc);
1627 tegra_emc_interconnect_init(emc);
1628
1629
1630
1631
1632
1633
1634 try_module_get(THIS_MODULE);
1635
1636 return 0;
1637}
1638
1639static int tegra_emc_suspend(struct device *dev)
1640{
1641 struct tegra_emc *emc = dev_get_drvdata(dev);
1642 int err;
1643
1644
1645 err = clk_rate_exclusive_get(emc->clk);
1646 if (err) {
1647 dev_err(emc->dev, "failed to acquire clk: %d\n", err);
1648 return err;
1649 }
1650
1651
1652 if (WARN(emc->bad_state, "hardware in a bad state\n"))
1653 return -EINVAL;
1654
1655 emc->bad_state = true;
1656
1657 return 0;
1658}
1659
1660static int tegra_emc_resume(struct device *dev)
1661{
1662 struct tegra_emc *emc = dev_get_drvdata(dev);
1663
1664 emc_setup_hw(emc);
1665 emc->bad_state = false;
1666
1667 clk_rate_exclusive_put(emc->clk);
1668
1669 return 0;
1670}
1671
1672static const struct dev_pm_ops tegra_emc_pm_ops = {
1673 .suspend = tegra_emc_suspend,
1674 .resume = tegra_emc_resume,
1675};
1676
1677static const struct of_device_id tegra_emc_of_match[] = {
1678 { .compatible = "nvidia,tegra30-emc", },
1679 {},
1680};
1681MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
1682
1683static struct platform_driver tegra_emc_driver = {
1684 .probe = tegra_emc_probe,
1685 .driver = {
1686 .name = "tegra30-emc",
1687 .of_match_table = tegra_emc_of_match,
1688 .pm = &tegra_emc_pm_ops,
1689 .suppress_bind_attrs = true,
1690 .sync_state = icc_sync_state,
1691 },
1692};
1693module_platform_driver(tegra_emc_driver);
1694
1695MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
1696MODULE_DESCRIPTION("NVIDIA Tegra30 EMC driver");
1697MODULE_LICENSE("GPL v2");
1698
