1
2
3
4#ifndef LINUX_MMC_CQHCI_H
5#define LINUX_MMC_CQHCI_H
6
7#include <linux/compiler.h>
8#include <linux/bitops.h>
9#include <linux/spinlock_types.h>
10#include <linux/types.h>
11#include <linux/completion.h>
12#include <linux/wait.h>
13#include <linux/irqreturn.h>
14#include <asm/io.h>
15
16
17
18#define CQHCI_VER 0x00
19#define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8)
20#define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4)
21#define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0))
22
23
24#define CQHCI_CAP 0x04
25#define CQHCI_CAP_CS 0x10000000
26
27
28#define CQHCI_CFG 0x08
29#define CQHCI_DCMD 0x00001000
30#define CQHCI_TASK_DESC_SZ 0x00000100
31#define CQHCI_CRYPTO_GENERAL_ENABLE 0x00000002
32#define CQHCI_ENABLE 0x00000001
33
34
35#define CQHCI_CTL 0x0C
36#define CQHCI_CLEAR_ALL_TASKS 0x00000100
37#define CQHCI_HALT 0x00000001
38
39
40#define CQHCI_IS 0x10
41#define CQHCI_IS_HAC BIT(0)
42#define CQHCI_IS_TCC BIT(1)
43#define CQHCI_IS_RED BIT(2)
44#define CQHCI_IS_TCL BIT(3)
45#define CQHCI_IS_GCE BIT(4)
46#define CQHCI_IS_ICCE BIT(5)
47
48#define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED | \
49 CQHCI_IS_GCE | CQHCI_IS_ICCE)
50
51
52#define CQHCI_ISTE 0x14
53
54
55#define CQHCI_ISGE 0x18
56
57
58#define CQHCI_IC 0x1C
59#define CQHCI_IC_ENABLE BIT(31)
60#define CQHCI_IC_RESET BIT(16)
61#define CQHCI_IC_ICCTHWEN BIT(15)
62#define CQHCI_IC_ICCTH(x) (((x) & 0x1F) << 8)
63#define CQHCI_IC_ICTOVALWEN BIT(7)
64#define CQHCI_IC_ICTOVAL(x) ((x) & 0x7F)
65
66
67#define CQHCI_TDLBA 0x20
68
69
70#define CQHCI_TDLBAU 0x24
71
72
73#define CQHCI_TDBR 0x28
74
75
76#define CQHCI_TCN 0x2C
77
78
79#define CQHCI_DQS 0x30
80
81
82#define CQHCI_DPT 0x34
83
84
85#define CQHCI_TCLR 0x38
86
87
88#define CQHCI_TDPE 0x3c
89
90
91#define CQHCI_SSC1 0x40
92#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
93
94
95#define CQHCI_SSC2 0x44
96
97
98#define CQHCI_CRDCT 0x48
99
100
101#define CQHCI_RMEM 0x50
102
103
104#define CQHCI_TERRI 0x54
105
106#define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0))
107#define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8)
108#define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15))
109#define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16)
110#define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24)
111#define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31))
112
113
114#define CQHCI_CRI 0x58
115
116
117#define CQHCI_CRA 0x5C
118
119
120#define CQHCI_CCAP 0x100
121#define CQHCI_CRYPTOCAP 0x104
122
123#define CQHCI_INT_ALL 0xF
124#define CQHCI_IC_DEFAULT_ICCTH 31
125#define CQHCI_IC_DEFAULT_ICTOVAL 1
126
127
128#define CQHCI_VALID(x) (((x) & 1) << 0)
129#define CQHCI_END(x) (((x) & 1) << 1)
130#define CQHCI_INT(x) (((x) & 1) << 2)
131#define CQHCI_ACT(x) (((x) & 0x7) << 3)
132
133
134#define CQHCI_FORCED_PROG(x) (((x) & 1) << 6)
135#define CQHCI_CONTEXT(x) (((x) & 0xF) << 7)
136#define CQHCI_DATA_TAG(x) (((x) & 1) << 11)
137#define CQHCI_DATA_DIR(x) (((x) & 1) << 12)
138#define CQHCI_PRIORITY(x) (((x) & 1) << 13)
139#define CQHCI_QBAR(x) (((x) & 1) << 14)
140#define CQHCI_REL_WRITE(x) (((x) & 1) << 15)
141#define CQHCI_BLK_COUNT(x) (((x) & 0xFFFF) << 16)
142#define CQHCI_BLK_ADDR(x) (((x) & 0xFFFFFFFF) << 32)
143
144
145#define CQHCI_CMD_INDEX(x) (((x) & 0x3F) << 16)
146#define CQHCI_CMD_TIMING(x) (((x) & 1) << 22)
147#define CQHCI_RESP_TYPE(x) (((x) & 0x3) << 23)
148
149
150#define CQHCI_CRYPTO_ENABLE_BIT (1ULL << 47)
151#define CQHCI_CRYPTO_KEYSLOT(x) ((u64)(x) << 32)
152
153
154#define CQHCI_DAT_LENGTH(x) (((x) & 0xFFFF) << 16)
155#define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32)
156#define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0)
157
158
159union cqhci_crypto_capabilities {
160 __le32 reg_val;
161 struct {
162 u8 num_crypto_cap;
163 u8 config_count;
164 u8 reserved;
165 u8 config_array_ptr;
166 };
167};
168
169enum cqhci_crypto_key_size {
170 CQHCI_CRYPTO_KEY_SIZE_INVALID = 0,
171 CQHCI_CRYPTO_KEY_SIZE_128 = 1,
172 CQHCI_CRYPTO_KEY_SIZE_192 = 2,
173 CQHCI_CRYPTO_KEY_SIZE_256 = 3,
174 CQHCI_CRYPTO_KEY_SIZE_512 = 4,
175};
176
177enum cqhci_crypto_alg {
178 CQHCI_CRYPTO_ALG_AES_XTS = 0,
179 CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC = 1,
180 CQHCI_CRYPTO_ALG_AES_ECB = 2,
181 CQHCI_CRYPTO_ALG_ESSIV_AES_CBC = 3,
182};
183
184
185union cqhci_crypto_cap_entry {
186 __le32 reg_val;
187 struct {
188 u8 algorithm_id;
189 u8 sdus_mask;
190 u8 key_size;
191 u8 reserved;
192 };
193};
194
195#define CQHCI_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
196#define CQHCI_CRYPTO_KEY_MAX_SIZE 64
197
198union cqhci_crypto_cfg_entry {
199 __le32 reg_val[32];
200 struct {
201 u8 crypto_key[CQHCI_CRYPTO_KEY_MAX_SIZE];
202 u8 data_unit_size;
203 u8 crypto_cap_idx;
204 u8 reserved_1;
205 u8 config_enable;
206 u8 reserved_multi_host;
207 u8 reserved_2;
208 u8 vsb[2];
209 u8 reserved_3[56];
210 };
211};
212
213struct cqhci_host_ops;
214struct mmc_host;
215struct mmc_request;
216struct cqhci_slot;
217
218struct cqhci_host {
219 const struct cqhci_host_ops *ops;
220 void __iomem *mmio;
221 struct mmc_host *mmc;
222
223 spinlock_t lock;
224
225
226 unsigned int rca;
227
228
229 bool dma64;
230 int num_slots;
231 int qcnt;
232
233 u32 dcmd_slot;
234 u32 caps;
235#define CQHCI_TASK_DESC_SZ_128 0x1
236
237 u32 quirks;
238#define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1
239
240 bool enabled;
241 bool halted;
242 bool init_done;
243 bool activated;
244 bool waiting_for_idle;
245 bool recovery_halt;
246
247 size_t desc_size;
248 size_t data_size;
249
250 u8 *desc_base;
251
252
253 u8 slot_sz;
254
255
256 u8 task_desc_len;
257
258
259 u8 link_desc_len;
260
261 u8 *trans_desc_base;
262
263 u8 trans_desc_len;
264
265 dma_addr_t desc_dma_base;
266 dma_addr_t trans_desc_dma_base;
267
268 struct completion halt_comp;
269 wait_queue_head_t wait_queue;
270 struct cqhci_slot *slot;
271
272#ifdef CONFIG_MMC_CRYPTO
273 union cqhci_crypto_capabilities crypto_capabilities;
274 union cqhci_crypto_cap_entry *crypto_cap_array;
275 u32 crypto_cfg_register;
276#endif
277};
278
279struct cqhci_host_ops {
280 void (*dumpregs)(struct mmc_host *mmc);
281 void (*write_l)(struct cqhci_host *host, u32 val, int reg);
282 u32 (*read_l)(struct cqhci_host *host, int reg);
283 void (*enable)(struct mmc_host *mmc);
284 void (*disable)(struct mmc_host *mmc, bool recovery);
285 void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq,
286 u64 *data);
287 void (*pre_enable)(struct mmc_host *mmc);
288 void (*post_disable)(struct mmc_host *mmc);
289#ifdef CONFIG_MMC_CRYPTO
290 int (*program_key)(struct cqhci_host *cq_host,
291 const union cqhci_crypto_cfg_entry *cfg, int slot);
292#endif
293};
294
295static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
296{
297 if (unlikely(host->ops->write_l))
298 host->ops->write_l(host, val, reg);
299 else
300 writel_relaxed(val, host->mmio + reg);
301}
302
303static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
304{
305 if (unlikely(host->ops->read_l))
306 return host->ops->read_l(host, reg);
307 else
308 return readl_relaxed(host->mmio + reg);
309}
310
311struct platform_device;
312
313irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
314 int data_error);
315int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
316struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
317int cqhci_deactivate(struct mmc_host *mmc);
318static inline int cqhci_suspend(struct mmc_host *mmc)
319{
320 return cqhci_deactivate(mmc);
321}
322int cqhci_resume(struct mmc_host *mmc);
323
324#endif
325
