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35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include "t4_hw.h"
39
40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/ethtool.h>
43#include <linux/interrupt.h>
44#include <linux/list.h>
45#include <linux/netdevice.h>
46#include <linux/pci.h>
47#include <linux/spinlock.h>
48#include <linux/timer.h>
49#include <linux/vmalloc.h>
50#include <linux/rhashtable.h>
51#include <linux/etherdevice.h>
52#include <linux/net_tstamp.h>
53#include <linux/ptp_clock_kernel.h>
54#include <linux/ptp_classify.h>
55#include <linux/crash_dump.h>
56#include <linux/thermal.h>
57#include <asm/io.h>
58#include "t4_chip_type.h"
59#include "cxgb4_uld.h"
60#include "t4fw_api.h"
61
62#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
63extern struct list_head adapter_list;
64extern struct list_head uld_list;
65extern struct mutex uld_mutex;
66
67
68
69
70
71#define ETHTXQ_STOP_THRES \
72 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
73
74#define FW_PARAM_DEV(param) \
75 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
76 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
77
78#define FW_PARAM_PFVF(param) \
79 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
80 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \
81 FW_PARAMS_PARAM_Y_V(0) | \
82 FW_PARAMS_PARAM_Z_V(0))
83
84enum {
85 MAX_NPORTS = 4,
86 SERNUM_LEN = 24,
87 EC_LEN = 16,
88 ID_LEN = 16,
89 PN_LEN = 16,
90 MACADDR_LEN = 12,
91};
92
93enum {
94 T4_REGMAP_SIZE = (160 * 1024),
95 T5_REGMAP_SIZE = (332 * 1024),
96};
97
98enum {
99 MEM_EDC0,
100 MEM_EDC1,
101 MEM_MC,
102 MEM_MC0 = MEM_MC,
103 MEM_MC1,
104 MEM_HMA,
105};
106
107enum {
108 MEMWIN0_APERTURE = 2048,
109 MEMWIN0_BASE = 0x1b800,
110 MEMWIN1_APERTURE = 32768,
111 MEMWIN1_BASE = 0x28000,
112 MEMWIN1_BASE_T5 = 0x52000,
113 MEMWIN2_APERTURE = 65536,
114 MEMWIN2_BASE = 0x30000,
115 MEMWIN2_APERTURE_T5 = 131072,
116 MEMWIN2_BASE_T5 = 0x60000,
117};
118
119enum dev_master {
120 MASTER_CANT,
121 MASTER_MAY,
122 MASTER_MUST
123};
124
125enum dev_state {
126 DEV_STATE_UNINIT,
127 DEV_STATE_INIT,
128 DEV_STATE_ERR
129};
130
131enum cc_pause {
132 PAUSE_RX = 1 << 0,
133 PAUSE_TX = 1 << 1,
134 PAUSE_AUTONEG = 1 << 2
135};
136
137enum cc_fec {
138 FEC_AUTO = 1 << 0,
139 FEC_RS = 1 << 1,
140 FEC_BASER_RS = 1 << 2
141};
142
143enum {
144 CXGB4_ETHTOOL_FLASH_FW = 1,
145 CXGB4_ETHTOOL_FLASH_PHY = 2,
146 CXGB4_ETHTOOL_FLASH_BOOT = 3,
147 CXGB4_ETHTOOL_FLASH_BOOTCFG = 4
148};
149
150enum cxgb4_netdev_tls_ops {
151 CXGB4_TLSDEV_OPS = 1,
152 CXGB4_XFRMDEV_OPS
153};
154
155struct cxgb4_bootcfg_data {
156 __le16 signature;
157 __u8 reserved[2];
158};
159
160struct cxgb4_pcir_data {
161 __le32 signature;
162 __le16 vendor_id;
163 __le16 device_id;
164 __u8 vital_product[2];
165 __u8 length[2];
166 __u8 revision;
167 __u8 class_code[3];
168 __u8 image_length[2];
169 __u8 code_revision[2];
170 __u8 code_type;
171 __u8 indicator;
172 __u8 reserved[2];
173};
174
175
176struct cxgb4_pci_exp_rom_header {
177 __le16 signature;
178 __u8 reserved[22];
179 __le16 pcir_offset;
180};
181
182
183struct legacy_pci_rom_hdr {
184 __u8 signature[2];
185 __u8 size512;
186 __u8 initentry_point[4];
187 __u8 cksum;
188 __u8 reserved[16];
189 __le16 pcir_offset;
190};
191
192#define CXGB4_HDR_CODE1 0x00
193#define CXGB4_HDR_CODE2 0x03
194#define CXGB4_HDR_INDI 0x80
195
196
197enum {
198 BOOT_CFG_SIG = 0x4243,
199 BOOT_SIZE_INC = 512,
200 BOOT_SIGNATURE = 0xaa55,
201 BOOT_MIN_SIZE = sizeof(struct cxgb4_pci_exp_rom_header),
202 BOOT_MAX_SIZE = 1024 * BOOT_SIZE_INC,
203 PCIR_SIGNATURE = 0x52494350
204};
205
206struct port_stats {
207 u64 tx_octets;
208 u64 tx_frames;
209 u64 tx_bcast_frames;
210 u64 tx_mcast_frames;
211 u64 tx_ucast_frames;
212 u64 tx_error_frames;
213
214 u64 tx_frames_64;
215 u64 tx_frames_65_127;
216 u64 tx_frames_128_255;
217 u64 tx_frames_256_511;
218 u64 tx_frames_512_1023;
219 u64 tx_frames_1024_1518;
220 u64 tx_frames_1519_max;
221
222 u64 tx_drop;
223 u64 tx_pause;
224 u64 tx_ppp0;
225 u64 tx_ppp1;
226 u64 tx_ppp2;
227 u64 tx_ppp3;
228 u64 tx_ppp4;
229 u64 tx_ppp5;
230 u64 tx_ppp6;
231 u64 tx_ppp7;
232
233 u64 rx_octets;
234 u64 rx_frames;
235 u64 rx_bcast_frames;
236 u64 rx_mcast_frames;
237 u64 rx_ucast_frames;
238 u64 rx_too_long;
239 u64 rx_jabber;
240 u64 rx_fcs_err;
241 u64 rx_len_err;
242 u64 rx_symbol_err;
243 u64 rx_runt;
244
245 u64 rx_frames_64;
246 u64 rx_frames_65_127;
247 u64 rx_frames_128_255;
248 u64 rx_frames_256_511;
249 u64 rx_frames_512_1023;
250 u64 rx_frames_1024_1518;
251 u64 rx_frames_1519_max;
252
253 u64 rx_pause;
254 u64 rx_ppp0;
255 u64 rx_ppp1;
256 u64 rx_ppp2;
257 u64 rx_ppp3;
258 u64 rx_ppp4;
259 u64 rx_ppp5;
260 u64 rx_ppp6;
261 u64 rx_ppp7;
262
263 u64 rx_ovflow0;
264 u64 rx_ovflow1;
265 u64 rx_ovflow2;
266 u64 rx_ovflow3;
267 u64 rx_trunc0;
268 u64 rx_trunc1;
269 u64 rx_trunc2;
270 u64 rx_trunc3;
271};
272
273struct lb_port_stats {
274 u64 octets;
275 u64 frames;
276 u64 bcast_frames;
277 u64 mcast_frames;
278 u64 ucast_frames;
279 u64 error_frames;
280
281 u64 frames_64;
282 u64 frames_65_127;
283 u64 frames_128_255;
284 u64 frames_256_511;
285 u64 frames_512_1023;
286 u64 frames_1024_1518;
287 u64 frames_1519_max;
288
289 u64 drop;
290
291 u64 ovflow0;
292 u64 ovflow1;
293 u64 ovflow2;
294 u64 ovflow3;
295 u64 trunc0;
296 u64 trunc1;
297 u64 trunc2;
298 u64 trunc3;
299};
300
301struct tp_tcp_stats {
302 u32 tcp_out_rsts;
303 u64 tcp_in_segs;
304 u64 tcp_out_segs;
305 u64 tcp_retrans_segs;
306};
307
308struct tp_usm_stats {
309 u32 frames;
310 u32 drops;
311 u64 octets;
312};
313
314struct tp_fcoe_stats {
315 u32 frames_ddp;
316 u32 frames_drop;
317 u64 octets_ddp;
318};
319
320struct tp_err_stats {
321 u32 mac_in_errs[4];
322 u32 hdr_in_errs[4];
323 u32 tcp_in_errs[4];
324 u32 tnl_cong_drops[4];
325 u32 ofld_chan_drops[4];
326 u32 tnl_tx_drops[4];
327 u32 ofld_vlan_drops[4];
328 u32 tcp6_in_errs[4];
329 u32 ofld_no_neigh;
330 u32 ofld_cong_defer;
331};
332
333struct tp_cpl_stats {
334 u32 req[4];
335 u32 rsp[4];
336};
337
338struct tp_rdma_stats {
339 u32 rqe_dfr_pkt;
340 u32 rqe_dfr_mod;
341};
342
343struct sge_params {
344 u32 hps;
345 u32 eq_qpp;
346 u32 iq_qpp;
347};
348
349struct tp_params {
350 unsigned int tre;
351 unsigned int la_mask;
352 unsigned short tx_modq_map;
353
354
355 uint32_t dack_re;
356 unsigned short tx_modq[NCHAN];
357
358 u32 vlan_pri_map;
359 u32 filter_mask;
360 u32 ingress_config;
361
362
363
364
365 int rx_pkt_encap;
366
367
368
369
370
371
372
373
374
375
376
377
378 int fcoe_shift;
379 int port_shift;
380 int vnic_shift;
381 int vlan_shift;
382 int tos_shift;
383 int protocol_shift;
384 int ethertype_shift;
385 int macmatch_shift;
386 int matchtype_shift;
387 int frag_shift;
388
389 u64 hash_filter_mask;
390};
391
392struct vpd_params {
393 unsigned int cclk;
394 u8 ec[EC_LEN + 1];
395 u8 sn[SERNUM_LEN + 1];
396 u8 id[ID_LEN + 1];
397 u8 pn[PN_LEN + 1];
398 u8 na[MACADDR_LEN + 1];
399};
400
401
402
403struct pf_resources {
404 unsigned int nvi;
405 unsigned int neq;
406 unsigned int nethctrl;
407 unsigned int niqflint;
408 unsigned int niq;
409 unsigned int tc;
410 unsigned int pmask;
411 unsigned int nexactf;
412 unsigned int r_caps;
413 unsigned int wx_caps;
414};
415
416struct pci_params {
417 unsigned char speed;
418 unsigned char width;
419};
420
421struct devlog_params {
422 u32 memtype;
423 u32 start;
424 u32 size;
425};
426
427
428struct arch_specific_params {
429 u8 nchan;
430 u8 pm_stats_cnt;
431 u8 cng_ch_bits_log;
432 u16 mps_rplc_size;
433 u16 vfcount;
434 u32 sge_fl_db;
435 u16 mps_tcam_size;
436};
437
438struct adapter_params {
439 struct sge_params sge;
440 struct tp_params tp;
441 struct vpd_params vpd;
442 struct pf_resources pfres;
443 struct pci_params pci;
444 struct devlog_params devlog;
445 enum pcie_memwin drv_memwin;
446
447 unsigned int cim_la_size;
448
449 unsigned int sf_size;
450 unsigned int sf_nsec;
451
452 unsigned int fw_vers;
453 unsigned int bs_vers;
454 unsigned int tp_vers;
455 unsigned int er_vers;
456 unsigned int scfg_vers;
457 unsigned int vpd_vers;
458 u8 api_vers[7];
459
460 unsigned short mtus[NMTUS];
461 unsigned short a_wnd[NCCTRL_WIN];
462 unsigned short b_wnd[NCCTRL_WIN];
463
464 unsigned char nports;
465 unsigned char portvec;
466 enum chip_type chip;
467 struct arch_specific_params arch;
468 unsigned char offload;
469 unsigned char crypto;
470 unsigned char ethofld;
471
472 unsigned char bypass;
473 unsigned char hash_filter;
474
475 unsigned int ofldq_wr_cred;
476 bool ulptx_memwrite_dsgl;
477
478 unsigned int nsched_cls;
479 unsigned int max_ordird_qp;
480 unsigned int max_ird_adapter;
481 bool fr_nsmr_tpte_wr_support;
482 u8 fw_caps_support;
483 bool filter2_wr_support;
484 unsigned int viid_smt_extn_support:1;
485
486
487
488
489 u8 mps_bg_map[MAX_NPORTS];
490 bool write_w_imm_support;
491 bool write_cmpl_support;
492};
493
494
495
496
497struct sge_idma_monitor_state {
498 unsigned int idma_1s_thresh;
499 unsigned int idma_stalled[2];
500 unsigned int idma_state[2];
501 unsigned int idma_qid[2];
502 unsigned int idma_warn[2];
503};
504
505
506
507
508
509struct mbox_cmd {
510 u64 cmd[MBOX_LEN / 8];
511 u64 timestamp;
512 u32 seqno;
513 s16 access;
514 s16 execute;
515};
516
517struct mbox_cmd_log {
518 unsigned int size;
519 unsigned int cursor;
520 u32 seqno;
521
522};
523
524
525
526
527static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
528 unsigned int entry_idx)
529{
530 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
531}
532
533#define FW_VERSION(chip) ( \
534 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
535 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
536 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
537 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
538#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
539
540struct cxgb4_ethtool_lb_test {
541 struct completion completion;
542 int result;
543 int loopback;
544};
545
546struct fw_info {
547 u8 chip;
548 char *fs_name;
549 char *fw_mod_name;
550 struct fw_hdr fw_hdr;
551};
552
553struct trace_params {
554 u32 data[TRACE_LEN / 4];
555 u32 mask[TRACE_LEN / 4];
556 unsigned short snap_len;
557 unsigned short min_len;
558 unsigned char skip_ofst;
559 unsigned char skip_len;
560 unsigned char invert;
561 unsigned char port;
562};
563
564struct cxgb4_fw_data {
565 __be32 signature;
566 __u8 reserved[4];
567};
568
569
570
571typedef u16 fw_port_cap16_t;
572typedef u32 fw_port_cap32_t;
573
574enum fw_caps {
575 FW_CAPS_UNKNOWN = 0,
576 FW_CAPS16 = 1,
577 FW_CAPS32 = 2,
578};
579
580struct link_config {
581 fw_port_cap32_t pcaps;
582 fw_port_cap32_t def_acaps;
583 fw_port_cap32_t acaps;
584 fw_port_cap32_t lpacaps;
585
586 fw_port_cap32_t speed_caps;
587 unsigned int speed;
588
589 enum cc_pause requested_fc;
590 enum cc_pause fc;
591 enum cc_pause advertised_fc;
592
593 enum cc_fec requested_fec;
594 enum cc_fec fec;
595
596 unsigned char autoneg;
597
598 unsigned char link_ok;
599 unsigned char link_down_rc;
600
601 bool new_module;
602 bool redo_l1cfg;
603};
604
605#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
606
607enum {
608 MAX_ETH_QSETS = 32,
609 MAX_OFLD_QSETS = 16,
610 MAX_CTRL_QUEUES = NCHAN,
611};
612
613enum {
614 MAX_TXQ_ENTRIES = 16384,
615 MAX_CTRL_TXQ_ENTRIES = 1024,
616 MAX_RSPQ_ENTRIES = 16384,
617 MAX_RX_BUFFERS = 16384,
618 MIN_TXQ_ENTRIES = 32,
619 MIN_CTRL_TXQ_ENTRIES = 32,
620 MIN_RSPQ_ENTRIES = 128,
621 MIN_FL_ENTRIES = 16
622};
623
624enum {
625 MAX_TXQ_DESC_SIZE = 64,
626 MAX_RXQ_DESC_SIZE = 128,
627 MAX_FL_DESC_SIZE = 8,
628 MAX_CTRL_TXQ_DESC_SIZE = 64,
629};
630
631enum {
632 INGQ_EXTRAS = 2,
633
634 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
635};
636
637enum {
638 PRIV_FLAG_PORT_TX_VM_BIT,
639};
640
641#define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
642
643#define PRIV_FLAGS_ADAP 0
644#define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
645
646struct adapter;
647struct sge_rspq;
648
649#include "cxgb4_dcb.h"
650
651#ifdef CONFIG_CHELSIO_T4_FCOE
652#include "cxgb4_fcoe.h"
653#endif
654
655struct port_info {
656 struct adapter *adapter;
657 u16 viid;
658 int xact_addr_filt;
659 u16 rss_size;
660 s8 mdio_addr;
661 enum fw_port_type port_type;
662 u8 mod_type;
663 u8 port_id;
664 u8 tx_chan;
665 u8 lport;
666 u8 nqsets;
667 u8 first_qset;
668 u8 rss_mode;
669 struct link_config link_cfg;
670 u16 *rss;
671 struct port_stats stats_base;
672#ifdef CONFIG_CHELSIO_T4_DCB
673 struct port_dcb_info dcb;
674#endif
675#ifdef CONFIG_CHELSIO_T4_FCOE
676 struct cxgb_fcoe fcoe;
677#endif
678 bool rxtstamp;
679 struct hwtstamp_config tstamp_config;
680 bool ptp_enable;
681 struct sched_table *sched_tbl;
682 u32 eth_flags;
683
684
685
686
687 u8 vin;
688 u8 vivld;
689 u8 smt_idx;
690 u8 rx_cchan;
691
692 bool tc_block_shared;
693
694
695 u16 viid_mirror;
696 u16 nmirrorqsets;
697 u32 vi_mirror_count;
698 struct mutex vi_mirror_mutex;
699 struct cxgb4_ethtool_lb_test ethtool_lb;
700};
701
702struct dentry;
703struct work_struct;
704
705enum {
706 CXGB4_FULL_INIT_DONE = (1 << 0),
707 CXGB4_DEV_ENABLED = (1 << 1),
708 CXGB4_USING_MSI = (1 << 2),
709 CXGB4_USING_MSIX = (1 << 3),
710 CXGB4_FW_OK = (1 << 4),
711 CXGB4_RSS_TNLALLLOOKUP = (1 << 5),
712 CXGB4_USING_SOFT_PARAMS = (1 << 6),
713 CXGB4_MASTER_PF = (1 << 7),
714 CXGB4_FW_OFLD_CONN = (1 << 9),
715 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10),
716 CXGB4_SHUTTING_DOWN = (1 << 11),
717 CXGB4_SGE_DBQ_TIMER = (1 << 12),
718};
719
720enum {
721 ULP_CRYPTO_LOOKASIDE = 1 << 0,
722 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
723 ULP_CRYPTO_KTLS_INLINE = 1 << 3,
724};
725
726#define CXGB4_MIRROR_RXQ_DEFAULT_DESC_NUM 1024
727#define CXGB4_MIRROR_RXQ_DEFAULT_DESC_SIZE 64
728#define CXGB4_MIRROR_RXQ_DEFAULT_INTR_USEC 5
729#define CXGB4_MIRROR_RXQ_DEFAULT_PKT_CNT 8
730
731#define CXGB4_MIRROR_FLQ_DEFAULT_DESC_NUM 72
732
733struct rx_sw_desc;
734
735struct sge_fl {
736 unsigned int avail;
737 unsigned int pend_cred;
738 unsigned int cidx;
739 unsigned int pidx;
740 unsigned long alloc_failed;
741 unsigned long large_alloc_failed;
742 unsigned long mapping_err;
743 unsigned long low;
744 unsigned long starving;
745
746 unsigned int cntxt_id;
747 unsigned int size;
748 struct rx_sw_desc *sdesc;
749 __be64 *desc;
750 dma_addr_t addr;
751 void __iomem *bar2_addr;
752 unsigned int bar2_qid;
753};
754
755
756struct pkt_gl {
757 u64 sgetstamp;
758 struct page_frag frags[MAX_SKB_FRAGS];
759 void *va;
760 unsigned int nfrags;
761 unsigned int tot_len;
762};
763
764typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
765 const struct pkt_gl *gl);
766typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
767
768struct t4_lro_mgr {
769#define MAX_LRO_SESSIONS 64
770 u8 lro_session_cnt;
771 unsigned long lro_pkts;
772 unsigned long lro_merged;
773 struct sk_buff_head lroq;
774};
775
776struct sge_rspq {
777 struct napi_struct napi;
778 const __be64 *cur_desc;
779 unsigned int cidx;
780 u8 gen;
781 u8 intr_params;
782 u8 next_intr_params;
783 u8 adaptive_rx;
784 u8 pktcnt_idx;
785 u8 uld;
786 u8 idx;
787 int offset;
788 u16 cntxt_id;
789 u16 abs_id;
790 __be64 *desc;
791 dma_addr_t phys_addr;
792 void __iomem *bar2_addr;
793 unsigned int bar2_qid;
794 unsigned int iqe_len;
795 unsigned int size;
796 struct adapter *adap;
797 struct net_device *netdev;
798 rspq_handler_t handler;
799 rspq_flush_handler_t flush_handler;
800 struct t4_lro_mgr lro_mgr;
801};
802
803struct sge_eth_stats {
804 unsigned long pkts;
805 unsigned long lro_pkts;
806 unsigned long lro_merged;
807 unsigned long rx_cso;
808 unsigned long vlan_ex;
809 unsigned long rx_drops;
810 unsigned long bad_rx_pkts;
811};
812
813struct sge_eth_rxq {
814 struct sge_rspq rspq;
815 struct sge_fl fl;
816 struct sge_eth_stats stats;
817 struct msix_info *msix;
818} ____cacheline_aligned_in_smp;
819
820struct sge_ofld_stats {
821 unsigned long pkts;
822 unsigned long imm;
823 unsigned long an;
824 unsigned long nomem;
825};
826
827struct sge_ofld_rxq {
828 struct sge_rspq rspq;
829 struct sge_fl fl;
830 struct sge_ofld_stats stats;
831 struct msix_info *msix;
832} ____cacheline_aligned_in_smp;
833
834struct tx_desc {
835 __be64 flit[8];
836};
837
838struct ulptx_sgl;
839
840struct tx_sw_desc {
841 struct sk_buff *skb;
842 dma_addr_t addr[MAX_SKB_FRAGS + 1];
843};
844
845struct sge_txq {
846 unsigned int in_use;
847 unsigned int q_type;
848 unsigned int size;
849 unsigned int cidx;
850 unsigned int pidx;
851 unsigned long stops;
852 unsigned long restarts;
853 unsigned int cntxt_id;
854 struct tx_desc *desc;
855 struct tx_sw_desc *sdesc;
856 struct sge_qstat *stat;
857 dma_addr_t phys_addr;
858 spinlock_t db_lock;
859 int db_disabled;
860 unsigned short db_pidx;
861 unsigned short db_pidx_inc;
862 void __iomem *bar2_addr;
863 unsigned int bar2_qid;
864};
865
866struct sge_eth_txq {
867 struct sge_txq q;
868 struct netdev_queue *txq;
869#ifdef CONFIG_CHELSIO_T4_DCB
870 u8 dcb_prio;
871#endif
872 u8 dbqt;
873 unsigned int dbqtimerix;
874 unsigned long tso;
875 unsigned long uso;
876 unsigned long tx_cso;
877 unsigned long vlan_ins;
878 unsigned long mapping_err;
879} ____cacheline_aligned_in_smp;
880
881struct sge_uld_txq {
882 struct sge_txq q;
883 struct adapter *adap;
884 struct sk_buff_head sendq;
885 struct tasklet_struct qresume_tsk;
886 bool service_ofldq_running;
887 u8 full;
888 unsigned long mapping_err;
889} ____cacheline_aligned_in_smp;
890
891struct sge_ctrl_txq {
892 struct sge_txq q;
893 struct adapter *adap;
894 struct sk_buff_head sendq;
895 struct tasklet_struct qresume_tsk;
896 u8 full;
897} ____cacheline_aligned_in_smp;
898
899struct sge_uld_rxq_info {
900 char name[IFNAMSIZ];
901 struct sge_ofld_rxq *uldrxq;
902 u16 *rspq_id;
903 u16 nrxq;
904 u16 nciq;
905 u8 uld;
906};
907
908struct sge_uld_txq_info {
909 struct sge_uld_txq *uldtxq;
910 atomic_t users;
911 u16 ntxq;
912};
913
914
915struct cxgb4_uld_list {
916 struct cxgb4_uld_info uld_info;
917 struct list_head list_node;
918 enum cxgb4_uld uld_type;
919};
920
921enum sge_eosw_state {
922 CXGB4_EO_STATE_CLOSED = 0,
923 CXGB4_EO_STATE_FLOWC_OPEN_SEND,
924 CXGB4_EO_STATE_FLOWC_OPEN_REPLY,
925 CXGB4_EO_STATE_ACTIVE,
926 CXGB4_EO_STATE_FLOWC_CLOSE_SEND,
927 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY,
928};
929
930struct sge_eosw_txq {
931 spinlock_t lock;
932 enum sge_eosw_state state;
933 struct tx_sw_desc *desc;
934 u32 ndesc;
935 u32 pidx;
936 u32 last_pidx;
937 u32 cidx;
938 u32 last_cidx;
939 u32 flowc_idx;
940 u32 inuse;
941
942 u32 cred;
943 u32 ncompl;
944 u32 last_compl;
945
946 u32 eotid;
947 u32 hwtid;
948
949 u32 hwqid;
950 struct net_device *netdev;
951 struct tasklet_struct qresume_tsk;
952 struct completion completion;
953};
954
955struct sge_eohw_txq {
956 spinlock_t lock;
957 struct sge_txq q;
958 struct adapter *adap;
959 unsigned long tso;
960 unsigned long uso;
961 unsigned long tx_cso;
962 unsigned long vlan_ins;
963 unsigned long mapping_err;
964};
965
966struct sge {
967 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
968 struct sge_eth_txq ptptxq;
969 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
970
971 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
972 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
973 struct sge_uld_rxq_info **uld_rxq_info;
974 struct sge_uld_txq_info **uld_txq_info;
975
976 struct sge_rspq intrq ____cacheline_aligned_in_smp;
977 spinlock_t intrq_lock;
978
979 struct sge_eohw_txq *eohw_txq;
980 struct sge_ofld_rxq *eohw_rxq;
981
982 struct sge_eth_rxq *mirror_rxq[NCHAN];
983
984 u16 max_ethqsets;
985 u16 ethqsets;
986 u16 ethtxq_rover;
987 u16 ofldqsets;
988 u16 nqs_per_uld;
989 u16 eoqsets;
990 u16 mirrorqsets;
991
992 u16 timer_val[SGE_NTIMERS];
993 u8 counter_val[SGE_NCOUNTERS];
994 u16 dbqtimer_tick;
995 u16 dbqtimer_val[SGE_NDBQTIMERS];
996 u32 fl_pg_order;
997 u32 stat_len;
998 u32 pktshift;
999 u32 fl_align;
1000 u32 fl_starve_thres;
1001
1002 struct sge_idma_monitor_state idma_monitor;
1003 unsigned int egr_start;
1004 unsigned int egr_sz;
1005 unsigned int ingr_start;
1006 unsigned int ingr_sz;
1007 void **egr_map;
1008 struct sge_rspq **ingr_map;
1009 unsigned long *starving_fl;
1010 unsigned long *txq_maperr;
1011 unsigned long *blocked_fl;
1012 struct timer_list rx_timer;
1013 struct timer_list tx_timer;
1014
1015 int fwevtq_msix_idx;
1016 int nd_msix_idx;
1017};
1018
1019#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
1020#define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
1021
1022struct l2t_data;
1023
1024#ifdef CONFIG_PCI_IOV
1025
1026
1027
1028
1029
1030#define NUM_OF_PF_WITH_SRIOV 4
1031
1032#endif
1033
1034struct doorbell_stats {
1035 u32 db_drop;
1036 u32 db_empty;
1037 u32 db_full;
1038};
1039
1040struct hash_mac_addr {
1041 struct list_head list;
1042 u8 addr[ETH_ALEN];
1043 unsigned int iface_mac;
1044};
1045
1046struct msix_bmap {
1047 unsigned long *msix_bmap;
1048 unsigned int mapsize;
1049 spinlock_t lock;
1050};
1051
1052struct msix_info {
1053 unsigned short vec;
1054 char desc[IFNAMSIZ + 10];
1055 unsigned int idx;
1056 cpumask_var_t aff_mask;
1057};
1058
1059struct vf_info {
1060 unsigned char vf_mac_addr[ETH_ALEN];
1061 unsigned int tx_rate;
1062 bool pf_set_mac;
1063 u16 vlan;
1064 int link_state;
1065};
1066
1067enum {
1068 HMA_DMA_MAPPED_FLAG = 1
1069};
1070
1071struct hma_data {
1072 unsigned char flags;
1073 struct sg_table *sgt;
1074 dma_addr_t *phy_addr;
1075};
1076
1077struct mbox_list {
1078 struct list_head list;
1079};
1080
1081#if IS_ENABLED(CONFIG_THERMAL)
1082struct ch_thermal {
1083 struct thermal_zone_device *tzdev;
1084 int trip_temp;
1085 int trip_type;
1086};
1087#endif
1088
1089struct mps_entries_ref {
1090 struct list_head list;
1091 u8 addr[ETH_ALEN];
1092 u8 mask[ETH_ALEN];
1093 u16 idx;
1094 refcount_t refcnt;
1095};
1096
1097struct cxgb4_ethtool_filter_info {
1098 u32 *loc_array;
1099 unsigned long *bmap;
1100 u32 in_use;
1101};
1102
1103struct cxgb4_ethtool_filter {
1104 u32 nentries;
1105 struct cxgb4_ethtool_filter_info *port;
1106};
1107
1108struct adapter {
1109 void __iomem *regs;
1110 void __iomem *bar2;
1111 u32 t4_bar0;
1112 struct pci_dev *pdev;
1113 struct device *pdev_dev;
1114 const char *name;
1115 unsigned int mbox;
1116 unsigned int pf;
1117 unsigned int flags;
1118 unsigned int adap_idx;
1119 enum chip_type chip;
1120 u32 eth_flags;
1121
1122 int msg_enable;
1123 __be16 vxlan_port;
1124 __be16 geneve_port;
1125
1126 struct adapter_params params;
1127 struct cxgb4_virt_res vres;
1128 unsigned int swintr;
1129
1130
1131 struct msix_info *msix_info;
1132 struct msix_bmap msix_bmap;
1133
1134 struct doorbell_stats db_stats;
1135 struct sge sge;
1136
1137 struct net_device *port[MAX_NPORTS];
1138 u8 chan_map[NCHAN];
1139
1140 struct vf_info *vfinfo;
1141 u8 num_vfs;
1142
1143 u32 filter_mode;
1144 unsigned int l2t_start;
1145 unsigned int l2t_end;
1146 struct l2t_data *l2t;
1147 unsigned int clipt_start;
1148 unsigned int clipt_end;
1149 struct clip_tbl *clipt;
1150 unsigned int rawf_start;
1151 unsigned int rawf_cnt;
1152 struct smt_data *smt;
1153 struct cxgb4_uld_info *uld;
1154 void *uld_handle[CXGB4_ULD_MAX];
1155 unsigned int num_uld;
1156 unsigned int num_ofld_uld;
1157 struct list_head list_node;
1158 struct list_head rcu_node;
1159 struct list_head mac_hlist;
1160 struct list_head mps_ref;
1161 spinlock_t mps_ref_lock;
1162
1163 void *iscsi_ppm;
1164
1165 struct tid_info tids;
1166 void **tid_release_head;
1167 spinlock_t tid_release_lock;
1168 struct workqueue_struct *workq;
1169 struct work_struct tid_release_task;
1170 struct work_struct db_full_task;
1171 struct work_struct db_drop_task;
1172 struct work_struct fatal_err_notify_task;
1173 bool tid_release_task_busy;
1174
1175
1176 spinlock_t mbox_lock;
1177 struct mbox_list mlist;
1178
1179
1180#define T4_OS_LOG_MBOX_CMDS 256
1181 struct mbox_cmd_log *mbox_log;
1182
1183 struct mutex uld_mutex;
1184
1185 struct dentry *debugfs_root;
1186 bool use_bd;
1187 bool trace_rss;
1188
1189
1190
1191
1192 struct ptp_clock *ptp_clock;
1193 struct ptp_clock_info ptp_clock_info;
1194 struct sk_buff *ptp_tx_skb;
1195
1196 spinlock_t ptp_lock;
1197 spinlock_t stats_lock;
1198 spinlock_t win0_lock ____cacheline_aligned_in_smp;
1199
1200
1201 struct cxgb4_tc_u32_table *tc_u32;
1202 struct chcr_ktls chcr_ktls;
1203 struct chcr_stats_debug chcr_stats;
1204#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
1205 struct ch_ktls_stats_debug ch_ktls_stats;
1206#endif
1207#if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE)
1208 struct ch_ipsec_stats_debug ch_ipsec_stats;
1209#endif
1210
1211
1212 bool tc_flower_initialized;
1213 struct rhashtable flower_tbl;
1214 struct rhashtable_params flower_ht_params;
1215 struct timer_list flower_stats_timer;
1216 struct work_struct flower_stats_work;
1217
1218
1219 struct ethtool_dump eth_dump;
1220
1221
1222 struct hma_data hma;
1223
1224 struct srq_data *srq;
1225
1226
1227 struct vmcoredd_data vmcoredd;
1228#if IS_ENABLED(CONFIG_THERMAL)
1229 struct ch_thermal ch_thermal;
1230#endif
1231
1232
1233 struct cxgb4_tc_mqprio *tc_mqprio;
1234
1235
1236 struct cxgb4_tc_matchall *tc_matchall;
1237
1238
1239 struct cxgb4_ethtool_filter *ethtool_filters;
1240};
1241
1242
1243
1244
1245struct ch_sched_params {
1246 u8 type;
1247 union {
1248 struct {
1249 u8 level;
1250 u8 mode;
1251 u8 rateunit;
1252 u8 ratemode;
1253 u8 channel;
1254 u8 class;
1255 u32 minrate;
1256 u32 maxrate;
1257 u16 weight;
1258 u16 pktsize;
1259 u16 burstsize;
1260 } params;
1261 } u;
1262};
1263
1264enum {
1265 SCHED_CLASS_TYPE_PACKET = 0,
1266};
1267
1268enum {
1269 SCHED_CLASS_LEVEL_CL_RL = 0,
1270 SCHED_CLASS_LEVEL_CH_RL = 2,
1271};
1272
1273enum {
1274 SCHED_CLASS_MODE_CLASS = 0,
1275 SCHED_CLASS_MODE_FLOW,
1276};
1277
1278enum {
1279 SCHED_CLASS_RATEUNIT_BITS = 0,
1280};
1281
1282enum {
1283 SCHED_CLASS_RATEMODE_ABS = 1,
1284};
1285
1286
1287
1288
1289struct ch_sched_queue {
1290 s8 queue;
1291 s8 class;
1292};
1293
1294
1295
1296
1297struct ch_sched_flowc {
1298 s32 tid;
1299 s8 class;
1300};
1301
1302
1303
1304#define ETHTYPE_BITWIDTH 16
1305#define FRAG_BITWIDTH 1
1306#define MACIDX_BITWIDTH 9
1307#define FCOE_BITWIDTH 1
1308#define IPORT_BITWIDTH 3
1309#define MATCHTYPE_BITWIDTH 3
1310#define PROTO_BITWIDTH 8
1311#define TOS_BITWIDTH 8
1312#define PF_BITWIDTH 8
1313#define VF_BITWIDTH 8
1314#define IVLAN_BITWIDTH 16
1315#define OVLAN_BITWIDTH 16
1316#define ENCAP_VNI_BITWIDTH 24
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335struct ch_filter_tuple {
1336
1337
1338
1339
1340
1341
1342 uint32_t ethtype:ETHTYPE_BITWIDTH;
1343 uint32_t frag:FRAG_BITWIDTH;
1344 uint32_t ivlan_vld:1;
1345 uint32_t ovlan_vld:1;
1346 uint32_t pfvf_vld:1;
1347 uint32_t encap_vld:1;
1348 uint32_t macidx:MACIDX_BITWIDTH;
1349 uint32_t fcoe:FCOE_BITWIDTH;
1350 uint32_t iport:IPORT_BITWIDTH;
1351 uint32_t matchtype:MATCHTYPE_BITWIDTH;
1352 uint32_t proto:PROTO_BITWIDTH;
1353 uint32_t tos:TOS_BITWIDTH;
1354 uint32_t pf:PF_BITWIDTH;
1355 uint32_t vf:VF_BITWIDTH;
1356 uint32_t ivlan:IVLAN_BITWIDTH;
1357 uint32_t ovlan:OVLAN_BITWIDTH;
1358 uint32_t vni:ENCAP_VNI_BITWIDTH;
1359
1360
1361
1362
1363 uint8_t lip[16];
1364 uint8_t fip[16];
1365 uint16_t lport;
1366 uint16_t fport;
1367};
1368
1369
1370
1371struct ch_filter_specification {
1372
1373
1374 uint32_t hitcnts:1;
1375 uint32_t prio:1;
1376
1377
1378
1379
1380 uint32_t type:1;
1381 u32 hash:1;
1382
1383
1384
1385
1386
1387 uint32_t action:2;
1388
1389 uint32_t rpttid:1;
1390
1391 uint32_t dirsteer:1;
1392 uint32_t iq:10;
1393
1394 uint32_t maskhash:1;
1395 uint32_t dirsteerhash:1;
1396
1397
1398
1399
1400
1401
1402 uint32_t eport:2;
1403 uint32_t newdmac:1;
1404 uint32_t newsmac:1;
1405 uint32_t newvlan:2;
1406 uint32_t nat_mode:3;
1407 uint8_t dmac[ETH_ALEN];
1408 uint8_t smac[ETH_ALEN];
1409 uint16_t vlan;
1410
1411 u8 nat_lip[16];
1412 u8 nat_fip[16];
1413 u16 nat_lport;
1414 u16 nat_fport;
1415
1416 u32 tc_prio;
1417 u64 tc_cookie;
1418
1419
1420 u8 rsvd[12];
1421
1422
1423
1424 struct ch_filter_tuple val;
1425 struct ch_filter_tuple mask;
1426};
1427
1428enum {
1429 FILTER_PASS = 0,
1430 FILTER_DROP,
1431 FILTER_SWITCH
1432};
1433
1434enum {
1435 VLAN_NOCHANGE = 0,
1436 VLAN_REMOVE,
1437 VLAN_INSERT,
1438 VLAN_REWRITE
1439};
1440
1441enum {
1442 NAT_MODE_NONE = 0,
1443 NAT_MODE_DIP,
1444 NAT_MODE_DIP_DP,
1445 NAT_MODE_DIP_DP_SIP,
1446 NAT_MODE_DIP_DP_SP,
1447 NAT_MODE_SIP_SP,
1448 NAT_MODE_DIP_SIP_SP,
1449 NAT_MODE_ALL
1450};
1451
1452#define CXGB4_FILTER_TYPE_MAX 2
1453
1454
1455
1456
1457
1458
1459
1460struct filter_entry {
1461
1462 u32 valid:1;
1463 u32 locked:1;
1464
1465 u32 pending:1;
1466 struct filter_ctx *ctx;
1467 struct l2t_entry *l2t;
1468 struct smt_entry *smt;
1469 struct net_device *dev;
1470 u32 tid;
1471
1472
1473
1474
1475
1476
1477 struct ch_filter_specification fs;
1478};
1479
1480static inline int is_offload(const struct adapter *adap)
1481{
1482 return adap->params.offload;
1483}
1484
1485static inline int is_hashfilter(const struct adapter *adap)
1486{
1487 return adap->params.hash_filter;
1488}
1489
1490static inline int is_pci_uld(const struct adapter *adap)
1491{
1492 return adap->params.crypto;
1493}
1494
1495static inline int is_uld(const struct adapter *adap)
1496{
1497 return (adap->params.offload || adap->params.crypto);
1498}
1499
1500static inline int is_ethofld(const struct adapter *adap)
1501{
1502 return adap->params.ethofld;
1503}
1504
1505static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1506{
1507 return readl(adap->regs + reg_addr);
1508}
1509
1510static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1511{
1512 writel(val, adap->regs + reg_addr);
1513}
1514
1515#ifndef readq
1516static inline u64 readq(const volatile void __iomem *addr)
1517{
1518 return readl(addr) + ((u64)readl(addr + 4) << 32);
1519}
1520
1521static inline void writeq(u64 val, volatile void __iomem *addr)
1522{
1523 writel(val, addr);
1524 writel(val >> 32, addr + 4);
1525}
1526#endif
1527
1528static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1529{
1530 return readq(adap->regs + reg_addr);
1531}
1532
1533static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1534{
1535 writeq(val, adap->regs + reg_addr);
1536}
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1548 u8 hw_addr[])
1549{
1550 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1551 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1552}
1553
1554
1555
1556
1557
1558
1559
1560static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1561{
1562 return netdev_priv(dev);
1563}
1564
1565
1566
1567
1568
1569
1570
1571
1572static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1573{
1574 return netdev_priv(adap->port[idx]);
1575}
1576
1577
1578
1579
1580
1581
1582
1583static inline struct adapter *netdev2adap(const struct net_device *dev)
1584{
1585 return netdev2pinfo(dev)->adapter;
1586}
1587
1588
1589
1590
1591
1592
1593static inline unsigned int mk_adap_vers(struct adapter *ap)
1594{
1595 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1596 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1597}
1598
1599
1600static inline unsigned int qtimer_val(const struct adapter *adap,
1601 const struct sge_rspq *q)
1602{
1603 unsigned int idx = q->intr_params >> 1;
1604
1605 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1606}
1607
1608
1609extern char cxgb4_driver_name[];
1610
1611void t4_os_portmod_changed(struct adapter *adap, int port_id);
1612void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1613
1614void t4_free_sge_resources(struct adapter *adap);
1615void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1616irq_handler_t t4_intr_handler(struct adapter *adap);
1617netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1618int cxgb4_selftest_lb_pkt(struct net_device *netdev);
1619int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1620 const struct pkt_gl *gl);
1621int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1622int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1623int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1624 struct net_device *dev, int intr_idx,
1625 struct sge_fl *fl, rspq_handler_t hnd,
1626 rspq_flush_handler_t flush_handler, int cong);
1627int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1628 struct net_device *dev, struct netdev_queue *netdevq,
1629 unsigned int iqid, u8 dbqt);
1630int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1631 struct net_device *dev, unsigned int iqid,
1632 unsigned int cmplqid);
1633int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1634 unsigned int cmplqid);
1635int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1636 struct net_device *dev, unsigned int iqid,
1637 unsigned int uld_type);
1638int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq,
1639 struct net_device *dev, u32 iqid);
1640void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq);
1641irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1642int t4_sge_init(struct adapter *adap);
1643void t4_sge_start(struct adapter *adap);
1644void t4_sge_stop(struct adapter *adap);
1645int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q,
1646 int maxreclaim);
1647void cxgb4_set_ethtool_ops(struct net_device *netdev);
1648int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1649enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1650extern int dbfifo_int_thresh;
1651
1652#define for_each_port(adapter, iter) \
1653 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1654
1655static inline int is_bypass(struct adapter *adap)
1656{
1657 return adap->params.bypass;
1658}
1659
1660static inline int is_bypass_device(int device)
1661{
1662
1663 switch (device) {
1664 case 0x440b:
1665 case 0x440c:
1666 return 1;
1667 default:
1668 return 0;
1669 }
1670}
1671
1672static inline int is_10gbt_device(int device)
1673{
1674
1675 switch (device) {
1676 case 0x4409:
1677 case 0x4486:
1678 return 1;
1679
1680 default:
1681 return 0;
1682 }
1683}
1684
1685static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1686{
1687 return adap->params.vpd.cclk / 1000;
1688}
1689
1690static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1691 unsigned int us)
1692{
1693 return (us * adap->params.vpd.cclk) / 1000;
1694}
1695
1696static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1697 unsigned int ticks)
1698{
1699
1700 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1701 adapter->params.vpd.cclk);
1702}
1703
1704static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1705 unsigned int ticks)
1706{
1707 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1708}
1709
1710void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1711 u32 val);
1712
1713int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1714 int size, void *rpl, bool sleep_ok, int timeout);
1715int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1716 void *rpl, bool sleep_ok);
1717
1718static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1719 const void *cmd, int size, void *rpl,
1720 int timeout)
1721{
1722 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1723 timeout);
1724}
1725
1726static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1727 int size, void *rpl)
1728{
1729 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1730}
1731
1732static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1733 int size, void *rpl)
1734{
1735 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1736}
1737
1738
1739
1740
1741
1742
1743
1744
1745static inline int hash_mac_addr(const u8 *addr)
1746{
1747 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1748 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1749
1750 a ^= b;
1751 a ^= (a >> 12);
1752 a ^= (a >> 6);
1753 return a & 0x3f;
1754}
1755
1756int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1757 unsigned int cnt);
1758static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1759 unsigned int us, unsigned int cnt,
1760 unsigned int size, unsigned int iqe_size)
1761{
1762 q->adap = adap;
1763 cxgb4_set_rspq_intr_params(q, us, cnt);
1764 q->iqe_len = iqe_size;
1765 q->size = size;
1766}
1767
1768
1769
1770
1771
1772
1773
1774
1775static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1776{
1777 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1778 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1779 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1780 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1781}
1782
1783void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1784 unsigned int data_reg, const u32 *vals,
1785 unsigned int nregs, unsigned int start_idx);
1786void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1787 unsigned int data_reg, u32 *vals, unsigned int nregs,
1788 unsigned int start_idx);
1789void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1790
1791struct fw_filter_wr;
1792
1793void t4_intr_enable(struct adapter *adapter);
1794void t4_intr_disable(struct adapter *adapter);
1795int t4_slow_intr_handler(struct adapter *adapter);
1796
1797int t4_wait_dev_ready(void __iomem *regs);
1798
1799fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
1800 struct link_config *lc);
1801int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1802 unsigned int port, struct link_config *lc,
1803 u8 sleep_ok, int timeout);
1804
1805static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1806 unsigned int port, struct link_config *lc)
1807{
1808 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1809 true, FW_CMD_MAX_TIMEOUT);
1810}
1811
1812static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1813 unsigned int port, struct link_config *lc)
1814{
1815 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1816 false, FW_CMD_MAX_TIMEOUT);
1817}
1818
1819int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1820
1821u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1822u32 t4_get_util_window(struct adapter *adap);
1823void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1824
1825int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1826 u32 *mem_base, u32 *mem_aperture);
1827void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1828void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1829 int dir);
1830#define T4_MEMORY_WRITE 0
1831#define T4_MEMORY_READ 1
1832int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1833 void *buf, int dir);
1834static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1835 u32 len, __be32 *buf)
1836{
1837 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1838}
1839
1840unsigned int t4_get_regs_len(struct adapter *adapter);
1841void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1842
1843int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1844int t4_seeprom_wp(struct adapter *adapter, bool enable);
1845int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1846int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1847int t4_get_pfres(struct adapter *adapter);
1848int t4_read_flash(struct adapter *adapter, unsigned int addr,
1849 unsigned int nwords, u32 *data, int byte_oriented);
1850int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1851int t4_load_phy_fw(struct adapter *adap, int win,
1852 int (*phy_fw_version)(const u8 *, size_t),
1853 const u8 *phy_fw_data, size_t phy_fw_size);
1854int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1855int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1856int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1857 const u8 *fw_data, unsigned int size, int force);
1858int t4_fl_pkt_align(struct adapter *adap);
1859unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1860int t4_check_fw_version(struct adapter *adap);
1861int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1862int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1863int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1864int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1865int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1866int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1867int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1868int t4_get_version_info(struct adapter *adapter);
1869void t4_dump_version_info(struct adapter *adapter);
1870int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1871 const u8 *fw_data, unsigned int fw_size,
1872 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1873int t4_prep_adapter(struct adapter *adapter);
1874int t4_shutdown_adapter(struct adapter *adapter);
1875
1876enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1877int t4_bar2_sge_qregs(struct adapter *adapter,
1878 unsigned int qid,
1879 enum t4_bar2_qtype qtype,
1880 int user,
1881 u64 *pbar2_qoffset,
1882 unsigned int *pbar2_qid);
1883
1884unsigned int qtimer_val(const struct adapter *adap,
1885 const struct sge_rspq *q);
1886
1887int t4_init_devlog_params(struct adapter *adapter);
1888int t4_init_sge_params(struct adapter *adapter);
1889int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1890int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1891int t4_init_rss_mode(struct adapter *adap, int mbox);
1892int t4_init_portinfo(struct port_info *pi, int mbox,
1893 int port, int pf, int vf, u8 mac[]);
1894int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1895int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
1896 u16 *mirror_viid);
1897void t4_fatal_err(struct adapter *adapter);
1898unsigned int t4_chip_rss_size(struct adapter *adapter);
1899int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1900 int start, int n, const u16 *rspq, unsigned int nrspq);
1901int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1902 unsigned int flags);
1903int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1904 unsigned int flags, unsigned int defq);
1905int t4_read_rss(struct adapter *adapter, u16 *entries);
1906void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1907void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1908 bool sleep_ok);
1909void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1910 u32 *valp, bool sleep_ok);
1911void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1912 u32 *vfl, u32 *vfh, bool sleep_ok);
1913u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1914u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1915
1916unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1917unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1918void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1919void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1920int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1921 size_t n);
1922int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1923 size_t n);
1924int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1925 unsigned int *valp);
1926int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1927 const unsigned int *valp);
1928int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1929void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1930 unsigned int *pif_req_wrptr,
1931 unsigned int *pif_rsp_wrptr);
1932void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1933void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1934const char *t4_get_port_type_description(enum fw_port_type port_type);
1935void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1936void t4_get_port_stats_offset(struct adapter *adap, int idx,
1937 struct port_stats *stats,
1938 struct port_stats *offset);
1939void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1940void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1941void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1942void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1943 unsigned int mask, unsigned int val);
1944void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1945void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1946 bool sleep_ok);
1947void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1948 bool sleep_ok);
1949void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1950 bool sleep_ok);
1951void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1952 bool sleep_ok);
1953void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1954 struct tp_tcp_stats *v6, bool sleep_ok);
1955void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1956 struct tp_fcoe_stats *st, bool sleep_ok);
1957void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1958 const unsigned short *alpha, const unsigned short *beta);
1959
1960void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1961
1962void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1963void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1964
1965void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1966 const u8 *addr);
1967int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1968 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1969
1970int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1971 enum dev_master master, enum dev_state *state);
1972int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1973int t4_early_init(struct adapter *adap, unsigned int mbox);
1974int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1975int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1976 unsigned int cache_line_size);
1977int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1978int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1979 unsigned int vf, unsigned int nparams, const u32 *params,
1980 u32 *val);
1981int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1982 unsigned int vf, unsigned int nparams, const u32 *params,
1983 u32 *val);
1984int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1985 unsigned int vf, unsigned int nparams, const u32 *params,
1986 u32 *val, int rw, bool sleep_ok);
1987int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1988 unsigned int pf, unsigned int vf,
1989 unsigned int nparams, const u32 *params,
1990 const u32 *val, int timeout);
1991int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1992 unsigned int vf, unsigned int nparams, const u32 *params,
1993 const u32 *val);
1994int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1995 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1996 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1997 unsigned int vi, unsigned int cmask, unsigned int pmask,
1998 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1999int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
2000 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
2001 unsigned int *rss_size, u8 *vivld, u8 *vin);
2002int t4_free_vi(struct adapter *adap, unsigned int mbox,
2003 unsigned int pf, unsigned int vf,
2004 unsigned int viid);
2005int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
2006 unsigned int viid_mirror, int mtu, int promisc, int all_multi,
2007 int bcast, int vlanex, bool sleep_ok);
2008int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
2009 const u8 *addr, const u8 *mask, unsigned int idx,
2010 u8 lookup_type, u8 port_id, bool sleep_ok);
2011int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
2012 bool sleep_ok);
2013int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
2014 const u8 *addr, const u8 *mask, unsigned int vni,
2015 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
2016 bool sleep_ok);
2017int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
2018 const u8 *addr, const u8 *mask, unsigned int idx,
2019 u8 lookup_type, u8 port_id, bool sleep_ok);
2020int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
2021 unsigned int viid, bool free, unsigned int naddr,
2022 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
2023int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
2024 unsigned int viid, unsigned int naddr,
2025 const u8 **addr, bool sleep_ok);
2026int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
2027 int idx, const u8 *addr, bool persist, u8 *smt_idx);
2028int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
2029 bool ucast, u64 vec, bool sleep_ok);
2030int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
2031 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
2032int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
2033 struct port_info *pi,
2034 bool rx_en, bool tx_en, bool dcb_en);
2035int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
2036 bool rx_en, bool tx_en);
2037int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
2038 unsigned int nblinks);
2039int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2040 unsigned int mmd, unsigned int reg, u16 *valp);
2041int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2042 unsigned int mmd, unsigned int reg, u16 val);
2043int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
2044 unsigned int vf, unsigned int iqtype, unsigned int iqid,
2045 unsigned int fl0id, unsigned int fl1id);
2046int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2047 unsigned int vf, unsigned int iqtype, unsigned int iqid,
2048 unsigned int fl0id, unsigned int fl1id);
2049int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2050 unsigned int vf, unsigned int eqid);
2051int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2052 unsigned int vf, unsigned int eqid);
2053int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2054 unsigned int vf, unsigned int eqid);
2055int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
2056int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
2057 u16 *dbqtimers);
2058void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
2059int t4_update_port_info(struct port_info *pi);
2060int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
2061 unsigned int *speedp, unsigned int *mtup);
2062int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
2063void t4_db_full(struct adapter *adapter);
2064void t4_db_dropped(struct adapter *adapter);
2065int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
2066 int filter_index, int enable);
2067void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
2068 int filter_index, int *enabled);
2069int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
2070 u32 addr, u32 val);
2071void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
2072void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
2073 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
2074int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
2075 enum ctxt_type ctype, u32 *data);
2076int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
2077 enum ctxt_type ctype, u32 *data);
2078int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
2079 u8 rateunit, u8 ratemode, u8 channel, u8 class,
2080 u32 minrate, u32 maxrate, u16 weight, u16 pktsize,
2081 u16 burstsize);
2082void t4_sge_decode_idma_state(struct adapter *adapter, int state);
2083void t4_idma_monitor_init(struct adapter *adapter,
2084 struct sge_idma_monitor_state *idma);
2085void t4_idma_monitor(struct adapter *adapter,
2086 struct sge_idma_monitor_state *idma,
2087 int hz, int ticks);
2088int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
2089 unsigned int naddr, u8 *addr);
2090void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
2091 u32 start_index, bool sleep_ok);
2092void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
2093 u32 start_index, bool sleep_ok);
2094void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
2095 u32 start_index, bool sleep_ok);
2096
2097void t4_uld_mem_free(struct adapter *adap);
2098int t4_uld_mem_alloc(struct adapter *adap);
2099void t4_uld_clean_up(struct adapter *adap);
2100void t4_register_netevent_notifier(void);
2101int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
2102 unsigned int devid, unsigned int offset,
2103 unsigned int len, u8 *buf);
2104int t4_load_boot(struct adapter *adap, u8 *boot_data,
2105 unsigned int boot_addr, unsigned int size);
2106int t4_load_bootcfg(struct adapter *adap,
2107 const u8 *cfg_data, unsigned int size);
2108void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
2109void free_tx_desc(struct adapter *adap, struct sge_txq *q,
2110 unsigned int n, bool unmap);
2111void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq,
2112 u32 ndesc);
2113int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc);
2114void cxgb4_ethofld_restart(struct tasklet_struct *t);
2115int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp,
2116 const struct pkt_gl *si);
2117void free_txq(struct adapter *adap, struct sge_txq *q);
2118void cxgb4_reclaim_completed_tx(struct adapter *adap,
2119 struct sge_txq *q, bool unmap);
2120int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
2121 dma_addr_t *addr);
2122void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
2123 void *pos);
2124void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
2125 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
2126 const dma_addr_t *addr);
2127void cxgb4_write_partial_sgl(const struct sk_buff *skb, struct sge_txq *q,
2128 struct ulptx_sgl *sgl, u64 *end,
2129 const dma_addr_t *addr, u32 start, u32 send_len);
2130void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
2131int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
2132 u16 vlan);
2133int cxgb4_dcb_enabled(const struct net_device *dev);
2134
2135int cxgb4_thermal_init(struct adapter *adap);
2136int cxgb4_thermal_remove(struct adapter *adap);
2137int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
2138 cpumask_var_t *aff_mask, int idx);
2139void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask);
2140
2141int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
2142 int *tcam_idx, const u8 *addr,
2143 bool persistent, u8 *smt_idx);
2144
2145int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid,
2146 bool free, unsigned int naddr,
2147 const u8 **addr, u16 *idx,
2148 u64 *hash, bool sleep_ok);
2149int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
2150 unsigned int naddr, const u8 **addr, bool sleep_ok);
2151int cxgb4_init_mps_ref_entries(struct adapter *adap);
2152void cxgb4_free_mps_ref_entries(struct adapter *adap);
2153int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
2154 const u8 *addr, const u8 *mask,
2155 unsigned int vni, unsigned int vni_mask,
2156 u8 dip_hit, u8 lookup_type, bool sleep_ok);
2157int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
2158 int idx, bool sleep_ok);
2159int cxgb4_free_raw_mac_filt(struct adapter *adap,
2160 unsigned int viid,
2161 const u8 *addr,
2162 const u8 *mask,
2163 unsigned int idx,
2164 u8 lookup_type,
2165 u8 port_id,
2166 bool sleep_ok);
2167int cxgb4_alloc_raw_mac_filt(struct adapter *adap,
2168 unsigned int viid,
2169 const u8 *addr,
2170 const u8 *mask,
2171 unsigned int idx,
2172 u8 lookup_type,
2173 u8 port_id,
2174 bool sleep_ok);
2175int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
2176 int *tcam_idx, const u8 *addr,
2177 bool persistent, u8 *smt_idx);
2178int cxgb4_get_msix_idx_from_bmap(struct adapter *adap);
2179void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx);
2180void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q);
2181void cxgb4_quiesce_rx(struct sge_rspq *q);
2182int cxgb4_port_mirror_alloc(struct net_device *dev);
2183void cxgb4_port_mirror_free(struct net_device *dev);
2184#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
2185int cxgb4_set_ktls_feature(struct adapter *adap, bool enable);
2186#endif
2187#endif
2188