1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7#ifndef REG_ADDR_H 8#define REG_ADDR_H 9 10#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ 11 0 12 13#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ 14 0xfff << 0) 15 16#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 17 12 18 19#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ 20 0xfff << 12) 21 22#define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 23 24 24 25#define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ 26 0xff << 24) 27 28#define CDU_REG_SEGMENT0_PARAMS \ 29 0x580904UL 30#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \ 31 (0xfff << 0) 32#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \ 33 0 34#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \ 35 (0xff << 16) 36#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \ 37 16 38#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \ 39 (0xff << 24) 40#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \ 41 24 42#define CDU_REG_SEGMENT1_PARAMS \ 43 0x580908UL 44#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \ 45 (0xfff << 0) 46#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \ 47 0 48#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \ 49 (0xff << 16) 50#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \ 51 16 52#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \ 53 (0xff << 24) 54#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \ 55 24 56 57#define XSDM_REG_OPERATION_GEN \ 58 0xf80408UL 59#define NIG_REG_RX_BRB_OUT_EN \ 60 0x500e18UL 61#define NIG_REG_STORM_OUT_EN \ 62 0x500e08UL 63#define PSWRQ2_REG_L2P_VALIDATE_VFID \ 64 0x240c50UL 65#define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ 66 0x2aae04UL 67#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 68 0x2aa16cUL 69#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \ 70 0x2aa118UL 71#define PSWHST_REG_ZONE_PERMISSION_TABLE \ 72 0x2a0800UL 73#define BAR0_MAP_REG_MSDM_RAM \ 74 0x1d00000UL 75#define BAR0_MAP_REG_USDM_RAM \ 76 0x1d80000UL 77#define BAR0_MAP_REG_PSDM_RAM \ 78 0x1f00000UL 79#define BAR0_MAP_REG_TSDM_RAM \ 80 0x1c80000UL 81#define BAR0_MAP_REG_XSDM_RAM \ 82 0x1e00000UL 83#define BAR0_MAP_REG_YSDM_RAM \ 84 0x1e80000UL 85#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ 86 0x5011f4UL 87#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \ 88 0x1f0164UL 89#define PRS_REG_SEARCH_TCP \ 90 0x1f0400UL 91#define PRS_REG_SEARCH_UDP \ 92 0x1f0404UL 93#define PRS_REG_SEARCH_FCOE \ 94 0x1f0408UL 95#define PRS_REG_SEARCH_ROCE \ 96 0x1f040cUL 97#define PRS_REG_SEARCH_OPENFLOW \ 98 0x1f0434UL 99#define PRS_REG_SEARCH_TAG1 \ 100 0x1f0444UL 101#define PRS_REG_SEARCH_TENANT_ID \ 102 0x1f044cUL 103#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \ 104 0x1f0a0cUL 105#define PRS_REG_SEARCH_TCP_FIRST_FRAG \ 106 0x1f0410UL 107#define TM_REG_PF_ENABLE_CONN \ 108 0x2c043cUL 109#define TM_REG_PF_ENABLE_TASK \ 110 0x2c0444UL 111#define TM_REG_PF_SCAN_ACTIVE_CONN \ 112 0x2c04fcUL 113#define TM_REG_PF_SCAN_ACTIVE_TASK \ 114 0x2c0500UL 115#define IGU_REG_LEADING_EDGE_LATCH \ 116 0x18082cUL 117#define IGU_REG_TRAILING_EDGE_LATCH \ 118 0x180830UL 119#define QM_REG_USG_CNT_PF_TX \ 120 0x2f2eacUL 121#define QM_REG_USG_CNT_PF_OTHER \ 122 0x2f2eb0UL 123#define DORQ_REG_PF_DB_ENABLE \ 124 0x100508UL 125#define DORQ_REG_VF_USAGE_CNT \ 126 0x1009c4UL 127#define QM_REG_PF_EN \ 128 0x2f2ea4UL 129#define TCFC_REG_WEAK_ENABLE_VF \ 130 0x2d0704UL 131#define TCFC_REG_STRONG_ENABLE_PF \ 132 0x2d0708UL 133#define TCFC_REG_STRONG_ENABLE_VF \ 134 0x2d070cUL 135#define CCFC_REG_WEAK_ENABLE_VF \ 136 0x2e0704UL 137#define CCFC_REG_STRONG_ENABLE_PF \ 138 0x2e0708UL 139#define PGLUE_B_REG_PGL_ADDR_88_F0_BB \ 140 0x2aa404UL 141#define PGLUE_B_REG_PGL_ADDR_8C_F0_BB \ 142 0x2aa408UL 143#define PGLUE_B_REG_PGL_ADDR_90_F0_BB \ 144 0x2aa40cUL 145#define PGLUE_B_REG_PGL_ADDR_94_F0_BB \ 146 0x2aa410UL 147#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ 148 0x2aa138UL 149#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 150 0x2aa174UL 151#define MISC_REG_GEN_PURP_CR0 \ 152 0x008c80UL 153#define MCP_REG_SCRATCH \ 154 0xe20000UL 155#define MCP_REG_SCRATCH_SIZE \ 156 57344 157#define CNIG_REG_NW_PORT_MODE_BB \ 158 0x218200UL 159#define MISCS_REG_CHIP_NUM \ 160 0x00976cUL 161#define MISCS_REG_CHIP_REV \ 162 0x009770UL 163#define MISCS_REG_CMT_ENABLED_FOR_PAIR \ 164 0x00971cUL 165#define MISCS_REG_CHIP_TEST_REG \ 166 0x009778UL 167#define MISCS_REG_CHIP_METAL \ 168 0x009774UL 169#define MISCS_REG_FUNCTION_HIDE \ 170 0x0096f0UL 171#define BRB_REG_HEADER_SIZE \ 172 0x340804UL 173#define BTB_REG_HEADER_SIZE \ 174 0xdb0804UL 175#define CAU_REG_LONG_TIMEOUT_THRESHOLD \ 176 0x1c0708UL 177#define CCFC_REG_ACTIVITY_COUNTER \ 178 0x2e8800UL 179#define CCFC_REG_STRONG_ENABLE_VF \ 180 0x2e070cUL 181#define CDU_REG_CCFC_CTX_VALID0 \ 182 0x580400UL 183#define CDU_REG_CCFC_CTX_VALID1 \ 184 0x580404UL 185#define CDU_REG_TCFC_CTX_VALID0 \ 186 0x580408UL 187#define CDU_REG_CID_ADDR_PARAMS \ 188 0x580900UL 189#define DBG_REG_CLIENT_ENABLE \ 190 0x010004UL 191#define DBG_REG_TIMESTAMP_VALID_EN \ 192 0x010b58UL 193#define DMAE_REG_INIT \ 194 0x00c000UL 195#define DORQ_REG_IFEN \ 196 0x100040UL 197#define DORQ_REG_TAG1_OVRD_MODE \ 198 0x1008b4UL 199#define DORQ_REG_PF_PCP_BB_K2 \ 200 0x1008c4UL 201#define DORQ_REG_PF_EXT_VID_BB_K2 \ 202 0x1008c8UL 203#define DORQ_REG_DB_DROP_REASON \ 204 0x100a2cUL 205#define DORQ_REG_DB_DROP_DETAILS \ 206 0x100a24UL 207#define DORQ_REG_DB_DROP_DETAILS_ADDRESS \ 208 0x100a1cUL 209#define GRC_REG_TIMEOUT_EN \ 210 0x050404UL 211#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \ 212 0x050054UL 213#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \ 214 0x05004cUL 215#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \ 216 0x050050UL 217#define IGU_REG_BLOCK_CONFIGURATION \ 218 0x180040UL 219#define MCM_REG_INIT \ 220 0x1200000UL 221#define MCP2_REG_DBG_DWORD_ENABLE \ 222 0x052404UL 223#define MISC_REG_PORT_MODE \ 224 0x008c00UL 225#define MISCS_REG_CLK_100G_MODE \ 226 0x009070UL 227#define MSDM_REG_ENABLE_IN1 \ 228 0xfc0004UL 229#define MSEM_REG_ENABLE_IN \ 230 0x1800004UL 231#define NIG_REG_CM_HDR \ 232 0x500840UL 233#define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \ 234 0x50196cUL 235#define NIG_REG_LLH_PPFID2PFID_TBL_0 \ 236 0x501970UL 237#define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL \ 238 0x50 239#define NIG_REG_LLH_CLS_TYPE_DUALMODE \ 240 0x501964UL 241#define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL 242#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL 243#define NIG_REG_LLH_FUNC_FILTER_VALUE \ 244 0x501a00UL 245#define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \ 246 32 247#define NIG_REG_LLH_FUNC_FILTER_EN \ 248 0x501a80UL 249#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \ 250 16 251#define NIG_REG_LLH_FUNC_FILTER_MODE \ 252 0x501ac0UL 253#define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \ 254 16 255#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \ 256 0x501b00UL 257#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \ 258 16 259#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \ 260 0x501b40UL 261#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \ 262 16 263#define NCSI_REG_CONFIG \ 264 0x040200UL 265#define PBF_REG_INIT \ 266 0xd80000UL 267#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \ 268 0xd806c8UL 269#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \ 270 0xd806ccUL 271#define PTU_REG_ATC_INIT_ARRAY \ 272 0x560000UL 273#define PCM_REG_INIT \ 274 0x1100000UL 275#define PGLUE_B_REG_ADMIN_PER_PF_REGION \ 276 0x2a9000UL 277#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \ 278 0x2aa150UL 279#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \ 280 0x2aa144UL 281#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \ 282 0x2aa148UL 283#define PGLUE_B_REG_TX_ERR_WR_DETAILS \ 284 0x2aa14cUL 285#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \ 286 0x2aa154UL 287#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \ 288 0x2aa158UL 289#define PGLUE_B_REG_TX_ERR_RD_DETAILS \ 290 0x2aa15cUL 291#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \ 292 0x2aa160UL 293#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \ 294 0x2aa164UL 295#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \ 296 0x2aa54cUL 297#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \ 298 0x2aa544UL 299#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \ 300 0x2aa548UL 301#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \ 302 0x2aae74UL 303#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \ 304 0x2aae78UL 305#define PGLUE_B_REG_VF_ILT_ERR_DETAILS \ 306 0x2aae7cUL 307#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \ 308 0x2aae80UL 309#define PGLUE_B_REG_LATCHED_ERRORS_CLR \ 310 0x2aa3bcUL 311#define PRM_REG_DISABLE_PRM \ 312 0x230000UL 313#define PRS_REG_SOFT_RST \ 314 0x1f0000UL 315#define PRS_REG_MSG_INFO \ 316 0x1f0a1cUL 317#define PRS_REG_ROCE_DEST_QP_MAX_PF \ 318 0x1f0430UL 319#define PRS_REG_USE_LIGHT_L2 \ 320 0x1f096cUL 321#define PSDM_REG_ENABLE_IN1 \ 322 0xfa0004UL 323#define PSEM_REG_ENABLE_IN \ 324 0x1600004UL 325#define PSWRQ_REG_DBG_SELECT \ 326 0x280020UL 327#define PSWRQ2_REG_CDUT_P_SIZE \ 328 0x24000cUL 329#define PSWRQ2_REG_ILT_MEMORY \ 330 0x260000UL 331#define PSWRQ2_REG_ILT_MEMORY_SIZE_BB \ 332 15200 333#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 \ 334 22000 335#define PSWHST_REG_DISCARD_INTERNAL_WRITES \ 336 0x2a0040UL 337#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ 338 0x29e050UL 339#define PSWHST_REG_INCORRECT_ACCESS_VALID \ 340 0x2a0070UL 341#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \ 342 0x2a0074UL 343#define PSWHST_REG_INCORRECT_ACCESS_DATA \ 344 0x2a0068UL 345#define PSWHST_REG_INCORRECT_ACCESS_LENGTH \ 346 0x2a006cUL 347#define PSWRD_REG_DBG_SELECT \ 348 0x29c040UL 349#define PSWRD2_REG_CONF11 \ 350 0x29d064UL 351#define PSWWR_REG_USDM_FULL_TH \ 352 0x29a040UL 353#define PSWWR2_REG_CDU_FULL_TH2 \ 354 0x29b040UL 355#define QM_REG_MAXPQSIZE_0 \ 356 0x2f0434UL 357#define RSS_REG_RSS_INIT_EN \ 358 0x238804UL 359#define RDIF_REG_STOP_ON_ERROR \ 360 0x300040UL 361#define RDIF_REG_DEBUG_ERROR_INFO \ 362 0x300400UL 363#define RDIF_REG_DEBUG_ERROR_INFO_SIZE \ 364 64 365#define SRC_REG_SOFT_RST \ 366 0x23874cUL 367#define TCFC_REG_ACTIVITY_COUNTER \ 368 0x2d8800UL 369#define TCM_REG_INIT \ 370 0x1180000UL 371#define TM_REG_PXP_READ_DATA_FIFO_INIT \ 372 0x2c0014UL 373#define TSDM_REG_ENABLE_IN1 \ 374 0xfb0004UL 375#define TSEM_REG_ENABLE_IN \ 376 0x1700004UL 377#define TDIF_REG_STOP_ON_ERROR \ 378 0x310040UL 379#define TDIF_REG_DEBUG_ERROR_INFO \ 380 0x310400UL 381#define TDIF_REG_DEBUG_ERROR_INFO_SIZE \ 382 64 383#define UCM_REG_INIT \ 384 0x1280000UL 385#define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ 386 0x051004UL 387#define USDM_REG_ENABLE_IN1 \ 388 0xfd0004UL 389#define USEM_REG_ENABLE_IN \ 390 0x1900004UL 391#define XCM_REG_INIT \ 392 0x1000000UL 393#define XSDM_REG_ENABLE_IN1 \ 394 0xf80004UL 395#define XSEM_REG_ENABLE_IN \ 396 0x1400004UL 397#define YCM_REG_INIT \ 398 0x1080000UL 399#define YSDM_REG_ENABLE_IN1 \ 400 0xf90004UL 401#define YSEM_REG_ENABLE_IN \ 402 0x1500004UL 403#define XYLD_REG_SCBD_STRICT_PRIO \ 404 0x4c0000UL 405#define TMLD_REG_SCBD_STRICT_PRIO \ 406 0x4d0000UL 407#define MULD_REG_SCBD_STRICT_PRIO \ 408 0x4e0000UL 409#define YULD_REG_SCBD_STRICT_PRIO \ 410 0x4c8000UL 411#define MISC_REG_SHARED_MEM_ADDR \ 412 0x008c20UL 413#define DMAE_REG_GO_C0 \ 414 0x00c048UL 415#define DMAE_REG_GO_C1 \ 416 0x00c04cUL 417#define DMAE_REG_GO_C2 \ 418 0x00c050UL 419#define DMAE_REG_GO_C3 \ 420 0x00c054UL 421#define DMAE_REG_GO_C4 \ 422 0x00c058UL 423#define DMAE_REG_GO_C5 \ 424 0x00c05cUL 425#define DMAE_REG_GO_C6 \ 426 0x00c060UL 427#define DMAE_REG_GO_C7 \ 428 0x00c064UL 429#define DMAE_REG_GO_C8 \ 430 0x00c068UL 431#define DMAE_REG_GO_C9 \ 432 0x00c06cUL 433#define DMAE_REG_GO_C10 \ 434 0x00c070UL 435#define DMAE_REG_GO_C11 \ 436 0x00c074UL 437#define DMAE_REG_GO_C12 \ 438 0x00c078UL 439#define DMAE_REG_GO_C13 \ 440 0x00c07cUL 441#define DMAE_REG_GO_C14 \ 442 0x00c080UL 443#define DMAE_REG_GO_C15 \ 444 0x00c084UL 445#define DMAE_REG_GO_C16 \ 446 0x00c088UL 447#define DMAE_REG_GO_C17 \ 448 0x00c08cUL 449#define DMAE_REG_GO_C18 \ 450 0x00c090UL 451#define DMAE_REG_GO_C19 \ 452 0x00c094UL 453#define DMAE_REG_GO_C20 \ 454 0x00c098UL 455#define DMAE_REG_GO_C21 \ 456 0x00c09cUL 457#define DMAE_REG_GO_C22 \ 458 0x00c0a0UL 459#define DMAE_REG_GO_C23 \ 460 0x00c0a4UL 461#define DMAE_REG_GO_C24 \ 462 0x00c0a8UL 463#define DMAE_REG_GO_C25 \ 464 0x00c0acUL 465#define DMAE_REG_GO_C26 \ 466 0x00c0b0UL 467#define DMAE_REG_GO_C27 \ 468 0x00c0b4UL 469#define DMAE_REG_GO_C28 \ 470 0x00c0b8UL 471#define DMAE_REG_GO_C29 \ 472 0x00c0bcUL 473#define DMAE_REG_GO_C30 \ 474 0x00c0c0UL 475#define DMAE_REG_GO_C31 \ 476 0x00c0c4UL 477#define DMAE_REG_CMD_MEM \ 478 0x00c800UL 479#define QM_REG_MAXPQSIZETXSEL_0 \ 480 0x2f0440UL 481#define QM_REG_SDMCMDREADY \ 482 0x2f1e10UL 483#define QM_REG_SDMCMDADDR \ 484 0x2f1e04UL 485#define QM_REG_SDMCMDDATALSB \ 486 0x2f1e08UL 487#define QM_REG_SDMCMDDATAMSB \ 488 0x2f1e0cUL 489#define QM_REG_SDMCMDGO \ 490 0x2f1e14UL 491#define QM_REG_RLPFCRD \ 492 0x2f4d80UL 493#define QM_REG_RLPFINCVAL \ 494 0x2f4c80UL 495#define QM_REG_RLGLBLCRD \ 496 0x2f4400UL 497#define QM_REG_RLGLBLINCVAL \ 498 0x2f3400UL 499#define IGU_REG_ATTENTION_ENABLE \ 500 0x18083cUL 501#define IGU_REG_ATTN_MSG_ADDR_L \ 502 0x180820UL 503#define IGU_REG_ATTN_MSG_ADDR_H \ 504 0x180824UL 505#define MISC_REG_AEU_GENERAL_ATTN_0 \ 506 0x008400UL 507#define MISC_REG_AEU_GENERAL_ATTN_35 \ 508 0x00848cUL 509#define CAU_REG_SB_ADDR_MEMORY \ 510 0x1c8000UL 511#define CAU_REG_SB_VAR_MEMORY \ 512 0x1c6000UL 513#define CAU_REG_PI_MEMORY \ 514 0x1d0000UL 515#define IGU_REG_PF_CONFIGURATION \ 516 0x180800UL 517#define IGU_REG_VF_CONFIGURATION \ 518 0x180804UL 519#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ 520 0x00849cUL 521#define MISC_REG_AEU_AFTER_INVERT_1_IGU \ 522 0x0087b4UL 523#define MISC_REG_AEU_MASK_ATTN_IGU \ 524 0x008494UL 525#define IGU_REG_CLEANUP_STATUS_0 \ 526 0x180980UL 527#define IGU_REG_CLEANUP_STATUS_1 \ 528 0x180a00UL 529#define IGU_REG_CLEANUP_STATUS_2 \ 530 0x180a80UL 531#define IGU_REG_CLEANUP_STATUS_3 \ 532 0x180b00UL 533#define IGU_REG_CLEANUP_STATUS_4 \ 534 0x180b80UL 535#define IGU_REG_COMMAND_REG_32LSB_DATA \ 536 0x180840UL 537#define IGU_REG_COMMAND_REG_CTRL \ 538 0x180848UL 539#define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ 540 0x1 << 1) 541#define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ 542 0x1 << 0) 543#define IGU_REG_MAPPING_MEMORY \ 544 0x184000UL 545#define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \ 546 0x180408UL 547#define IGU_REG_WRITE_DONE_PENDING \ 548 0x180900UL 549#define MISCS_REG_GENERIC_POR_0 \ 550 0x0096d4UL 551#define MCP_REG_NVM_CFG4 \ 552 0xe0642cUL 553#define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ 554 0x7 << 0) 555#define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 556 0 557#define MCP_REG_CPU_STATE \ 558 0xe05004UL 559#define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10) 560#define MCP_REG_CPU_EVENT_MASK \ 561 0xe05008UL 562#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL 563#define PGLUE_B_REG_PF_BAR0_SIZE \ 564 0x2aae60UL 565#define PGLUE_B_REG_PF_BAR1_SIZE \ 566 0x2aae64UL 567#define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL 568#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL 569#define PRS_REG_GRE_PROTOCOL 0x1f0734UL 570#define PRS_REG_VXLAN_PORT 0x1f0738UL 571#define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL 572#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL 573 574#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0) 575#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0 576#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1) 577#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1 578#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2) 579#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2 580 581#define NIG_REG_VXLAN_CTRL 0x50105cUL 582#define PBF_REG_VXLAN_PORT 0xd80518UL 583#define PBF_REG_NGE_PORT 0xd8051cUL 584#define PRS_REG_NGE_PORT 0x1f086cUL 585#define NIG_REG_NGE_PORT 0x508b38UL 586 587#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL 588#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL 589#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL 590#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL 591#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL 592 593#define NIG_REG_NGE_IP_ENABLE 0x508b28UL 594#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL 595#define NIG_REG_NGE_COMP_VER 0x508b30UL 596#define PBF_REG_NGE_COMP_VER 0xd80524UL 597#define PRS_REG_NGE_COMP_VER 0x1f0878UL 598 599#define QM_REG_WFQPFWEIGHT 0x2f4e80UL 600#define QM_REG_WFQVPWEIGHT 0x2fa000UL 601 602#define PGLCS_REG_DBG_SELECT_K2_E5 \ 603 0x001d14UL 604#define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \ 605 0x001d18UL 606#define PGLCS_REG_DBG_SHIFT_K2_E5 \ 607 0x001d1cUL 608#define PGLCS_REG_DBG_FORCE_VALID_K2_E5 \ 609 0x001d20UL 610#define PGLCS_REG_DBG_FORCE_FRAME_K2_E5 \ 611 0x001d24UL 612#define MISC_REG_RESET_PL_PDA_VMAIN_1 \ 613 0x008070UL 614#define MISC_REG_RESET_PL_PDA_VMAIN_2 \ 615 0x008080UL 616#define MISC_REG_RESET_PL_PDA_VAUX \ 617 0x008090UL 618#define MISCS_REG_RESET_PL_UA \ 619 0x009050UL 620#define MISCS_REG_RESET_PL_HV \ 621 0x009060UL 622#define MISCS_REG_RESET_PL_HV_2_K2_E5 \ 623 0x009150UL 624#define DMAE_REG_DBG_SELECT \ 625 0x00c510UL 626#define DMAE_REG_DBG_DWORD_ENABLE \ 627 0x00c514UL 628#define DMAE_REG_DBG_SHIFT \ 629 0x00c518UL 630#define DMAE_REG_DBG_FORCE_VALID \ 631 0x00c51cUL 632#define DMAE_REG_DBG_FORCE_FRAME \ 633 0x00c520UL 634#define NCSI_REG_DBG_SELECT \ 635 0x040474UL 636#define NCSI_REG_DBG_DWORD_ENABLE \ 637 0x040478UL 638#define NCSI_REG_DBG_SHIFT \ 639 0x04047cUL 640#define NCSI_REG_DBG_FORCE_VALID \ 641 0x040480UL 642#define NCSI_REG_DBG_FORCE_FRAME \ 643 0x040484UL 644#define GRC_REG_DBG_SELECT \ 645 0x0500a4UL 646#define GRC_REG_DBG_DWORD_ENABLE \ 647 0x0500a8UL 648#define GRC_REG_DBG_SHIFT \ 649 0x0500acUL 650#define GRC_REG_DBG_FORCE_VALID \ 651 0x0500b0UL 652#define GRC_REG_DBG_FORCE_FRAME \ 653 0x0500b4UL 654#define UMAC_REG_DBG_SELECT_K2_E5 \ 655 0x051094UL 656#define UMAC_REG_DBG_DWORD_ENABLE_K2_E5 \ 657 0x051098UL 658#define UMAC_REG_DBG_SHIFT_K2_E5 \ 659 0x05109cUL 660#define UMAC_REG_DBG_FORCE_VALID_K2_E5 \ 661 0x0510a0UL 662#define UMAC_REG_DBG_FORCE_FRAME_K2_E5 \ 663 0x0510a4UL 664#define MCP2_REG_DBG_SELECT \ 665 0x052400UL 666#define MCP2_REG_DBG_DWORD_ENABLE \ 667 0x052404UL 668#define MCP2_REG_DBG_SHIFT \ 669 0x052408UL 670#define MCP2_REG_DBG_FORCE_VALID \ 671 0x052440UL 672#define MCP2_REG_DBG_FORCE_FRAME \ 673 0x052444UL 674#define PCIE_REG_DBG_SELECT \ 675 0x0547e8UL 676#define PCIE_REG_DBG_DWORD_ENABLE \ 677 0x0547ecUL 678#define PCIE_REG_DBG_SHIFT \ 679 0x0547f0UL 680#define PCIE_REG_DBG_FORCE_VALID \ 681 0x0547f4UL 682#define PCIE_REG_DBG_FORCE_FRAME \ 683 0x0547f8UL 684#define DORQ_REG_DBG_SELECT \ 685 0x100ad0UL 686#define DORQ_REG_DBG_DWORD_ENABLE \ 687 0x100ad4UL 688#define DORQ_REG_DBG_SHIFT \ 689 0x100ad8UL 690#define DORQ_REG_DBG_FORCE_VALID \ 691 0x100adcUL 692#define DORQ_REG_DBG_FORCE_FRAME \ 693 0x100ae0UL 694#define IGU_REG_DBG_SELECT \ 695 0x181578UL 696#define IGU_REG_DBG_DWORD_ENABLE \ 697 0x18157cUL 698#define IGU_REG_DBG_SHIFT \ 699 0x181580UL 700#define IGU_REG_DBG_FORCE_VALID \ 701 0x181584UL 702#define IGU_REG_DBG_FORCE_FRAME \ 703 0x181588UL 704#define CAU_REG_DBG_SELECT \ 705 0x1c0ea8UL 706#define CAU_REG_DBG_DWORD_ENABLE \ 707 0x1c0eacUL 708#define CAU_REG_DBG_SHIFT \ 709 0x1c0eb0UL 710#define CAU_REG_DBG_FORCE_VALID \ 711 0x1c0eb4UL 712#define CAU_REG_DBG_FORCE_FRAME \ 713 0x1c0eb8UL 714#define PRS_REG_DBG_SELECT \ 715 0x1f0b6cUL 716#define PRS_REG_DBG_DWORD_ENABLE \ 717 0x1f0b70UL 718#define PRS_REG_DBG_SHIFT \ 719 0x1f0b74UL 720#define PRS_REG_DBG_FORCE_VALID \ 721 0x1f0ba0UL 722#define PRS_REG_DBG_FORCE_FRAME \ 723 0x1f0ba4UL 724#define CNIG_REG_DBG_SELECT_K2_E5 \ 725 0x218254UL 726#define CNIG_REG_DBG_DWORD_ENABLE_K2_E5 \ 727 0x218258UL 728#define CNIG_REG_DBG_SHIFT_K2_E5 \ 729 0x21825cUL 730#define CNIG_REG_DBG_FORCE_VALID_K2_E5 \ 731 0x218260UL 732#define CNIG_REG_DBG_FORCE_FRAME_K2_E5 \ 733 0x218264UL 734#define PRM_REG_DBG_SELECT \ 735 0x2306a8UL 736#define PRM_REG_DBG_DWORD_ENABLE \ 737 0x2306acUL 738#define PRM_REG_DBG_SHIFT \ 739 0x2306b0UL 740#define PRM_REG_DBG_FORCE_VALID \ 741 0x2306b4UL 742#define PRM_REG_DBG_FORCE_FRAME \ 743 0x2306b8UL 744#define SRC_REG_DBG_SELECT \ 745 0x238700UL 746#define SRC_REG_DBG_DWORD_ENABLE \ 747 0x238704UL 748#define SRC_REG_DBG_SHIFT \ 749 0x238708UL 750#define SRC_REG_DBG_FORCE_VALID \ 751 0x23870cUL 752#define SRC_REG_DBG_FORCE_FRAME \ 753 0x238710UL 754#define RSS_REG_DBG_SELECT \ 755 0x238c4cUL 756#define RSS_REG_DBG_DWORD_ENABLE \ 757 0x238c50UL 758#define RSS_REG_DBG_SHIFT \ 759 0x238c54UL 760#define RSS_REG_DBG_FORCE_VALID \ 761 0x238c58UL 762#define RSS_REG_DBG_FORCE_FRAME \ 763 0x238c5cUL 764#define RPB_REG_DBG_SELECT \ 765 0x23c728UL 766#define RPB_REG_DBG_DWORD_ENABLE \ 767 0x23c72cUL 768#define RPB_REG_DBG_SHIFT \ 769 0x23c730UL 770#define RPB_REG_DBG_FORCE_VALID \ 771 0x23c734UL 772#define RPB_REG_DBG_FORCE_FRAME \ 773 0x23c738UL 774#define PSWRQ2_REG_DBG_SELECT \ 775 0x240100UL 776#define PSWRQ2_REG_DBG_DWORD_ENABLE \ 777 0x240104UL 778#define PSWRQ2_REG_DBG_SHIFT \ 779 0x240108UL 780#define PSWRQ2_REG_DBG_FORCE_VALID \ 781 0x24010cUL 782#define PSWRQ2_REG_DBG_FORCE_FRAME \ 783 0x240110UL 784#define PSWRQ_REG_DBG_SELECT \ 785 0x280020UL 786#define PSWRQ_REG_DBG_DWORD_ENABLE \ 787 0x280024UL 788#define PSWRQ_REG_DBG_SHIFT \ 789 0x280028UL 790#define PSWRQ_REG_DBG_FORCE_VALID \ 791 0x28002cUL 792#define PSWRQ_REG_DBG_FORCE_FRAME \ 793 0x280030UL 794#define PSWWR_REG_DBG_SELECT \ 795 0x29a084UL 796#define PSWWR_REG_DBG_DWORD_ENABLE \ 797 0x29a088UL 798#define PSWWR_REG_DBG_SHIFT \ 799 0x29a08cUL 800#define PSWWR_REG_DBG_FORCE_VALID \ 801 0x29a090UL 802#define PSWWR_REG_DBG_FORCE_FRAME \ 803 0x29a094UL 804#define PSWRD_REG_DBG_SELECT \ 805 0x29c040UL 806#define PSWRD_REG_DBG_DWORD_ENABLE \ 807 0x29c044UL 808#define PSWRD_REG_DBG_SHIFT \ 809 0x29c048UL 810#define PSWRD_REG_DBG_FORCE_VALID \ 811 0x29c04cUL 812#define PSWRD_REG_DBG_FORCE_FRAME \ 813 0x29c050UL 814#define PSWRD2_REG_DBG_SELECT \ 815 0x29d400UL 816#define PSWRD2_REG_DBG_DWORD_ENABLE \ 817 0x29d404UL 818#define PSWRD2_REG_DBG_SHIFT \ 819 0x29d408UL 820#define PSWRD2_REG_DBG_FORCE_VALID \ 821 0x29d40cUL 822#define PSWRD2_REG_DBG_FORCE_FRAME \ 823 0x29d410UL 824#define PSWHST2_REG_DBG_SELECT \ 825 0x29e058UL 826#define PSWHST2_REG_DBG_DWORD_ENABLE \ 827 0x29e05cUL 828#define PSWHST2_REG_DBG_SHIFT \ 829 0x29e060UL 830#define PSWHST2_REG_DBG_FORCE_VALID \ 831 0x29e064UL 832#define PSWHST2_REG_DBG_FORCE_FRAME \ 833 0x29e068UL 834#define PSWHST_REG_DBG_SELECT \ 835 0x2a0100UL 836#define PSWHST_REG_DBG_DWORD_ENABLE \ 837 0x2a0104UL 838#define PSWHST_REG_DBG_SHIFT \ 839 0x2a0108UL 840#define PSWHST_REG_DBG_FORCE_VALID \ 841 0x2a010cUL 842#define PSWHST_REG_DBG_FORCE_FRAME \ 843 0x2a0110UL 844#define PGLUE_B_REG_DBG_SELECT \ 845 0x2a8400UL 846#define PGLUE_B_REG_DBG_DWORD_ENABLE \ 847 0x2a8404UL 848#define PGLUE_B_REG_DBG_SHIFT \ 849 0x2a8408UL 850#define PGLUE_B_REG_DBG_FORCE_VALID \ 851 0x2a840cUL 852#define PGLUE_B_REG_DBG_FORCE_FRAME \ 853 0x2a8410UL 854#define TM_REG_DBG_SELECT \ 855 0x2c07a8UL 856#define TM_REG_DBG_DWORD_ENABLE \ 857 0x2c07acUL 858#define TM_REG_DBG_SHIFT \ 859 0x2c07b0UL 860#define TM_REG_DBG_FORCE_VALID \ 861 0x2c07b4UL 862#define TM_REG_DBG_FORCE_FRAME \ 863 0x2c07b8UL 864#define TCFC_REG_DBG_SELECT \ 865 0x2d0500UL 866#define TCFC_REG_DBG_DWORD_ENABLE \ 867 0x2d0504UL 868#define TCFC_REG_DBG_SHIFT \ 869 0x2d0508UL 870#define TCFC_REG_DBG_FORCE_VALID \ 871 0x2d050cUL 872#define TCFC_REG_DBG_FORCE_FRAME \ 873 0x2d0510UL 874#define CCFC_REG_DBG_SELECT \ 875 0x2e0500UL 876#define CCFC_REG_DBG_DWORD_ENABLE \ 877 0x2e0504UL 878#define CCFC_REG_DBG_SHIFT \ 879 0x2e0508UL 880#define CCFC_REG_DBG_FORCE_VALID \ 881 0x2e050cUL 882#define CCFC_REG_DBG_FORCE_FRAME \ 883 0x2e0510UL 884#define QM_REG_DBG_SELECT \ 885 0x2f2e74UL 886#define QM_REG_DBG_DWORD_ENABLE \ 887 0x2f2e78UL 888#define QM_REG_DBG_SHIFT \ 889 0x2f2e7cUL 890#define QM_REG_DBG_FORCE_VALID \ 891 0x2f2e80UL 892#define QM_REG_DBG_FORCE_FRAME \ 893 0x2f2e84UL 894#define RDIF_REG_DBG_SELECT \ 895 0x300500UL 896#define RDIF_REG_DBG_DWORD_ENABLE \ 897 0x300504UL 898#define RDIF_REG_DBG_SHIFT \ 899 0x300508UL 900#define RDIF_REG_DBG_FORCE_VALID \ 901 0x30050cUL 902#define RDIF_REG_DBG_FORCE_FRAME \ 903 0x300510UL 904#define TDIF_REG_DBG_SELECT \ 905 0x310500UL 906#define TDIF_REG_DBG_DWORD_ENABLE \ 907 0x310504UL 908#define TDIF_REG_DBG_SHIFT \ 909 0x310508UL 910#define TDIF_REG_DBG_FORCE_VALID \ 911 0x31050cUL 912#define TDIF_REG_DBG_FORCE_FRAME \ 913 0x310510UL 914#define BRB_REG_DBG_SELECT \ 915 0x340ed0UL 916#define BRB_REG_DBG_DWORD_ENABLE \ 917 0x340ed4UL 918#define BRB_REG_DBG_SHIFT \ 919 0x340ed8UL 920#define BRB_REG_DBG_FORCE_VALID \ 921 0x340edcUL 922#define BRB_REG_DBG_FORCE_FRAME \ 923 0x340ee0UL 924#define XYLD_REG_DBG_SELECT \ 925 0x4c1600UL 926#define XYLD_REG_DBG_DWORD_ENABLE \ 927 0x4c1604UL 928#define XYLD_REG_DBG_SHIFT \ 929 0x4c1608UL 930#define XYLD_REG_DBG_FORCE_VALID \ 931 0x4c160cUL 932#define XYLD_REG_DBG_FORCE_FRAME \ 933 0x4c1610UL 934#define YULD_REG_DBG_SELECT_BB_K2 \ 935 0x4c9600UL 936#define YULD_REG_DBG_DWORD_ENABLE_BB_K2 \ 937 0x4c9604UL 938#define YULD_REG_DBG_SHIFT_BB_K2 \ 939 0x4c9608UL 940#define YULD_REG_DBG_FORCE_VALID_BB_K2 \ 941 0x4c960cUL 942#define YULD_REG_DBG_FORCE_FRAME_BB_K2 \ 943 0x4c9610UL 944#define TMLD_REG_DBG_SELECT \ 945 0x4d1600UL 946#define TMLD_REG_DBG_DWORD_ENABLE \ 947 0x4d1604UL 948#define TMLD_REG_DBG_SHIFT \ 949 0x4d1608UL 950#define TMLD_REG_DBG_FORCE_VALID \ 951 0x4d160cUL 952#define TMLD_REG_DBG_FORCE_FRAME \ 953 0x4d1610UL 954#define MULD_REG_DBG_SELECT \ 955 0x4e1600UL 956#define MULD_REG_DBG_DWORD_ENABLE \ 957 0x4e1604UL 958#define MULD_REG_DBG_SHIFT \ 959 0x4e1608UL 960#define MULD_REG_DBG_FORCE_VALID \ 961 0x4e160cUL 962#define MULD_REG_DBG_FORCE_FRAME \ 963 0x4e1610UL 964#define NIG_REG_DBG_SELECT \ 965 0x502140UL 966#define NIG_REG_DBG_DWORD_ENABLE \ 967 0x502144UL 968#define NIG_REG_DBG_SHIFT \ 969 0x502148UL 970#define NIG_REG_DBG_FORCE_VALID \ 971 0x50214cUL 972#define NIG_REG_DBG_FORCE_FRAME \ 973 0x502150UL 974#define BMB_REG_DBG_SELECT \ 975 0x540a7cUL 976#define BMB_REG_DBG_DWORD_ENABLE \ 977 0x540a80UL 978#define BMB_REG_DBG_SHIFT \ 979 0x540a84UL 980#define BMB_REG_DBG_FORCE_VALID \ 981 0x540a88UL 982#define BMB_REG_DBG_FORCE_FRAME \ 983 0x540a8cUL 984#define PTU_REG_DBG_SELECT \ 985 0x560100UL 986#define PTU_REG_DBG_DWORD_ENABLE \ 987 0x560104UL 988#define PTU_REG_DBG_SHIFT \ 989 0x560108UL 990#define PTU_REG_DBG_FORCE_VALID \ 991 0x56010cUL 992#define PTU_REG_DBG_FORCE_FRAME \ 993 0x560110UL 994#define CDU_REG_DBG_SELECT \ 995 0x580704UL 996#define CDU_REG_DBG_DWORD_ENABLE \ 997 0x580708UL 998#define CDU_REG_DBG_SHIFT \ 999 0x58070cUL 1000#define CDU_REG_DBG_FORCE_VALID \
1001 0x580710UL 1002#define CDU_REG_DBG_FORCE_FRAME \ 1003 0x580714UL 1004#define WOL_REG_DBG_SELECT_K2_E5 \ 1005 0x600140UL 1006#define WOL_REG_DBG_DWORD_ENABLE_K2_E5 \ 1007 0x600144UL 1008#define WOL_REG_DBG_SHIFT_K2_E5 \ 1009 0x600148UL 1010#define WOL_REG_DBG_FORCE_VALID_K2_E5 \ 1011 0x60014cUL 1012#define WOL_REG_DBG_FORCE_FRAME_K2_E5 \ 1013 0x600150UL 1014#define BMBN_REG_DBG_SELECT_K2_E5 \ 1015 0x610140UL 1016#define BMBN_REG_DBG_DWORD_ENABLE_K2_E5 \ 1017 0x610144UL 1018#define BMBN_REG_DBG_SHIFT_K2_E5 \ 1019 0x610148UL 1020#define BMBN_REG_DBG_FORCE_VALID_K2_E5 \ 1021 0x61014cUL 1022#define BMBN_REG_DBG_FORCE_FRAME_K2_E5 \ 1023 0x610150UL 1024#define NWM_REG_DBG_SELECT_K2_E5 \ 1025 0x8000ecUL 1026#define NWM_REG_DBG_DWORD_ENABLE_K2_E5 \ 1027 0x8000f0UL 1028#define NWM_REG_DBG_SHIFT_K2_E5 \ 1029 0x8000f4UL 1030#define NWM_REG_DBG_FORCE_VALID_K2_E5 \ 1031 0x8000f8UL 1032#define NWM_REG_DBG_FORCE_FRAME_K2_E5 \ 1033 0x8000fcUL 1034#define PBF_REG_DBG_SELECT \ 1035 0xd80060UL 1036#define PBF_REG_DBG_DWORD_ENABLE \ 1037 0xd80064UL 1038#define PBF_REG_DBG_SHIFT \ 1039 0xd80068UL 1040#define PBF_REG_DBG_FORCE_VALID \ 1041 0xd8006cUL 1042#define PBF_REG_DBG_FORCE_FRAME \ 1043 0xd80070UL 1044#define PBF_PB1_REG_DBG_SELECT \ 1045 0xda0728UL 1046#define PBF_PB1_REG_DBG_DWORD_ENABLE \ 1047 0xda072cUL 1048#define PBF_PB1_REG_DBG_SHIFT \ 1049 0xda0730UL 1050#define PBF_PB1_REG_DBG_FORCE_VALID \ 1051 0xda0734UL 1052#define PBF_PB1_REG_DBG_FORCE_FRAME \ 1053 0xda0738UL 1054#define PBF_PB2_REG_DBG_SELECT \ 1055 0xda4728UL 1056#define PBF_PB2_REG_DBG_DWORD_ENABLE \ 1057 0xda472cUL 1058#define PBF_PB2_REG_DBG_SHIFT \ 1059 0xda4730UL 1060#define PBF_PB2_REG_DBG_FORCE_VALID \ 1061 0xda4734UL 1062#define PBF_PB2_REG_DBG_FORCE_FRAME \ 1063 0xda4738UL 1064#define BTB_REG_DBG_SELECT \ 1065 0xdb08c8UL 1066#define BTB_REG_DBG_DWORD_ENABLE \ 1067 0xdb08ccUL 1068#define BTB_REG_DBG_SHIFT \ 1069 0xdb08d0UL 1070#define BTB_REG_DBG_FORCE_VALID \ 1071 0xdb08d4UL 1072#define BTB_REG_DBG_FORCE_FRAME \ 1073 0xdb08d8UL 1074#define XSDM_REG_DBG_SELECT \ 1075 0xf80e28UL 1076#define XSDM_REG_DBG_DWORD_ENABLE \ 1077 0xf80e2cUL 1078#define XSDM_REG_DBG_SHIFT \ 1079 0xf80e30UL 1080#define XSDM_REG_DBG_FORCE_VALID \ 1081 0xf80e34UL 1082#define XSDM_REG_DBG_FORCE_FRAME \ 1083 0xf80e38UL 1084#define YSDM_REG_DBG_SELECT \ 1085 0xf90e28UL 1086#define YSDM_REG_DBG_DWORD_ENABLE \ 1087 0xf90e2cUL 1088#define YSDM_REG_DBG_SHIFT \ 1089 0xf90e30UL 1090#define YSDM_REG_DBG_FORCE_VALID \ 1091 0xf90e34UL 1092#define YSDM_REG_DBG_FORCE_FRAME \ 1093 0xf90e38UL 1094#define PSDM_REG_DBG_SELECT \ 1095 0xfa0e28UL 1096#define PSDM_REG_DBG_DWORD_ENABLE \ 1097 0xfa0e2cUL 1098#define PSDM_REG_DBG_SHIFT \ 1099 0xfa0e30UL 1100#define PSDM_REG_DBG_FORCE_VALID \ 1101 0xfa0e34UL 1102#define PSDM_REG_DBG_FORCE_FRAME \ 1103 0xfa0e38UL 1104#define TSDM_REG_DBG_SELECT \ 1105 0xfb0e28UL 1106#define TSDM_REG_DBG_DWORD_ENABLE \ 1107 0xfb0e2cUL 1108#define TSDM_REG_DBG_SHIFT \ 1109 0xfb0e30UL 1110#define TSDM_REG_DBG_FORCE_VALID \ 1111 0xfb0e34UL 1112#define TSDM_REG_DBG_FORCE_FRAME \ 1113 0xfb0e38UL 1114#define MSDM_REG_DBG_SELECT \ 1115 0xfc0e28UL 1116#define MSDM_REG_DBG_DWORD_ENABLE \ 1117 0xfc0e2cUL 1118#define MSDM_REG_DBG_SHIFT \ 1119 0xfc0e30UL 1120#define MSDM_REG_DBG_FORCE_VALID \ 1121 0xfc0e34UL 1122#define MSDM_REG_DBG_FORCE_FRAME \ 1123 0xfc0e38UL 1124#define USDM_REG_DBG_SELECT \ 1125 0xfd0e28UL 1126#define USDM_REG_DBG_DWORD_ENABLE \ 1127 0xfd0e2cUL 1128#define USDM_REG_DBG_SHIFT \ 1129 0xfd0e30UL 1130#define USDM_REG_DBG_FORCE_VALID \ 1131 0xfd0e34UL 1132#define USDM_REG_DBG_FORCE_FRAME \ 1133 0xfd0e38UL 1134#define XCM_REG_DBG_SELECT \ 1135 0x1000040UL 1136#define XCM_REG_DBG_DWORD_ENABLE \ 1137 0x1000044UL 1138#define XCM_REG_DBG_SHIFT \ 1139 0x1000048UL 1140#define XCM_REG_DBG_FORCE_VALID \ 1141 0x100004cUL 1142#define XCM_REG_DBG_FORCE_FRAME \ 1143 0x1000050UL 1144#define YCM_REG_DBG_SELECT \ 1145 0x1080040UL 1146#define YCM_REG_DBG_DWORD_ENABLE \ 1147 0x1080044UL 1148#define YCM_REG_DBG_SHIFT \ 1149 0x1080048UL 1150#define YCM_REG_DBG_FORCE_VALID \ 1151 0x108004cUL 1152#define YCM_REG_DBG_FORCE_FRAME \ 1153 0x1080050UL 1154#define PCM_REG_DBG_SELECT \ 1155 0x1100040UL 1156#define PCM_REG_DBG_DWORD_ENABLE \ 1157 0x1100044UL 1158#define PCM_REG_DBG_SHIFT \ 1159 0x1100048UL 1160#define PCM_REG_DBG_FORCE_VALID \ 1161 0x110004cUL 1162#define PCM_REG_DBG_FORCE_FRAME \ 1163 0x1100050UL 1164#define TCM_REG_DBG_SELECT \ 1165 0x1180040UL 1166#define TCM_REG_DBG_DWORD_ENABLE \ 1167 0x1180044UL 1168#define TCM_REG_DBG_SHIFT \ 1169 0x1180048UL 1170#define TCM_REG_DBG_FORCE_VALID \ 1171 0x118004cUL 1172#define TCM_REG_DBG_FORCE_FRAME \ 1173 0x1180050UL 1174#define MCM_REG_DBG_SELECT \ 1175 0x1200040UL 1176#define MCM_REG_DBG_DWORD_ENABLE \ 1177 0x1200044UL 1178#define MCM_REG_DBG_SHIFT \ 1179 0x1200048UL 1180#define MCM_REG_DBG_FORCE_VALID \ 1181 0x120004cUL 1182#define MCM_REG_DBG_FORCE_FRAME \ 1183 0x1200050UL 1184#define UCM_REG_DBG_SELECT \ 1185 0x1280050UL 1186#define UCM_REG_DBG_DWORD_ENABLE \ 1187 0x1280054UL 1188#define UCM_REG_DBG_SHIFT \ 1189 0x1280058UL 1190#define UCM_REG_DBG_FORCE_VALID \ 1191 0x128005cUL 1192#define UCM_REG_DBG_FORCE_FRAME \ 1193 0x1280060UL 1194#define XSEM_REG_DBG_SELECT \ 1195 0x1401528UL 1196#define XSEM_REG_DBG_DWORD_ENABLE \ 1197 0x140152cUL 1198#define XSEM_REG_DBG_SHIFT \ 1199 0x1401530UL 1200#define XSEM_REG_DBG_FORCE_VALID \ 1201 0x1401534UL 1202#define XSEM_REG_DBG_FORCE_FRAME \ 1203 0x1401538UL 1204#define YSEM_REG_DBG_SELECT \ 1205 0x1501528UL 1206#define YSEM_REG_DBG_DWORD_ENABLE \ 1207 0x150152cUL 1208#define YSEM_REG_DBG_SHIFT \ 1209 0x1501530UL 1210#define YSEM_REG_DBG_FORCE_VALID \ 1211 0x1501534UL 1212#define YSEM_REG_DBG_FORCE_FRAME \ 1213 0x1501538UL 1214#define PSEM_REG_DBG_SELECT \ 1215 0x1601528UL 1216#define PSEM_REG_DBG_DWORD_ENABLE \ 1217 0x160152cUL 1218#define PSEM_REG_DBG_SHIFT \ 1219 0x1601530UL 1220#define PSEM_REG_DBG_FORCE_VALID \ 1221 0x1601534UL 1222#define PSEM_REG_DBG_FORCE_FRAME \ 1223 0x1601538UL 1224#define TSEM_REG_DBG_SELECT \ 1225 0x1701528UL 1226#define TSEM_REG_DBG_DWORD_ENABLE \ 1227 0x170152cUL 1228#define TSEM_REG_DBG_SHIFT \ 1229 0x1701530UL 1230#define TSEM_REG_DBG_FORCE_VALID \ 1231 0x1701534UL 1232#define TSEM_REG_DBG_FORCE_FRAME \ 1233 0x1701538UL 1234#define DORQ_REG_PF_USAGE_CNT \ 1235 0x1009c0UL 1236#define DORQ_REG_PF_OVFL_STICKY \ 1237 0x1009d0UL 1238#define DORQ_REG_DPM_FORCE_ABORT \ 1239 0x1009d8UL 1240#define DORQ_REG_INT_STS \ 1241 0x100180UL 1242#define DORQ_REG_INT_STS_ADDRESS_ERROR \ 1243 (0x1UL << 0) 1244#define DORQ_REG_INT_STS_WR \ 1245 0x100188UL 1246#define DORQ_REG_DB_DROP_DETAILS_REL \ 1247 0x100a28UL 1248#define DORQ_REG_INT_STS_ADDRESS_ERROR_SHIFT \ 1249 0 1250#define DORQ_REG_INT_STS_DB_DROP \ 1251 (0x1UL << 1) 1252#define DORQ_REG_INT_STS_DB_DROP_SHIFT \ 1253 1 1254#define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR \ 1255 (0x1UL << 2) 1256#define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR_SHIFT \ 1257 2 1258#define DORQ_REG_INT_STS_DORQ_FIFO_AFULL\ 1259 (0x1UL << 3) 1260#define DORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT \ 1261 3 1262#define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR \ 1263 (0x1UL << 4) 1264#define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR_SHIFT \ 1265 4 1266#define DORQ_REG_INT_STS_CFC_LD_RESP_ERR \ 1267 (0x1UL << 5) 1268#define DORQ_REG_INT_STS_CFC_LD_RESP_ERR_SHIFT \ 1269 5 1270#define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR \ 1271 (0x1UL << 6) 1272#define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR_SHIFT \ 1273 6 1274#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR \ 1275 (0x1UL << 7) 1276#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT \ 1277 7 1278#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR \ 1279 (0x1UL << 8) 1280#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT \ 1281 8 1282#define DORQ_REG_DB_DROP_DETAILS_REASON \ 1283 0x100a20UL 1284#define MSEM_REG_DBG_SELECT \ 1285 0x1801528UL 1286#define MSEM_REG_DBG_DWORD_ENABLE \ 1287 0x180152cUL 1288#define MSEM_REG_DBG_SHIFT \ 1289 0x1801530UL 1290#define MSEM_REG_DBG_FORCE_VALID \ 1291 0x1801534UL 1292#define MSEM_REG_DBG_FORCE_FRAME \ 1293 0x1801538UL 1294#define USEM_REG_DBG_SELECT \ 1295 0x1901528UL 1296#define USEM_REG_DBG_DWORD_ENABLE \ 1297 0x190152cUL 1298#define USEM_REG_DBG_SHIFT \ 1299 0x1901530UL 1300#define USEM_REG_DBG_FORCE_VALID \ 1301 0x1901534UL 1302#define USEM_REG_DBG_FORCE_FRAME \ 1303 0x1901538UL 1304#define NWS_REG_DBG_SELECT_K2_E5 \ 1305 0x700128UL 1306#define NWS_REG_DBG_DWORD_ENABLE_K2_E5 \ 1307 0x70012cUL 1308#define NWS_REG_DBG_SHIFT_K2_E5 \ 1309 0x700130UL 1310#define NWS_REG_DBG_FORCE_VALID_K2_E5 \ 1311 0x700134UL 1312#define NWS_REG_DBG_FORCE_FRAME_K2_E5 \ 1313 0x700138UL 1314#define MS_REG_DBG_SELECT_K2_E5 \ 1315 0x6a0228UL 1316#define MS_REG_DBG_DWORD_ENABLE_K2_E5 \ 1317 0x6a022cUL 1318#define MS_REG_DBG_SHIFT_K2_E5 \ 1319 0x6a0230UL 1320#define MS_REG_DBG_FORCE_VALID_K2_E5 \ 1321 0x6a0234UL 1322#define MS_REG_DBG_FORCE_FRAME_K2_E5 \ 1323 0x6a0238UL 1324#define PCIE_REG_DBG_COMMON_SELECT_K2_E5 \ 1325 0x054398UL 1326#define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5 \ 1327 0x05439cUL 1328#define PCIE_REG_DBG_COMMON_SHIFT_K2_E5 \ 1329 0x0543a0UL 1330#define PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5 \ 1331 0x0543a4UL 1332#define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5 \ 1333 0x0543a8UL 1334#define PTLD_REG_DBG_SELECT_E5 \ 1335 0x5a1600UL 1336#define PTLD_REG_DBG_DWORD_ENABLE_E5 \ 1337 0x5a1604UL 1338#define PTLD_REG_DBG_SHIFT_E5 \ 1339 0x5a1608UL 1340#define PTLD_REG_DBG_FORCE_VALID_E5 \ 1341 0x5a160cUL 1342#define PTLD_REG_DBG_FORCE_FRAME_E5 \ 1343 0x5a1610UL 1344#define YPLD_REG_DBG_SELECT_E5 \ 1345 0x5c1600UL 1346#define YPLD_REG_DBG_DWORD_ENABLE_E5 \ 1347 0x5c1604UL 1348#define YPLD_REG_DBG_SHIFT_E5 \ 1349 0x5c1608UL 1350#define YPLD_REG_DBG_FORCE_VALID_E5 \ 1351 0x5c160cUL 1352#define YPLD_REG_DBG_FORCE_FRAME_E5 \ 1353 0x5c1610UL 1354#define RGSRC_REG_DBG_SELECT_E5 \ 1355 0x320040UL 1356#define RGSRC_REG_DBG_DWORD_ENABLE_E5 \ 1357 0x320044UL 1358#define RGSRC_REG_DBG_SHIFT_E5 \ 1359 0x320048UL 1360#define RGSRC_REG_DBG_FORCE_VALID_E5 \ 1361 0x32004cUL 1362#define RGSRC_REG_DBG_FORCE_FRAME_E5 \ 1363 0x320050UL 1364#define TGSRC_REG_DBG_SELECT_E5 \ 1365 0x322040UL 1366#define TGSRC_REG_DBG_DWORD_ENABLE_E5 \ 1367 0x322044UL 1368#define TGSRC_REG_DBG_SHIFT_E5 \ 1369 0x322048UL 1370#define TGSRC_REG_DBG_FORCE_VALID_E5 \ 1371 0x32204cUL 1372#define TGSRC_REG_DBG_FORCE_FRAME_E5 \ 1373 0x322050UL 1374#define MISC_REG_RESET_PL_UA \ 1375 0x008050UL 1376#define MISC_REG_RESET_PL_HV \ 1377 0x008060UL 1378#define XCM_REG_CTX_RBC_ACCS \ 1379 0x1001800UL 1380#define XCM_REG_AGG_CON_CTX \ 1381 0x1001804UL 1382#define XCM_REG_SM_CON_CTX \ 1383 0x1001808UL 1384#define YCM_REG_CTX_RBC_ACCS \ 1385 0x1081800UL 1386#define YCM_REG_AGG_CON_CTX \ 1387 0x1081804UL 1388#define YCM_REG_AGG_TASK_CTX \ 1389 0x1081808UL 1390#define YCM_REG_SM_CON_CTX \ 1391 0x108180cUL 1392#define YCM_REG_SM_TASK_CTX \ 1393 0x1081810UL 1394#define PCM_REG_CTX_RBC_ACCS \ 1395 0x1101440UL 1396#define PCM_REG_SM_CON_CTX \ 1397 0x1101444UL 1398#define TCM_REG_CTX_RBC_ACCS \ 1399 0x11814c0UL 1400#define TCM_REG_AGG_CON_CTX \ 1401 0x11814c4UL 1402#define TCM_REG_AGG_TASK_CTX \ 1403 0x11814c8UL 1404#define TCM_REG_SM_CON_CTX \ 1405 0x11814ccUL 1406#define TCM_REG_SM_TASK_CTX \ 1407 0x11814d0UL 1408#define MCM_REG_CTX_RBC_ACCS \ 1409 0x1201800UL 1410#define MCM_REG_AGG_CON_CTX \ 1411 0x1201804UL 1412#define MCM_REG_AGG_TASK_CTX \ 1413 0x1201808UL 1414#define MCM_REG_SM_CON_CTX \ 1415 0x120180cUL 1416#define MCM_REG_SM_TASK_CTX \ 1417 0x1201810UL 1418#define UCM_REG_CTX_RBC_ACCS \ 1419 0x1281700UL 1420#define UCM_REG_AGG_CON_CTX \ 1421 0x1281704UL 1422#define UCM_REG_AGG_TASK_CTX \ 1423 0x1281708UL 1424#define UCM_REG_SM_CON_CTX \ 1425 0x128170cUL 1426#define UCM_REG_SM_TASK_CTX \ 1427 0x1281710UL 1428#define XSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1429 0x1401140UL 1430#define XSEM_REG_SYNC_DBG_EMPTY \ 1431 0x1401160UL 1432#define XSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1433 0x1401400UL 1434#define XSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1435 0x1401404UL 1436#define XSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1437 0x1401408UL 1438#define XSEM_REG_DBG_GPRE_VECT \ 1439 0x1401410UL 1440#define XSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1441 0x1401420UL 1442#define XSEM_REG_FAST_MEMORY \ 1443 0x1440000UL 1444#define YSEM_REG_SYNC_DBG_EMPTY \ 1445 0x1501160UL 1446#define YSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1447 0x1501400UL 1448#define YSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1449 0x1501404UL 1450#define YSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1451 0x1501408UL 1452#define YSEM_REG_DBG_GPRE_VECT \ 1453 0x1501410UL 1454#define YSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1455 0x1501420UL 1456#define YSEM_REG_FAST_MEMORY \ 1457 0x1540000UL 1458#define PSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1459 0x1601140UL 1460#define PSEM_REG_SYNC_DBG_EMPTY \ 1461 0x1601160UL 1462#define PSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1463 0x1601400UL 1464#define PSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1465 0x1601404UL 1466#define PSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1467 0x1601408UL 1468#define PSEM_REG_DBG_GPRE_VECT \ 1469 0x1601410UL 1470#define PSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1471 0x1601420UL 1472#define PSEM_REG_FAST_MEMORY \ 1473 0x1640000UL 1474#define TSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1475 0x1701140UL 1476#define TSEM_REG_SYNC_DBG_EMPTY \ 1477 0x1701160UL 1478#define TSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1479 0x1701400UL 1480#define TSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1481 0x1701404UL 1482#define TSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1483 0x1701408UL 1484#define TSEM_REG_DBG_GPRE_VECT \ 1485 0x1701410UL 1486#define TSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1487 0x1701420UL 1488#define TSEM_REG_FAST_MEMORY \ 1489 0x1740000UL 1490#define MSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1491 0x1801140UL 1492#define MSEM_REG_SYNC_DBG_EMPTY \ 1493 0x1801160UL 1494#define MSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1495 0x1801400UL 1496#define MSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1497 0x1801404UL 1498#define MSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1499 0x1801408UL 1500#define MSEM_REG_DBG_GPRE_VECT \ 1501 0x1801410UL 1502#define MSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1503 0x1801420UL 1504#define MSEM_REG_FAST_MEMORY \ 1505 0x1840000UL 1506#define USEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1507 0x1901140UL 1508#define SEM_FAST_REG_INT_RAM_SIZE \ 1509 20480 1510#define USEM_REG_SYNC_DBG_EMPTY \ 1511 0x1901160UL 1512#define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1513 0x1901400UL 1514#define USEM_REG_SLOW_DBG_MODE_BB_K2 \ 1515 0x1901404UL 1516#define USEM_REG_DBG_FRAME_MODE_BB_K2 \ 1517 0x1901408UL 1518#define USEM_REG_DBG_GPRE_VECT \ 1519 0x1901410UL 1520#define USEM_REG_DBG_MODE1_CFG_BB_K2 \ 1521 0x1901420UL 1522#define USEM_REG_FAST_MEMORY \ 1523 0x1940000UL 1524#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE \ 1525 0x000748UL 1526#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE \ 1527 0x00074cUL 1528#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE \ 1529 0x000750UL 1530#define SEM_FAST_REG_DEBUG_ACTIVE \ 1531 0x000740UL 1532#define SEM_FAST_REG_INT_RAM \ 1533 0x020000UL 1534#define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \ 1535 20480 1536#define SEM_FAST_REG_RECORD_FILTER_ENABLE \ 1537 0x000768UL 1538#define GRC_REG_TRACE_FIFO_VALID_DATA \ 1539 0x050064UL 1540#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \ 1541 0x05040cUL 1542#define GRC_REG_PROTECTION_OVERRIDE_WINDOW \ 1543 0x050500UL 1544#define IGU_REG_ERROR_HANDLING_MEMORY \ 1545 0x181520UL 1546#define MCP_REG_CPU_MODE \ 1547 0xe05000UL 1548#define MCP_REG_CPU_MODE_SOFT_HALT \ 1549 (0x1 << 10) 1550#define BRB_REG_BIG_RAM_ADDRESS \ 1551 0x340800UL 1552#define BRB_REG_BIG_RAM_DATA \ 1553 0x341500UL 1554#define BRB_REG_BIG_RAM_DATA_SIZE \ 1555 64 1556#define SEM_FAST_REG_STALL_0_BB_K2 \ 1557 0x000488UL 1558#define SEM_FAST_REG_STALLED \ 1559 0x000494UL 1560#define BTB_REG_BIG_RAM_ADDRESS \ 1561 0xdb0800UL 1562#define BTB_REG_BIG_RAM_DATA \ 1563 0xdb0c00UL 1564#define BMB_REG_BIG_RAM_ADDRESS \ 1565 0x540800UL 1566#define BMB_REG_BIG_RAM_DATA \ 1567 0x540f00UL 1568#define SEM_FAST_REG_STORM_REG_FILE \ 1569 0x008000UL 1570#define RSS_REG_RSS_RAM_ADDR \ 1571 0x238c30UL 1572#define MISCS_REG_BLOCK_256B_EN \ 1573 0x009074UL 1574#define MCP_REG_SCRATCH_SIZE_BB_K2 \ 1575 57344 1576#define MCP_REG_CPU_REG_FILE \ 1577 0xe05200UL 1578#define MCP_REG_CPU_REG_FILE_SIZE \ 1579 32 1580#define DBG_REG_DEBUG_TARGET \ 1581 0x01005cUL 1582#define DBG_REG_FULL_MODE \ 1583 0x010060UL 1584#define DBG_REG_CALENDAR_OUT_DATA \ 1585 0x010480UL 1586#define GRC_REG_TRACE_FIFO \ 1587 0x050068UL 1588#define IGU_REG_ERROR_HANDLING_DATA_VALID \ 1589 0x181530UL 1590#define DBG_REG_DBG_BLOCK_ON \ 1591 0x010454UL 1592#define DBG_REG_FILTER_ENABLE \ 1593 0x0109d0UL 1594#define DBG_REG_FRAMING_MODE \ 1595 0x010058UL 1596#define DBG_REG_TRIGGER_ENABLE \ 1597 0x01054cUL 1598#define SEM_FAST_REG_VFC_DATA_WR \ 1599 0x000b40UL 1600#define SEM_FAST_REG_VFC_ADDR \ 1601 0x000b44UL 1602#define SEM_FAST_REG_VFC_DATA_RD \ 1603 0x000b48UL 1604#define SEM_FAST_REG_VFC_STATUS \ 1605 0x000b4cUL 1606#define RSS_REG_RSS_RAM_DATA \ 1607 0x238c20UL 1608#define RSS_REG_RSS_RAM_DATA_SIZE \ 1609 4 1610#define MISC_REG_BLOCK_256B_EN \ 1611 0x008c14UL 1612#define NWS_REG_NWS_CMU_K2 \ 1613 0x720000UL 1614#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5 \ 1615 0x000680UL 1616#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5 \ 1617 0x000684UL 1618#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5 \ 1619 0x0006c0UL 1620#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 \ 1621 0x0006c4UL 1622#define MS_REG_MS_CMU_K2_E5 \ 1623 0x6a4000UL 1624#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \ 1625 0x000208UL 1626#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \ 1627 0x00020cUL 1628#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \ 1629 0x000210UL 1630#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \ 1631 0x000214UL 1632#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \ 1633 0x000208UL 1634#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \ 1635 0x00020cUL 1636#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \ 1637 0x000210UL 1638#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \ 1639 0x000214UL 1640#define PHY_PCIE_REG_PHY0_K2_E5 \ 1641 0x620000UL 1642#define PHY_PCIE_REG_PHY1_K2_E5 \ 1643 0x624000UL 1644#define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL 1645#define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL 1646#define NIG_REG_PPF_TO_ENGINE_SEL_SIZE 8 1647#define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL 1648#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL 1649#define DORQ_REG_PF_DPM_ENABLE 0x100510UL 1650#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL 1651#define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL 1652#define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL 1653#define NIG_REG_RX_PTP_EN 0x501900UL 1654#define NIG_REG_TX_PTP_EN 0x501904UL 1655#define NIG_REG_LLH_PTP_TO_HOST 0x501908UL 1656#define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL 1657#define NIG_REG_PTP_SW_TXTSEN 0x501910UL 1658#define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL 1659#define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL 1660#define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL 1661#define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL 1662#define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL 1663#define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL 1664#define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL 1665#define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL 1666#define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL 1667#define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL 1668#define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL 1669#define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL 1670#define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL 1671#define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL 1672#define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL 1673#define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL 1674#define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL 1675#define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL 1676#define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL 1677#define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL 1678#define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL 1679#define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL 1680#define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL 1681#define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL 1682#define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL 1683#define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL 1684#define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL 1685#define PSWRQ2_REG_WR_MBS0 0x240400UL 1686 1687#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL 1688#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL 1689#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL 1690#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL 1691#define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL 1692#define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL 1693#define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL 1694 1695#define NIG_REG_TX_EDPM_CTRL 0x501f0cUL 1696#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN (0x1 << 0) 1697#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT 0 1698#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN (0xff << 1) 1699#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT 1 1700 1701#define PRS_REG_SEARCH_GFT 0x1f11bcUL 1702#define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL 1703#define PRS_REG_CM_HDR_GFT 0x1f11c8UL 1704#define PRS_REG_GFT_CAM 0x1f1100UL 1705#define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL 1706#define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0 1707#define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8 1708#define PRS_REG_LOAD_L2_FILTER 0x1f0198UL 1709 1710#endif 1711