1
2
3
4
5
6#ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
7#define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
8
9#include "davinci_cpdma.h"
10
11#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
12 NETIF_MSG_DRV | NETIF_MSG_LINK | \
13 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
14 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
15 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
16 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
17 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
18 NETIF_MSG_RX_STATUS)
19
20#define cpsw_info(priv, type, format, ...) \
21do { \
22 if (netif_msg_##type(priv) && net_ratelimit()) \
23 dev_info(priv->dev, format, ## __VA_ARGS__); \
24} while (0)
25
26#define cpsw_err(priv, type, format, ...) \
27do { \
28 if (netif_msg_##type(priv) && net_ratelimit()) \
29 dev_err(priv->dev, format, ## __VA_ARGS__); \
30} while (0)
31
32#define cpsw_dbg(priv, type, format, ...) \
33do { \
34 if (netif_msg_##type(priv) && net_ratelimit()) \
35 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
36} while (0)
37
38#define cpsw_notice(priv, type, format, ...) \
39do { \
40 if (netif_msg_##type(priv) && net_ratelimit()) \
41 dev_notice(priv->dev, format, ## __VA_ARGS__); \
42} while (0)
43
44#define ALE_ALL_PORTS 0x7
45
46#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
47#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
48#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
49
50#define CPSW_VERSION_1 0x19010a
51#define CPSW_VERSION_2 0x19010c
52#define CPSW_VERSION_3 0x19010f
53#define CPSW_VERSION_4 0x190112
54
55#define HOST_PORT_NUM 0
56#define CPSW_ALE_PORTS_NUM 3
57#define CPSW_SLAVE_PORTS_NUM 2
58#define SLIVER_SIZE 0x40
59
60#define CPSW1_HOST_PORT_OFFSET 0x028
61#define CPSW1_SLAVE_OFFSET 0x050
62#define CPSW1_SLAVE_SIZE 0x040
63#define CPSW1_CPDMA_OFFSET 0x100
64#define CPSW1_STATERAM_OFFSET 0x200
65#define CPSW1_HW_STATS 0x400
66#define CPSW1_CPTS_OFFSET 0x500
67#define CPSW1_ALE_OFFSET 0x600
68#define CPSW1_SLIVER_OFFSET 0x700
69#define CPSW1_WR_OFFSET 0x900
70
71#define CPSW2_HOST_PORT_OFFSET 0x108
72#define CPSW2_SLAVE_OFFSET 0x200
73#define CPSW2_SLAVE_SIZE 0x100
74#define CPSW2_CPDMA_OFFSET 0x800
75#define CPSW2_HW_STATS 0x900
76#define CPSW2_STATERAM_OFFSET 0xa00
77#define CPSW2_CPTS_OFFSET 0xc00
78#define CPSW2_ALE_OFFSET 0xd00
79#define CPSW2_SLIVER_OFFSET 0xd80
80#define CPSW2_BD_OFFSET 0x2000
81#define CPSW2_WR_OFFSET 0x1200
82
83#define CPDMA_RXTHRESH 0x0c0
84#define CPDMA_RXFREE 0x0e0
85#define CPDMA_TXHDP 0x00
86#define CPDMA_RXHDP 0x20
87#define CPDMA_TXCP 0x40
88#define CPDMA_RXCP 0x60
89
90#define CPSW_POLL_WEIGHT 64
91#define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4
92#define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN)
93#define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\
94 ETH_FCS_LEN +\
95 CPSW_RX_VLAN_ENCAP_HDR_SIZE)
96
97#define RX_PRIORITY_MAPPING 0x76543210
98#define TX_PRIORITY_MAPPING 0x33221100
99#define CPDMA_TX_PRIORITY_MAP 0x76543210
100
101#define CPSW_VLAN_AWARE BIT(1)
102#define CPSW_RX_VLAN_ENCAP BIT(2)
103#define CPSW_ALE_VLAN_AWARE 1
104
105#define CPSW_FIFO_NORMAL_MODE (0 << 16)
106#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
107#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
108
109#define CPSW_INTPACEEN (0x3f << 16)
110#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
111#define CPSW_CMINTMAX_CNT 63
112#define CPSW_CMINTMIN_CNT 2
113#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
114#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
115
116#define IRQ_NUM 2
117#define CPSW_MAX_QUEUES 8
118#define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
119#define CPSW_ALE_AGEOUT_DEFAULT 10
120#define CPSW_FIFO_QUEUE_TYPE_SHIFT 16
121#define CPSW_FIFO_SHAPE_EN_SHIFT 16
122#define CPSW_FIFO_RATE_EN_SHIFT 20
123#define CPSW_TC_NUM 4
124#define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1)
125#define CPSW_PCT_MASK 0x7f
126#define CPSW_BD_RAM_SIZE 0x2000
127
128#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29
129#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0)
130#define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16
131#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8
132#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0)
133enum {
134 CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
135 CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
136 CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
137 CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
138};
139
140struct cpsw_wr_regs {
141 u32 id_ver;
142 u32 soft_reset;
143 u32 control;
144 u32 int_control;
145 u32 rx_thresh_en;
146 u32 rx_en;
147 u32 tx_en;
148 u32 misc_en;
149 u32 mem_allign1[8];
150 u32 rx_thresh_stat;
151 u32 rx_stat;
152 u32 tx_stat;
153 u32 misc_stat;
154 u32 mem_allign2[8];
155 u32 rx_imax;
156 u32 tx_imax;
157
158};
159
160struct cpsw_ss_regs {
161 u32 id_ver;
162 u32 control;
163 u32 soft_reset;
164 u32 stat_port_en;
165 u32 ptype;
166 u32 soft_idle;
167 u32 thru_rate;
168 u32 gap_thresh;
169 u32 tx_start_wds;
170 u32 flow_control;
171 u32 vlan_ltype;
172 u32 ts_ltype;
173 u32 dlr_ltype;
174};
175
176
177#define CPSW1_MAX_BLKS 0x00
178#define CPSW1_BLK_CNT 0x04
179#define CPSW1_TX_IN_CTL 0x08
180#define CPSW1_PORT_VLAN 0x0c
181#define CPSW1_TX_PRI_MAP 0x10
182#define CPSW1_TS_CTL 0x14
183#define CPSW1_TS_SEQ_LTYPE 0x18
184#define CPSW1_TS_VLAN 0x1c
185
186
187#define CPSW2_CONTROL 0x00
188#define CPSW2_MAX_BLKS 0x08
189#define CPSW2_BLK_CNT 0x0c
190#define CPSW2_TX_IN_CTL 0x10
191#define CPSW2_PORT_VLAN 0x14
192#define CPSW2_TX_PRI_MAP 0x18
193#define CPSW2_TS_SEQ_MTYPE 0x1c
194
195
196#define SA_LO 0x20
197#define SA_HI 0x24
198#define SEND_PERCENT 0x28
199
200
201#define RX_DSCP_PRI_MAP0 0x30
202#define RX_DSCP_PRI_MAP1 0x34
203#define RX_DSCP_PRI_MAP2 0x38
204#define RX_DSCP_PRI_MAP3 0x3c
205#define RX_DSCP_PRI_MAP4 0x40
206#define RX_DSCP_PRI_MAP5 0x44
207#define RX_DSCP_PRI_MAP6 0x48
208#define RX_DSCP_PRI_MAP7 0x4c
209
210
211#define PASS_PRI_TAGGED BIT(24)
212#define VLAN_LTYPE2_EN BIT(21)
213#define VLAN_LTYPE1_EN BIT(20)
214#define DSCP_PRI_EN BIT(16)
215#define TS_107 BIT(15)
216#define TS_320 BIT(14)
217#define TS_319 BIT(13)
218#define TS_132 BIT(12)
219#define TS_131 BIT(11)
220#define TS_130 BIT(10)
221#define TS_129 BIT(9)
222#define TS_TTL_NONZERO BIT(8)
223#define TS_ANNEX_F_EN BIT(6)
224#define TS_ANNEX_D_EN BIT(4)
225#define TS_LTYPE2_EN BIT(3)
226#define TS_LTYPE1_EN BIT(2)
227#define TS_TX_EN BIT(1)
228#define TS_RX_EN BIT(0)
229
230#define CTRL_V2_TS_BITS \
231 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
232 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN)
233
234#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
235#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
236#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
237
238
239#define CTRL_V3_TS_BITS \
240 (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
241 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
242 TS_LTYPE1_EN | VLAN_LTYPE1_EN)
243
244#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
245#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
246#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
247
248
249#define TS_SEQ_ID_OFFSET_SHIFT (16)
250#define TS_SEQ_ID_OFFSET_MASK (0x3f)
251#define TS_MSG_TYPE_EN_SHIFT (0)
252#define TS_MSG_TYPE_EN_MASK (0xffff)
253
254
255#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
256
257
258#define CPSW_V1_TS_RX_EN BIT(0)
259#define CPSW_V1_TS_TX_EN BIT(4)
260#define CPSW_V1_MSG_TYPE_OFS 16
261
262
263#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
264
265#define CPSW_MAX_BLKS_TX 15
266#define CPSW_MAX_BLKS_TX_SHIFT 4
267#define CPSW_MAX_BLKS_RX 5
268
269struct cpsw_host_regs {
270 u32 max_blks;
271 u32 blk_cnt;
272 u32 tx_in_ctl;
273 u32 port_vlan;
274 u32 tx_pri_map;
275 u32 cpdma_tx_pri_map;
276 u32 cpdma_rx_chan_map;
277};
278
279struct cpsw_slave_data {
280 struct device_node *slave_node;
281 struct device_node *phy_node;
282 char phy_id[MII_BUS_ID_SIZE];
283 phy_interface_t phy_if;
284 u8 mac_addr[ETH_ALEN];
285 u16 dual_emac_res_vlan;
286 struct phy *ifphy;
287 bool disabled;
288};
289
290struct cpsw_platform_data {
291 struct cpsw_slave_data *slave_data;
292 u32 ss_reg_ofs;
293 u32 channels;
294 u32 slaves;
295 u32 active_slave;
296 u32 bd_ram_size;
297 u32 mac_control;
298 u16 default_vlan;
299 bool dual_emac;
300};
301
302struct cpsw_slave {
303 void __iomem *regs;
304 int slave_num;
305 u32 mac_control;
306 struct cpsw_slave_data *data;
307 struct phy_device *phy;
308 struct net_device *ndev;
309 u32 port_vlan;
310 struct cpsw_sl *mac_sl;
311};
312
313static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
314{
315 return readl_relaxed(slave->regs + offset);
316}
317
318static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
319{
320 writel_relaxed(val, slave->regs + offset);
321}
322
323struct cpsw_vector {
324 struct cpdma_chan *ch;
325 int budget;
326};
327
328struct cpsw_common {
329 struct device *dev;
330 struct cpsw_platform_data data;
331 struct napi_struct napi_rx;
332 struct napi_struct napi_tx;
333 struct cpsw_ss_regs __iomem *regs;
334 struct cpsw_wr_regs __iomem *wr_regs;
335 u8 __iomem *hw_stats;
336 struct cpsw_host_regs __iomem *host_port_regs;
337 u32 version;
338 u32 coal_intvl;
339 u32 bus_freq_mhz;
340 int rx_packet_max;
341 int descs_pool_size;
342 struct cpsw_slave *slaves;
343 struct cpdma_ctlr *dma;
344 struct cpsw_vector txv[CPSW_MAX_QUEUES];
345 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
346 struct cpsw_ale *ale;
347 bool quirk_irq;
348 bool rx_irq_disabled;
349 bool tx_irq_disabled;
350 u32 irqs_table[IRQ_NUM];
351 int misc_irq;
352 struct cpts *cpts;
353 struct devlink *devlink;
354 int rx_ch_num, tx_ch_num;
355 int speed;
356 int usage_count;
357 struct page_pool *page_pool[CPSW_MAX_QUEUES];
358 u8 br_members;
359 struct net_device *hw_bridge_dev;
360 bool ale_bypass;
361 u8 base_mac[ETH_ALEN];
362};
363
364struct cpsw_priv {
365 struct net_device *ndev;
366 struct device *dev;
367 u32 msg_enable;
368 u8 mac_addr[ETH_ALEN];
369 bool rx_pause;
370 bool tx_pause;
371 bool mqprio_hw;
372 int fifo_bw[CPSW_TC_NUM];
373 int shp_cfg_speed;
374 int tx_ts_enabled;
375 int rx_ts_enabled;
376 struct bpf_prog *xdp_prog;
377 struct xdp_rxq_info xdp_rxq[CPSW_MAX_QUEUES];
378 struct xdp_attachment_info xdpi;
379
380 u32 emac_port;
381 struct cpsw_common *cpsw;
382 int offload_fwd_mark;
383};
384
385#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
386#define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
387
388extern int (*cpsw_slave_index)(struct cpsw_common *cpsw,
389 struct cpsw_priv *priv);
390
391struct addr_sync_ctx {
392 struct net_device *ndev;
393 const u8 *addr;
394 int consumed;
395 int flush;
396};
397
398#define CPSW_XMETA_OFFSET ALIGN(sizeof(struct xdp_frame), sizeof(long))
399
400#define CPSW_XDP_CONSUMED 1
401#define CPSW_XDP_PASS 0
402
403struct __aligned(sizeof(long)) cpsw_meta_xdp {
404 struct net_device *ndev;
405 int ch;
406};
407
408
409#define CPSW_HEADROOM_NA (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + NET_IP_ALIGN)
410#define CPSW_HEADROOM ALIGN(CPSW_HEADROOM_NA, sizeof(long))
411
412static inline int cpsw_is_xdpf_handle(void *handle)
413{
414 return (unsigned long)handle & BIT(0);
415}
416
417static inline void *cpsw_xdpf_to_handle(struct xdp_frame *xdpf)
418{
419 return (void *)((unsigned long)xdpf | BIT(0));
420}
421
422static inline struct xdp_frame *cpsw_handle_to_xdpf(void *handle)
423{
424 return (struct xdp_frame *)((unsigned long)handle & ~BIT(0));
425}
426
427int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs,
428 int ale_ageout, phys_addr_t desc_mem_phys,
429 int descs_pool_size);
430void cpsw_split_res(struct cpsw_common *cpsw);
431int cpsw_fill_rx_channels(struct cpsw_priv *priv);
432void cpsw_intr_enable(struct cpsw_common *cpsw);
433void cpsw_intr_disable(struct cpsw_common *cpsw);
434void cpsw_tx_handler(void *token, int len, int status);
435int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw);
436void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw);
437int cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf);
438int cpsw_xdp_tx_frame(struct cpsw_priv *priv, struct xdp_frame *xdpf,
439 struct page *page, int port);
440int cpsw_run_xdp(struct cpsw_priv *priv, int ch, struct xdp_buff *xdp,
441 struct page *page, int port, int *len);
442irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id);
443irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id);
444irqreturn_t cpsw_misc_interrupt(int irq, void *dev_id);
445int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget);
446int cpsw_tx_poll(struct napi_struct *napi_tx, int budget);
447int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget);
448int cpsw_rx_poll(struct napi_struct *napi_rx, int budget);
449void cpsw_rx_vlan_encap(struct sk_buff *skb);
450void soft_reset(const char *module, void __iomem *reg);
451void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv);
452void cpsw_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue);
453int cpsw_need_resplit(struct cpsw_common *cpsw);
454int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd);
455int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate);
456int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
457 void *type_data);
458bool cpsw_shp_is_off(struct cpsw_priv *priv);
459void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv);
460void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv);
461
462
463u32 cpsw_get_msglevel(struct net_device *ndev);
464void cpsw_set_msglevel(struct net_device *ndev, u32 value);
465int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal);
466int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal);
467int cpsw_get_sset_count(struct net_device *ndev, int sset);
468void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data);
469void cpsw_get_ethtool_stats(struct net_device *ndev,
470 struct ethtool_stats *stats, u64 *data);
471void cpsw_get_pauseparam(struct net_device *ndev,
472 struct ethtool_pauseparam *pause);
473void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
474int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
475int cpsw_get_regs_len(struct net_device *ndev);
476void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p);
477int cpsw_ethtool_op_begin(struct net_device *ndev);
478void cpsw_ethtool_op_complete(struct net_device *ndev);
479void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch);
480int cpsw_get_link_ksettings(struct net_device *ndev,
481 struct ethtool_link_ksettings *ecmd);
482int cpsw_set_link_ksettings(struct net_device *ndev,
483 const struct ethtool_link_ksettings *ecmd);
484int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata);
485int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata);
486int cpsw_nway_reset(struct net_device *ndev);
487void cpsw_get_ringparam(struct net_device *ndev,
488 struct ethtool_ringparam *ering);
489int cpsw_set_ringparam(struct net_device *ndev,
490 struct ethtool_ringparam *ering);
491int cpsw_set_channels_common(struct net_device *ndev,
492 struct ethtool_channels *chs,
493 cpdma_handler_fn rx_handler);
494int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info);
495
496#endif
497