linux/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
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   1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2/*
   3 * Copyright (C) 2005-2014, 2018-2020 Intel Corporation
   4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
   5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
   6 */
   7#include <linux/types.h>
   8#include <linux/slab.h>
   9#include <linux/export.h>
  10#include <linux/etherdevice.h>
  11#include <linux/pci.h>
  12#include <linux/firmware.h>
  13
  14#include "iwl-drv.h"
  15#include "iwl-modparams.h"
  16#include "iwl-nvm-parse.h"
  17#include "iwl-prph.h"
  18#include "iwl-io.h"
  19#include "iwl-csr.h"
  20#include "fw/acpi.h"
  21#include "fw/api/nvm-reg.h"
  22#include "fw/api/commands.h"
  23#include "fw/api/cmdhdr.h"
  24#include "fw/img.h"
  25
  26/* NVM offsets (in words) definitions */
  27enum nvm_offsets {
  28        /* NVM HW-Section offset (in words) definitions */
  29        SUBSYSTEM_ID = 0x0A,
  30        HW_ADDR = 0x15,
  31
  32        /* NVM SW-Section offset (in words) definitions */
  33        NVM_SW_SECTION = 0x1C0,
  34        NVM_VERSION = 0,
  35        RADIO_CFG = 1,
  36        SKU = 2,
  37        N_HW_ADDRS = 3,
  38        NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
  39
  40        /* NVM calibration section offset (in words) definitions */
  41        NVM_CALIB_SECTION = 0x2B8,
  42        XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
  43
  44        /* NVM REGULATORY -Section offset (in words) definitions */
  45        NVM_CHANNELS_SDP = 0,
  46};
  47
  48enum ext_nvm_offsets {
  49        /* NVM HW-Section offset (in words) definitions */
  50        MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
  51
  52        /* NVM SW-Section offset (in words) definitions */
  53        NVM_VERSION_EXT_NVM = 0,
  54        N_HW_ADDRS_FAMILY_8000 = 3,
  55
  56        /* NVM PHY_SKU-Section offset (in words) definitions */
  57        RADIO_CFG_FAMILY_EXT_NVM = 0,
  58        SKU_FAMILY_8000 = 2,
  59
  60        /* NVM REGULATORY -Section offset (in words) definitions */
  61        NVM_CHANNELS_EXTENDED = 0,
  62        NVM_LAR_OFFSET_OLD = 0x4C7,
  63        NVM_LAR_OFFSET = 0x507,
  64        NVM_LAR_ENABLED = 0x7,
  65};
  66
  67/* SKU Capabilities (actual values from NVM definition) */
  68enum nvm_sku_bits {
  69        NVM_SKU_CAP_BAND_24GHZ          = BIT(0),
  70        NVM_SKU_CAP_BAND_52GHZ          = BIT(1),
  71        NVM_SKU_CAP_11N_ENABLE          = BIT(2),
  72        NVM_SKU_CAP_11AC_ENABLE         = BIT(3),
  73        NVM_SKU_CAP_MIMO_DISABLE        = BIT(5),
  74};
  75
  76/*
  77 * These are the channel numbers in the order that they are stored in the NVM
  78 */
  79static const u16 iwl_nvm_channels[] = {
  80        /* 2.4 GHz */
  81        1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  82        /* 5 GHz */
  83        36, 40, 44 , 48, 52, 56, 60, 64,
  84        100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  85        149, 153, 157, 161, 165
  86};
  87
  88static const u16 iwl_ext_nvm_channels[] = {
  89        /* 2.4 GHz */
  90        1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  91        /* 5 GHz */
  92        36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
  93        96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  94        149, 153, 157, 161, 165, 169, 173, 177, 181
  95};
  96
  97static const u16 iwl_uhb_nvm_channels[] = {
  98        /* 2.4 GHz */
  99        1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 100        /* 5 GHz */
 101        36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
 102        96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
 103        149, 153, 157, 161, 165, 169, 173, 177, 181,
 104        /* 6-7 GHz */
 105        1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
 106        73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
 107        133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
 108        189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
 109};
 110
 111#define IWL_NVM_NUM_CHANNELS            ARRAY_SIZE(iwl_nvm_channels)
 112#define IWL_NVM_NUM_CHANNELS_EXT        ARRAY_SIZE(iwl_ext_nvm_channels)
 113#define IWL_NVM_NUM_CHANNELS_UHB        ARRAY_SIZE(iwl_uhb_nvm_channels)
 114#define NUM_2GHZ_CHANNELS               14
 115#define NUM_5GHZ_CHANNELS               37
 116#define FIRST_2GHZ_HT_MINUS             5
 117#define LAST_2GHZ_HT_PLUS               9
 118#define N_HW_ADDR_MASK                  0xF
 119
 120/* rate data (static) */
 121static struct ieee80211_rate iwl_cfg80211_rates[] = {
 122        { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
 123        { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
 124          .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
 125        { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
 126          .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
 127        { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
 128          .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
 129        { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
 130        { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
 131        { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
 132        { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
 133        { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
 134        { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
 135        { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
 136        { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
 137};
 138#define RATES_24_OFFS   0
 139#define N_RATES_24      ARRAY_SIZE(iwl_cfg80211_rates)
 140#define RATES_52_OFFS   4
 141#define N_RATES_52      (N_RATES_24 - RATES_52_OFFS)
 142
 143/**
 144 * enum iwl_nvm_channel_flags - channel flags in NVM
 145 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
 146 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
 147 * @NVM_CHANNEL_ACTIVE: active scanning allowed
 148 * @NVM_CHANNEL_RADAR: radar detection required
 149 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
 150 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
 151 *      on same channel on 2.4 or same UNII band on 5.2
 152 * @NVM_CHANNEL_UNIFORM: uniform spreading required
 153 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
 154 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
 155 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
 156 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
 157 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
 158 */
 159enum iwl_nvm_channel_flags {
 160        NVM_CHANNEL_VALID               = BIT(0),
 161        NVM_CHANNEL_IBSS                = BIT(1),
 162        NVM_CHANNEL_ACTIVE              = BIT(3),
 163        NVM_CHANNEL_RADAR               = BIT(4),
 164        NVM_CHANNEL_INDOOR_ONLY         = BIT(5),
 165        NVM_CHANNEL_GO_CONCURRENT       = BIT(6),
 166        NVM_CHANNEL_UNIFORM             = BIT(7),
 167        NVM_CHANNEL_20MHZ               = BIT(8),
 168        NVM_CHANNEL_40MHZ               = BIT(9),
 169        NVM_CHANNEL_80MHZ               = BIT(10),
 170        NVM_CHANNEL_160MHZ              = BIT(11),
 171        NVM_CHANNEL_DC_HIGH             = BIT(12),
 172};
 173
 174/**
 175 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory
 176 * domain.
 177 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
 178 *      2.4Ghz band is allowed.
 179 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
 180 *      5Ghz band is allowed.
 181 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
 182 *      for this regulatory domain (valid only in 5Ghz).
 183 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
 184 *      for this regulatory domain (valid only in 5Ghz).
 185 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
 186 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
 187 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
 188 *      for this regulatory domain (valid only in 5Ghz).
 189 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed.
 190 * @REG_CAPA_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
 191 */
 192enum iwl_reg_capa_flags {
 193        REG_CAPA_BF_CCD_LOW_BAND        = BIT(0),
 194        REG_CAPA_BF_CCD_HIGH_BAND       = BIT(1),
 195        REG_CAPA_160MHZ_ALLOWED         = BIT(2),
 196        REG_CAPA_80MHZ_ALLOWED          = BIT(3),
 197        REG_CAPA_MCS_8_ALLOWED          = BIT(4),
 198        REG_CAPA_MCS_9_ALLOWED          = BIT(5),
 199        REG_CAPA_40MHZ_FORBIDDEN        = BIT(7),
 200        REG_CAPA_DC_HIGH_ENABLED        = BIT(9),
 201        REG_CAPA_11AX_DISABLED          = BIT(10),
 202};
 203
 204/**
 205 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory
 206 * domain (version 2).
 207 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are
 208 *      disabled.
 209 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
 210 *      2.4Ghz band is allowed.
 211 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
 212 *      5Ghz band is allowed.
 213 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
 214 *      for this regulatory domain (valid only in 5Ghz).
 215 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
 216 *      for this regulatory domain (valid only in 5Ghz).
 217 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
 218 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
 219 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118,
 220 *      126, 122) are disabled.
 221 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed
 222 *      for this regulatory domain (uvalid only in 5Ghz).
 223 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
 224 */
 225enum iwl_reg_capa_flags_v2 {
 226        REG_CAPA_V2_STRADDLE_DISABLED   = BIT(0),
 227        REG_CAPA_V2_BF_CCD_LOW_BAND     = BIT(1),
 228        REG_CAPA_V2_BF_CCD_HIGH_BAND    = BIT(2),
 229        REG_CAPA_V2_160MHZ_ALLOWED      = BIT(3),
 230        REG_CAPA_V2_80MHZ_ALLOWED       = BIT(4),
 231        REG_CAPA_V2_MCS_8_ALLOWED       = BIT(5),
 232        REG_CAPA_V2_MCS_9_ALLOWED       = BIT(6),
 233        REG_CAPA_V2_WEATHER_DISABLED    = BIT(7),
 234        REG_CAPA_V2_40MHZ_ALLOWED       = BIT(8),
 235        REG_CAPA_V2_11AX_DISABLED       = BIT(10),
 236};
 237
 238/*
 239* API v2 for reg_capa_flags is relevant from version 6 and onwards of the
 240* MCC update command response.
 241*/
 242#define REG_CAPA_V2_RESP_VER    6
 243
 244/**
 245 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for
 246 * handling the different APIs of reg_capa_flags.
 247 *
 248 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed
 249 *      for this regulatory domain (valid only in 5Ghz).
 250 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed
 251 *      for this regulatory domain (valid only in 5Ghz).
 252 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed
 253 *      for this regulatory domain (valid only in 5Ghz).
 254 * @disable_11ax: 11ax is forbidden for this regulatory domain.
 255 */
 256struct iwl_reg_capa {
 257        u16 allow_40mhz;
 258        u16 allow_80mhz;
 259        u16 allow_160mhz;
 260        u16 disable_11ax;
 261};
 262
 263static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
 264                                               int chan, u32 flags)
 265{
 266#define CHECK_AND_PRINT_I(x)    \
 267        ((flags & NVM_CHANNEL_##x) ? " " #x : "")
 268
 269        if (!(flags & NVM_CHANNEL_VALID)) {
 270                IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
 271                              chan, flags);
 272                return;
 273        }
 274
 275        /* Note: already can print up to 101 characters, 110 is the limit! */
 276        IWL_DEBUG_DEV(dev, level,
 277                      "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
 278                      chan, flags,
 279                      CHECK_AND_PRINT_I(VALID),
 280                      CHECK_AND_PRINT_I(IBSS),
 281                      CHECK_AND_PRINT_I(ACTIVE),
 282                      CHECK_AND_PRINT_I(RADAR),
 283                      CHECK_AND_PRINT_I(INDOOR_ONLY),
 284                      CHECK_AND_PRINT_I(GO_CONCURRENT),
 285                      CHECK_AND_PRINT_I(UNIFORM),
 286                      CHECK_AND_PRINT_I(20MHZ),
 287                      CHECK_AND_PRINT_I(40MHZ),
 288                      CHECK_AND_PRINT_I(80MHZ),
 289                      CHECK_AND_PRINT_I(160MHZ),
 290                      CHECK_AND_PRINT_I(DC_HIGH));
 291#undef CHECK_AND_PRINT_I
 292}
 293
 294static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
 295                                 u32 nvm_flags, const struct iwl_cfg *cfg)
 296{
 297        u32 flags = IEEE80211_CHAN_NO_HT40;
 298
 299        if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
 300                if (ch_num <= LAST_2GHZ_HT_PLUS)
 301                        flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
 302                if (ch_num >= FIRST_2GHZ_HT_MINUS)
 303                        flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
 304        } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
 305                if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
 306                        flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
 307                else
 308                        flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
 309        }
 310        if (!(nvm_flags & NVM_CHANNEL_80MHZ))
 311                flags |= IEEE80211_CHAN_NO_80MHZ;
 312        if (!(nvm_flags & NVM_CHANNEL_160MHZ))
 313                flags |= IEEE80211_CHAN_NO_160MHZ;
 314
 315        if (!(nvm_flags & NVM_CHANNEL_IBSS))
 316                flags |= IEEE80211_CHAN_NO_IR;
 317
 318        if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
 319                flags |= IEEE80211_CHAN_NO_IR;
 320
 321        if (nvm_flags & NVM_CHANNEL_RADAR)
 322                flags |= IEEE80211_CHAN_RADAR;
 323
 324        if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
 325                flags |= IEEE80211_CHAN_INDOOR_ONLY;
 326
 327        /* Set the GO concurrent flag only in case that NO_IR is set.
 328         * Otherwise it is meaningless
 329         */
 330        if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
 331            (flags & IEEE80211_CHAN_NO_IR))
 332                flags |= IEEE80211_CHAN_IR_CONCURRENT;
 333
 334        return flags;
 335}
 336
 337static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
 338{
 339        if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) {
 340                return NL80211_BAND_6GHZ;
 341        }
 342
 343        if (ch_idx >= NUM_2GHZ_CHANNELS)
 344                return NL80211_BAND_5GHZ;
 345        return NL80211_BAND_2GHZ;
 346}
 347
 348static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
 349                                struct iwl_nvm_data *data,
 350                                const void * const nvm_ch_flags,
 351                                u32 sbands_flags, bool v4)
 352{
 353        int ch_idx;
 354        int n_channels = 0;
 355        struct ieee80211_channel *channel;
 356        u32 ch_flags;
 357        int num_of_ch;
 358        const u16 *nvm_chan;
 359
 360        if (cfg->uhb_supported) {
 361                num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
 362                nvm_chan = iwl_uhb_nvm_channels;
 363        } else if (cfg->nvm_type == IWL_NVM_EXT) {
 364                num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
 365                nvm_chan = iwl_ext_nvm_channels;
 366        } else {
 367                num_of_ch = IWL_NVM_NUM_CHANNELS;
 368                nvm_chan = iwl_nvm_channels;
 369        }
 370
 371        for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
 372                enum nl80211_band band =
 373                        iwl_nl80211_band_from_channel_idx(ch_idx);
 374
 375                if (v4)
 376                        ch_flags =
 377                                __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx);
 378                else
 379                        ch_flags =
 380                                __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx);
 381
 382                if (band == NL80211_BAND_5GHZ &&
 383                    !data->sku_cap_band_52ghz_enable)
 384                        continue;
 385
 386                /* workaround to disable wide channels in 5GHz */
 387                if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
 388                    band == NL80211_BAND_5GHZ) {
 389                        ch_flags &= ~(NVM_CHANNEL_40MHZ |
 390                                     NVM_CHANNEL_80MHZ |
 391                                     NVM_CHANNEL_160MHZ);
 392                }
 393
 394                if (ch_flags & NVM_CHANNEL_160MHZ)
 395                        data->vht160_supported = true;
 396
 397                if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
 398                    !(ch_flags & NVM_CHANNEL_VALID)) {
 399                        /*
 400                         * Channels might become valid later if lar is
 401                         * supported, hence we still want to add them to
 402                         * the list of supported channels to cfg80211.
 403                         */
 404                        iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
 405                                                    nvm_chan[ch_idx], ch_flags);
 406                        continue;
 407                }
 408
 409                channel = &data->channels[n_channels];
 410                n_channels++;
 411
 412                channel->hw_value = nvm_chan[ch_idx];
 413                channel->band = band;
 414                channel->center_freq =
 415                        ieee80211_channel_to_frequency(
 416                                channel->hw_value, channel->band);
 417
 418                /* Initialize regulatory-based run-time data */
 419
 420                /*
 421                 * Default value - highest tx power value.  max_power
 422                 * is not used in mvm, and is used for backwards compatibility
 423                 */
 424                channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
 425
 426                /* don't put limitations in case we're using LAR */
 427                if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
 428                        channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
 429                                                               ch_idx, band,
 430                                                               ch_flags, cfg);
 431                else
 432                        channel->flags = 0;
 433
 434                /* TODO: Don't put limitations on UHB devices as we still don't
 435                 * have NVM for them
 436                 */
 437                if (cfg->uhb_supported)
 438                        channel->flags = 0;
 439                iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
 440                                            channel->hw_value, ch_flags);
 441                IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
 442                                 channel->hw_value, channel->max_power);
 443        }
 444
 445        return n_channels;
 446}
 447
 448static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
 449                                  struct iwl_nvm_data *data,
 450                                  struct ieee80211_sta_vht_cap *vht_cap,
 451                                  u8 tx_chains, u8 rx_chains)
 452{
 453        const struct iwl_cfg *cfg = trans->cfg;
 454        int num_rx_ants = num_of_ant(rx_chains);
 455        int num_tx_ants = num_of_ant(tx_chains);
 456
 457        vht_cap->vht_supported = true;
 458
 459        vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
 460                       IEEE80211_VHT_CAP_RXSTBC_1 |
 461                       IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
 462                       3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
 463                       IEEE80211_VHT_MAX_AMPDU_1024K <<
 464                       IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
 465
 466        if (data->vht160_supported)
 467                vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
 468                                IEEE80211_VHT_CAP_SHORT_GI_160;
 469
 470        if (cfg->vht_mu_mimo_supported)
 471                vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
 472
 473        if (cfg->ht_params->ldpc)
 474                vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
 475
 476        if (data->sku_cap_mimo_disabled) {
 477                num_rx_ants = 1;
 478                num_tx_ants = 1;
 479        }
 480
 481        if (num_tx_ants > 1)
 482                vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
 483        else
 484                vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
 485
 486        switch (iwlwifi_mod_params.amsdu_size) {
 487        case IWL_AMSDU_DEF:
 488                if (trans->trans_cfg->mq_rx_supported)
 489                        vht_cap->cap |=
 490                                IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
 491                else
 492                        vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
 493                break;
 494        case IWL_AMSDU_2K:
 495                if (trans->trans_cfg->mq_rx_supported)
 496                        vht_cap->cap |=
 497                                IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
 498                else
 499                        WARN(1, "RB size of 2K is not supported by this device\n");
 500                break;
 501        case IWL_AMSDU_4K:
 502                vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
 503                break;
 504        case IWL_AMSDU_8K:
 505                vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
 506                break;
 507        case IWL_AMSDU_12K:
 508                vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
 509                break;
 510        default:
 511                break;
 512        }
 513
 514        vht_cap->vht_mcs.rx_mcs_map =
 515                cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
 516                            IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
 517                            IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
 518                            IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
 519                            IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
 520                            IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
 521                            IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
 522                            IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
 523
 524        if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
 525                vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
 526                /* this works because NOT_SUPPORTED == 3 */
 527                vht_cap->vht_mcs.rx_mcs_map |=
 528                        cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
 529        }
 530
 531        vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
 532
 533        vht_cap->vht_mcs.tx_highest |=
 534                cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
 535}
 536
 537static const struct ieee80211_sband_iftype_data iwl_he_capa[] = {
 538        {
 539                .types_mask = BIT(NL80211_IFTYPE_STATION),
 540                .he_cap = {
 541                        .has_he = true,
 542                        .he_cap_elem = {
 543                                .mac_cap_info[0] =
 544                                        IEEE80211_HE_MAC_CAP0_HTC_HE |
 545                                        IEEE80211_HE_MAC_CAP0_TWT_REQ,
 546                                .mac_cap_info[1] =
 547                                        IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
 548                                        IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
 549                                .mac_cap_info[2] =
 550                                        IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP,
 551                                .mac_cap_info[3] =
 552                                        IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
 553                                        IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2,
 554                                .mac_cap_info[4] =
 555                                        IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU |
 556                                        IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
 557                                .mac_cap_info[5] =
 558                                        IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
 559                                        IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
 560                                        IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
 561                                        IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
 562                                        IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
 563                                .phy_cap_info[0] =
 564                                        IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
 565                                        IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
 566                                        IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
 567                                .phy_cap_info[1] =
 568                                        IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
 569                                        IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
 570                                        IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
 571                                .phy_cap_info[2] =
 572                                        IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
 573                                .phy_cap_info[3] =
 574                                        IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
 575                                        IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
 576                                        IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
 577                                        IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
 578                                .phy_cap_info[4] =
 579                                        IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
 580                                        IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
 581                                        IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
 582                                .phy_cap_info[5] =
 583                                        IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
 584                                        IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
 585                                .phy_cap_info[6] =
 586                                        IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
 587                                        IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB |
 588                                        IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
 589                                .phy_cap_info[7] =
 590                                        IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
 591                                        IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
 592                                        IEEE80211_HE_PHY_CAP7_MAX_NC_1,
 593                                .phy_cap_info[8] =
 594                                        IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
 595                                        IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
 596                                        IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
 597                                        IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
 598                                        IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
 599                                .phy_cap_info[9] =
 600                                        IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
 601                                        IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
 602                                        IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
 603                                        IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
 604                        },
 605                        /*
 606                         * Set default Tx/Rx HE MCS NSS Support field.
 607                         * Indicate support for up to 2 spatial streams and all
 608                         * MCS, without any special cases
 609                         */
 610                        .he_mcs_nss_supp = {
 611                                .rx_mcs_80 = cpu_to_le16(0xfffa),
 612                                .tx_mcs_80 = cpu_to_le16(0xfffa),
 613                                .rx_mcs_160 = cpu_to_le16(0xfffa),
 614                                .tx_mcs_160 = cpu_to_le16(0xfffa),
 615                                .rx_mcs_80p80 = cpu_to_le16(0xffff),
 616                                .tx_mcs_80p80 = cpu_to_le16(0xffff),
 617                        },
 618                        /*
 619                         * Set default PPE thresholds, with PPET16 set to 0,
 620                         * PPET8 set to 7
 621                         */
 622                        .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
 623                },
 624        },
 625        {
 626                .types_mask = BIT(NL80211_IFTYPE_AP),
 627                .he_cap = {
 628                        .has_he = true,
 629                        .he_cap_elem = {
 630                                .mac_cap_info[0] =
 631                                        IEEE80211_HE_MAC_CAP0_HTC_HE,
 632                                .mac_cap_info[1] =
 633                                        IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
 634                                        IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
 635                                .mac_cap_info[2] =
 636                                        IEEE80211_HE_MAC_CAP2_BSR,
 637                                .mac_cap_info[3] =
 638                                        IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
 639                                        IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2,
 640                                .mac_cap_info[4] =
 641                                        IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU,
 642                                .mac_cap_info[5] =
 643                                        IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU,
 644                                .phy_cap_info[0] =
 645                                        IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
 646                                        IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
 647                                        IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
 648                                .phy_cap_info[1] =
 649                                        IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
 650                                .phy_cap_info[2] =
 651                                        IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
 652                                .phy_cap_info[3] =
 653                                        IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
 654                                        IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
 655                                        IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
 656                                        IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
 657                                .phy_cap_info[4] =
 658                                        IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
 659                                        IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
 660                                        IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
 661                                .phy_cap_info[5] =
 662                                        IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
 663                                        IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
 664                                .phy_cap_info[6] =
 665                                        IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
 666                                .phy_cap_info[7] =
 667                                        IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
 668                                        IEEE80211_HE_PHY_CAP7_MAX_NC_1,
 669                                .phy_cap_info[8] =
 670                                        IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
 671                                        IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
 672                                        IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
 673                                        IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
 674                                        IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
 675                                .phy_cap_info[9] =
 676                                        IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
 677                                        IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
 678                                        IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
 679                        },
 680                        /*
 681                         * Set default Tx/Rx HE MCS NSS Support field.
 682                         * Indicate support for up to 2 spatial streams and all
 683                         * MCS, without any special cases
 684                         */
 685                        .he_mcs_nss_supp = {
 686                                .rx_mcs_80 = cpu_to_le16(0xfffa),
 687                                .tx_mcs_80 = cpu_to_le16(0xfffa),
 688                                .rx_mcs_160 = cpu_to_le16(0xfffa),
 689                                .tx_mcs_160 = cpu_to_le16(0xfffa),
 690                                .rx_mcs_80p80 = cpu_to_le16(0xffff),
 691                                .tx_mcs_80p80 = cpu_to_le16(0xffff),
 692                        },
 693                        /*
 694                         * Set default PPE thresholds, with PPET16 set to 0,
 695                         * PPET8 set to 7
 696                         */
 697                        .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
 698                },
 699        },
 700};
 701
 702static void iwl_init_he_6ghz_capa(struct iwl_trans *trans,
 703                                  struct iwl_nvm_data *data,
 704                                  struct ieee80211_supported_band *sband,
 705                                  u8 tx_chains, u8 rx_chains)
 706{
 707        struct ieee80211_sta_ht_cap ht_cap;
 708        struct ieee80211_sta_vht_cap vht_cap = {};
 709        struct ieee80211_sband_iftype_data *iftype_data;
 710        u16 he_6ghz_capa = 0;
 711        u32 exp;
 712        int i;
 713
 714        if (sband->band != NL80211_BAND_6GHZ)
 715                return;
 716
 717        /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */
 718        iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ,
 719                             tx_chains, rx_chains);
 720        WARN_ON(!ht_cap.ht_supported);
 721        iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains);
 722        WARN_ON(!vht_cap.vht_supported);
 723
 724        he_6ghz_capa |=
 725                u16_encode_bits(ht_cap.ampdu_density,
 726                                IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START);
 727        exp = u32_get_bits(vht_cap.cap,
 728                           IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
 729        he_6ghz_capa |=
 730                u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP);
 731        exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK);
 732        he_6ghz_capa |=
 733                u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
 734        /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */
 735        if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN)
 736                he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS;
 737        if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN)
 738                he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
 739
 740        IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa);
 741
 742        /* we know it's writable - we set it before ourselves */
 743        iftype_data = (void *)sband->iftype_data;
 744        for (i = 0; i < sband->n_iftype_data; i++)
 745                iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa);
 746}
 747
 748static void iwl_init_he_hw_capab(struct iwl_trans *trans,
 749                                 struct iwl_nvm_data *data,
 750                                 struct ieee80211_supported_band *sband,
 751                                 u8 tx_chains, u8 rx_chains)
 752{
 753        struct ieee80211_sband_iftype_data *iftype_data;
 754
 755        /* should only initialize once */
 756        if (WARN_ON(sband->iftype_data))
 757                return;
 758
 759        BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_capa));
 760        BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_capa));
 761
 762        switch (sband->band) {
 763        case NL80211_BAND_2GHZ:
 764                iftype_data = data->iftd.low;
 765                break;
 766        case NL80211_BAND_5GHZ:
 767        case NL80211_BAND_6GHZ:
 768                iftype_data = data->iftd.high;
 769                break;
 770        default:
 771                WARN_ON(1);
 772                return;
 773        }
 774
 775        memcpy(iftype_data, iwl_he_capa, sizeof(iwl_he_capa));
 776
 777        sband->iftype_data = iftype_data;
 778        sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa);
 779
 780        /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */
 781        if ((tx_chains & rx_chains) != ANT_AB) {
 782                int i;
 783
 784                for (i = 0; i < sband->n_iftype_data; i++) {
 785                        iftype_data[i].he_cap.he_cap_elem.phy_cap_info[1] &=
 786                                ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
 787                        iftype_data[i].he_cap.he_cap_elem.phy_cap_info[2] &=
 788                                ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
 789                        iftype_data[i].he_cap.he_cap_elem.phy_cap_info[7] &=
 790                                ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
 791                }
 792        }
 793        iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains);
 794}
 795
 796static void iwl_init_sbands(struct iwl_trans *trans,
 797                            struct iwl_nvm_data *data,
 798                            const void *nvm_ch_flags, u8 tx_chains,
 799                            u8 rx_chains, u32 sbands_flags, bool v4)
 800{
 801        struct device *dev = trans->dev;
 802        const struct iwl_cfg *cfg = trans->cfg;
 803        int n_channels;
 804        int n_used = 0;
 805        struct ieee80211_supported_band *sband;
 806
 807        n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
 808                                          sbands_flags, v4);
 809        sband = &data->bands[NL80211_BAND_2GHZ];
 810        sband->band = NL80211_BAND_2GHZ;
 811        sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
 812        sband->n_bitrates = N_RATES_24;
 813        n_used += iwl_init_sband_channels(data, sband, n_channels,
 814                                          NL80211_BAND_2GHZ);
 815        iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
 816                             tx_chains, rx_chains);
 817
 818        if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
 819                iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
 820
 821        sband = &data->bands[NL80211_BAND_5GHZ];
 822        sband->band = NL80211_BAND_5GHZ;
 823        sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
 824        sband->n_bitrates = N_RATES_52;
 825        n_used += iwl_init_sband_channels(data, sband, n_channels,
 826                                          NL80211_BAND_5GHZ);
 827        iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
 828                             tx_chains, rx_chains);
 829        if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
 830                iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
 831                                      tx_chains, rx_chains);
 832
 833        if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
 834                iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
 835
 836        /* 6GHz band. */
 837        sband = &data->bands[NL80211_BAND_6GHZ];
 838        sband->band = NL80211_BAND_6GHZ;
 839        /* use the same rates as 5GHz band */
 840        sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
 841        sband->n_bitrates = N_RATES_52;
 842        n_used += iwl_init_sband_channels(data, sband, n_channels,
 843                                          NL80211_BAND_6GHZ);
 844
 845        if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
 846                iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
 847        else
 848                sband->n_channels = 0;
 849        if (n_channels != n_used)
 850                IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
 851                            n_used, n_channels);
 852}
 853
 854static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
 855                       const __le16 *phy_sku)
 856{
 857        if (cfg->nvm_type != IWL_NVM_EXT)
 858                return le16_to_cpup(nvm_sw + SKU);
 859
 860        return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
 861}
 862
 863static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
 864{
 865        if (cfg->nvm_type != IWL_NVM_EXT)
 866                return le16_to_cpup(nvm_sw + NVM_VERSION);
 867        else
 868                return le32_to_cpup((__le32 *)(nvm_sw +
 869                                               NVM_VERSION_EXT_NVM));
 870}
 871
 872static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
 873                             const __le16 *phy_sku)
 874{
 875        if (cfg->nvm_type != IWL_NVM_EXT)
 876                return le16_to_cpup(nvm_sw + RADIO_CFG);
 877
 878        return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
 879
 880}
 881
 882static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
 883{
 884        int n_hw_addr;
 885
 886        if (cfg->nvm_type != IWL_NVM_EXT)
 887                return le16_to_cpup(nvm_sw + N_HW_ADDRS);
 888
 889        n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
 890
 891        return n_hw_addr & N_HW_ADDR_MASK;
 892}
 893
 894static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
 895                              struct iwl_nvm_data *data,
 896                              u32 radio_cfg)
 897{
 898        if (cfg->nvm_type != IWL_NVM_EXT) {
 899                data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
 900                data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
 901                data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
 902                data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
 903                return;
 904        }
 905
 906        /* set the radio configuration for family 8000 */
 907        data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
 908        data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
 909        data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
 910        data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
 911        data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
 912        data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
 913}
 914
 915static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
 916{
 917        const u8 *hw_addr;
 918
 919        hw_addr = (const u8 *)&mac_addr0;
 920        dest[0] = hw_addr[3];
 921        dest[1] = hw_addr[2];
 922        dest[2] = hw_addr[1];
 923        dest[3] = hw_addr[0];
 924
 925        hw_addr = (const u8 *)&mac_addr1;
 926        dest[4] = hw_addr[1];
 927        dest[5] = hw_addr[0];
 928}
 929
 930static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
 931                                        struct iwl_nvm_data *data)
 932{
 933        __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
 934        __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
 935
 936        iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
 937        /*
 938         * If the OEM fused a valid address, use it instead of the one in the
 939         * OTP
 940         */
 941        if (is_valid_ether_addr(data->hw_addr))
 942                return;
 943
 944        mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
 945        mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
 946
 947        iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
 948}
 949
 950static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
 951                                           const struct iwl_cfg *cfg,
 952                                           struct iwl_nvm_data *data,
 953                                           const __le16 *mac_override,
 954                                           const __be16 *nvm_hw)
 955{
 956        const u8 *hw_addr;
 957
 958        if (mac_override) {
 959                static const u8 reserved_mac[] = {
 960                        0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
 961                };
 962
 963                hw_addr = (const u8 *)(mac_override +
 964                                 MAC_ADDRESS_OVERRIDE_EXT_NVM);
 965
 966                /*
 967                 * Store the MAC address from MAO section.
 968                 * No byte swapping is required in MAO section
 969                 */
 970                memcpy(data->hw_addr, hw_addr, ETH_ALEN);
 971
 972                /*
 973                 * Force the use of the OTP MAC address in case of reserved MAC
 974                 * address in the NVM, or if address is given but invalid.
 975                 */
 976                if (is_valid_ether_addr(data->hw_addr) &&
 977                    memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
 978                        return;
 979
 980                IWL_ERR(trans,
 981                        "mac address from nvm override section is not valid\n");
 982        }
 983
 984        if (nvm_hw) {
 985                /* read the mac address from WFMP registers */
 986                __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
 987                                                WFMP_MAC_ADDR_0));
 988                __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
 989                                                WFMP_MAC_ADDR_1));
 990
 991                iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
 992
 993                return;
 994        }
 995
 996        IWL_ERR(trans, "mac address is not found\n");
 997}
 998
 999static int iwl_set_hw_address(struct iwl_trans *trans,
1000                              const struct iwl_cfg *cfg,
1001                              struct iwl_nvm_data *data, const __be16 *nvm_hw,
1002                              const __le16 *mac_override)
1003{
1004        if (cfg->mac_addr_from_csr) {
1005                iwl_set_hw_address_from_csr(trans, data);
1006        } else if (cfg->nvm_type != IWL_NVM_EXT) {
1007                const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
1008
1009                /* The byte order is little endian 16 bit, meaning 214365 */
1010                data->hw_addr[0] = hw_addr[1];
1011                data->hw_addr[1] = hw_addr[0];
1012                data->hw_addr[2] = hw_addr[3];
1013                data->hw_addr[3] = hw_addr[2];
1014                data->hw_addr[4] = hw_addr[5];
1015                data->hw_addr[5] = hw_addr[4];
1016        } else {
1017                iwl_set_hw_address_family_8000(trans, cfg, data,
1018                                               mac_override, nvm_hw);
1019        }
1020
1021        if (!is_valid_ether_addr(data->hw_addr)) {
1022                IWL_ERR(trans, "no valid mac address was found\n");
1023                return -EINVAL;
1024        }
1025
1026        IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
1027
1028        return 0;
1029}
1030
1031static bool
1032iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1033                        const __be16 *nvm_hw)
1034{
1035        /*
1036         * Workaround a bug in Indonesia SKUs where the regulatory in
1037         * some 7000-family OTPs erroneously allow wide channels in
1038         * 5GHz.  To check for Indonesia, we take the SKU value from
1039         * bits 1-4 in the subsystem ID and check if it is either 5 or
1040         * 9.  In those cases, we need to force-disable wide channels
1041         * in 5GHz otherwise the FW will throw a sysassert when we try
1042         * to use them.
1043         */
1044        if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1045                /*
1046                 * Unlike the other sections in the NVM, the hw
1047                 * section uses big-endian.
1048                 */
1049                u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
1050                u8 sku = (subsystem_id & 0x1e) >> 1;
1051
1052                if (sku == 5 || sku == 9) {
1053                        IWL_DEBUG_EEPROM(trans->dev,
1054                                         "disabling wide channels in 5GHz (0x%0x %d)\n",
1055                                         subsystem_id, sku);
1056                        return true;
1057                }
1058        }
1059
1060        return false;
1061}
1062
1063struct iwl_nvm_data *
1064iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1065                   const struct iwl_fw *fw,
1066                   const __be16 *nvm_hw, const __le16 *nvm_sw,
1067                   const __le16 *nvm_calib, const __le16 *regulatory,
1068                   const __le16 *mac_override, const __le16 *phy_sku,
1069                   u8 tx_chains, u8 rx_chains)
1070{
1071        struct iwl_nvm_data *data;
1072        bool lar_enabled;
1073        u32 sku, radio_cfg;
1074        u32 sbands_flags = 0;
1075        u16 lar_config;
1076        const __le16 *ch_section;
1077
1078        if (cfg->uhb_supported)
1079                data = kzalloc(struct_size(data, channels,
1080                                           IWL_NVM_NUM_CHANNELS_UHB),
1081                                           GFP_KERNEL);
1082        else if (cfg->nvm_type != IWL_NVM_EXT)
1083                data = kzalloc(struct_size(data, channels,
1084                                           IWL_NVM_NUM_CHANNELS),
1085                                           GFP_KERNEL);
1086        else
1087                data = kzalloc(struct_size(data, channels,
1088                                           IWL_NVM_NUM_CHANNELS_EXT),
1089                                           GFP_KERNEL);
1090        if (!data)
1091                return NULL;
1092
1093        data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
1094
1095        radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
1096        iwl_set_radio_cfg(cfg, data, radio_cfg);
1097        if (data->valid_tx_ant)
1098                tx_chains &= data->valid_tx_ant;
1099        if (data->valid_rx_ant)
1100                rx_chains &= data->valid_rx_ant;
1101
1102        sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1103        data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1104        data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1105        data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1106        if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1107                data->sku_cap_11n_enable = false;
1108        data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1109                                    (sku & NVM_SKU_CAP_11AC_ENABLE);
1110        data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1111
1112        data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1113
1114        if (cfg->nvm_type != IWL_NVM_EXT) {
1115                /* Checking for required sections */
1116                if (!nvm_calib) {
1117                        IWL_ERR(trans,
1118                                "Can't parse empty Calib NVM sections\n");
1119                        kfree(data);
1120                        return NULL;
1121                }
1122
1123                ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1124                             &regulatory[NVM_CHANNELS_SDP] :
1125                             &nvm_sw[NVM_CHANNELS];
1126
1127                /* in family 8000 Xtal calibration values moved to OTP */
1128                data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
1129                data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
1130                lar_enabled = true;
1131        } else {
1132                u16 lar_offset = data->nvm_version < 0xE39 ?
1133                                 NVM_LAR_OFFSET_OLD :
1134                                 NVM_LAR_OFFSET;
1135
1136                lar_config = le16_to_cpup(regulatory + lar_offset);
1137                data->lar_enabled = !!(lar_config &
1138                                       NVM_LAR_ENABLED);
1139                lar_enabled = data->lar_enabled;
1140                ch_section = &regulatory[NVM_CHANNELS_EXTENDED];
1141        }
1142
1143        /* If no valid mac address was found - bail out */
1144        if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1145                kfree(data);
1146                return NULL;
1147        }
1148
1149        if (lar_enabled &&
1150            fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1151                sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1152
1153        if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1154                sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1155
1156        iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1157                        sbands_flags, false);
1158        data->calib_version = 255;
1159
1160        return data;
1161}
1162IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1163
1164static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1165                                       int ch_idx, u16 nvm_flags,
1166                                       struct iwl_reg_capa reg_capa,
1167                                       const struct iwl_cfg *cfg)
1168{
1169        u32 flags = NL80211_RRF_NO_HT40;
1170
1171        if (ch_idx < NUM_2GHZ_CHANNELS &&
1172            (nvm_flags & NVM_CHANNEL_40MHZ)) {
1173                if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1174                        flags &= ~NL80211_RRF_NO_HT40PLUS;
1175                if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1176                        flags &= ~NL80211_RRF_NO_HT40MINUS;
1177        } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1178                if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1179                        flags &= ~NL80211_RRF_NO_HT40PLUS;
1180                else
1181                        flags &= ~NL80211_RRF_NO_HT40MINUS;
1182        }
1183
1184        if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1185                flags |= NL80211_RRF_NO_80MHZ;
1186        if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1187                flags |= NL80211_RRF_NO_160MHZ;
1188
1189        if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1190                flags |= NL80211_RRF_NO_IR;
1191
1192        if (nvm_flags & NVM_CHANNEL_RADAR)
1193                flags |= NL80211_RRF_DFS;
1194
1195        if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1196                flags |= NL80211_RRF_NO_OUTDOOR;
1197
1198        /* Set the GO concurrent flag only in case that NO_IR is set.
1199         * Otherwise it is meaningless
1200         */
1201        if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
1202            (flags & NL80211_RRF_NO_IR))
1203                flags |= NL80211_RRF_GO_CONCURRENT;
1204
1205        /*
1206         * reg_capa is per regulatory domain so apply it for every channel
1207         */
1208        if (ch_idx >= NUM_2GHZ_CHANNELS) {
1209                if (!reg_capa.allow_40mhz)
1210                        flags |= NL80211_RRF_NO_HT40;
1211
1212                if (!reg_capa.allow_80mhz)
1213                        flags |= NL80211_RRF_NO_80MHZ;
1214
1215                if (!reg_capa.allow_160mhz)
1216                        flags |= NL80211_RRF_NO_160MHZ;
1217        }
1218        if (reg_capa.disable_11ax)
1219                flags |= NL80211_RRF_NO_HE;
1220
1221        return flags;
1222}
1223
1224static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver)
1225{
1226        struct iwl_reg_capa reg_capa;
1227
1228        if (resp_ver >= REG_CAPA_V2_RESP_VER) {
1229                reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED;
1230                reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED;
1231                reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED;
1232                reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED;
1233        } else {
1234                reg_capa.allow_40mhz = !(flags & REG_CAPA_40MHZ_FORBIDDEN);
1235                reg_capa.allow_80mhz = flags & REG_CAPA_80MHZ_ALLOWED;
1236                reg_capa.allow_160mhz = flags & REG_CAPA_160MHZ_ALLOWED;
1237                reg_capa.disable_11ax = flags & REG_CAPA_11AX_DISABLED;
1238        }
1239        return reg_capa;
1240}
1241
1242struct ieee80211_regdomain *
1243iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1244                       int num_of_ch, __le32 *channels, u16 fw_mcc,
1245                       u16 geo_info, u16 cap, u8 resp_ver)
1246{
1247        int ch_idx;
1248        u16 ch_flags;
1249        u32 reg_rule_flags, prev_reg_rule_flags = 0;
1250        const u16 *nvm_chan;
1251        struct ieee80211_regdomain *regd, *copy_rd;
1252        struct ieee80211_reg_rule *rule;
1253        enum nl80211_band band;
1254        int center_freq, prev_center_freq = 0;
1255        int valid_rules = 0;
1256        bool new_rule;
1257        int max_num_ch;
1258        struct iwl_reg_capa reg_capa;
1259
1260        if (cfg->uhb_supported) {
1261                max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1262                nvm_chan = iwl_uhb_nvm_channels;
1263        } else if (cfg->nvm_type == IWL_NVM_EXT) {
1264                max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1265                nvm_chan = iwl_ext_nvm_channels;
1266        } else {
1267                max_num_ch = IWL_NVM_NUM_CHANNELS;
1268                nvm_chan = iwl_nvm_channels;
1269        }
1270
1271        if (WARN_ON(num_of_ch > max_num_ch))
1272                num_of_ch = max_num_ch;
1273
1274        if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1275                return ERR_PTR(-EINVAL);
1276
1277        IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1278                      num_of_ch);
1279
1280        /* build a regdomain rule for every valid channel */
1281        regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1282        if (!regd)
1283                return ERR_PTR(-ENOMEM);
1284
1285        /* set alpha2 from FW. */
1286        regd->alpha2[0] = fw_mcc >> 8;
1287        regd->alpha2[1] = fw_mcc & 0xff;
1288
1289        /* parse regulatory capability flags */
1290        reg_capa = iwl_get_reg_capa(cap, resp_ver);
1291
1292        for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1293                ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1294                band = iwl_nl80211_band_from_channel_idx(ch_idx);
1295                center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1296                                                             band);
1297                new_rule = false;
1298
1299                if (!(ch_flags & NVM_CHANNEL_VALID)) {
1300                        iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1301                                                    nvm_chan[ch_idx], ch_flags);
1302                        continue;
1303                }
1304
1305                reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1306                                                             ch_flags, reg_capa,
1307                                                             cfg);
1308
1309                /* we can't continue the same rule */
1310                if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1311                    center_freq - prev_center_freq > 20) {
1312                        valid_rules++;
1313                        new_rule = true;
1314                }
1315
1316                rule = &regd->reg_rules[valid_rules - 1];
1317
1318                if (new_rule)
1319                        rule->freq_range.start_freq_khz =
1320                                                MHZ_TO_KHZ(center_freq - 10);
1321
1322                rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1323
1324                /* this doesn't matter - not used by FW */
1325                rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1326                rule->power_rule.max_eirp =
1327                        DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1328
1329                rule->flags = reg_rule_flags;
1330
1331                /* rely on auto-calculation to merge BW of contiguous chans */
1332                rule->flags |= NL80211_RRF_AUTO_BW;
1333                rule->freq_range.max_bandwidth_khz = 0;
1334
1335                prev_center_freq = center_freq;
1336                prev_reg_rule_flags = reg_rule_flags;
1337
1338                iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1339                                            nvm_chan[ch_idx], ch_flags);
1340
1341                if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1342                    band == NL80211_BAND_2GHZ)
1343                        continue;
1344
1345                reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1346        }
1347
1348        regd->n_reg_rules = valid_rules;
1349
1350        /*
1351         * Narrow down regdom for unused regulatory rules to prevent hole
1352         * between reg rules to wmm rules.
1353         */
1354        copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1355                          GFP_KERNEL);
1356        if (!copy_rd)
1357                copy_rd = ERR_PTR(-ENOMEM);
1358
1359        kfree(regd);
1360        return copy_rd;
1361}
1362IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1363
1364#define IWL_MAX_NVM_SECTION_SIZE        0x1b58
1365#define IWL_MAX_EXT_NVM_SECTION_SIZE    0x1ffc
1366#define MAX_NVM_FILE_LEN        16384
1367
1368void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1369                    unsigned int len)
1370{
1371#define IWL_4165_DEVICE_ID      0x5501
1372#define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1373
1374        if (section == NVM_SECTION_TYPE_PHY_SKU &&
1375            hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1376            (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1377                /* OTP 0x52 bug work around: it's a 1x1 device */
1378                data[3] = ANT_B | (ANT_B << 4);
1379}
1380IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1381
1382/*
1383 * Reads external NVM from a file into mvm->nvm_sections
1384 *
1385 * HOW TO CREATE THE NVM FILE FORMAT:
1386 * ------------------------------
1387 * 1. create hex file, format:
1388 *      3800 -> header
1389 *      0000 -> header
1390 *      5a40 -> data
1391 *
1392 *   rev - 6 bit (word1)
1393 *   len - 10 bit (word1)
1394 *   id - 4 bit (word2)
1395 *   rsv - 12 bit (word2)
1396 *
1397 * 2. flip 8bits with 8 bits per line to get the right NVM file format
1398 *
1399 * 3. create binary file from the hex file
1400 *
1401 * 4. save as "iNVM_xxx.bin" under /lib/firmware
1402 */
1403int iwl_read_external_nvm(struct iwl_trans *trans,
1404                          const char *nvm_file_name,
1405                          struct iwl_nvm_section *nvm_sections)
1406{
1407        int ret, section_size;
1408        u16 section_id;
1409        const struct firmware *fw_entry;
1410        const struct {
1411                __le16 word1;
1412                __le16 word2;
1413                u8 data[];
1414        } *file_sec;
1415        const u8 *eof;
1416        u8 *temp;
1417        int max_section_size;
1418        const __le32 *dword_buff;
1419
1420#define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1421#define NVM_WORD2_ID(x) (x >> 12)
1422#define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1423#define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1424#define NVM_HEADER_0    (0x2A504C54)
1425#define NVM_HEADER_1    (0x4E564D2A)
1426#define NVM_HEADER_SIZE (4 * sizeof(u32))
1427
1428        IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1429
1430        /* Maximal size depends on NVM version */
1431        if (trans->cfg->nvm_type != IWL_NVM_EXT)
1432                max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1433        else
1434                max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1435
1436        /*
1437         * Obtain NVM image via request_firmware. Since we already used
1438         * request_firmware_nowait() for the firmware binary load and only
1439         * get here after that we assume the NVM request can be satisfied
1440         * synchronously.
1441         */
1442        ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1443        if (ret) {
1444                IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1445                        nvm_file_name, ret);
1446                return ret;
1447        }
1448
1449        IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1450                 nvm_file_name, fw_entry->size);
1451
1452        if (fw_entry->size > MAX_NVM_FILE_LEN) {
1453                IWL_ERR(trans, "NVM file too large\n");
1454                ret = -EINVAL;
1455                goto out;
1456        }
1457
1458        eof = fw_entry->data + fw_entry->size;
1459        dword_buff = (__le32 *)fw_entry->data;
1460
1461        /* some NVM file will contain a header.
1462         * The header is identified by 2 dwords header as follow:
1463         * dword[0] = 0x2A504C54
1464         * dword[1] = 0x4E564D2A
1465         *
1466         * This header must be skipped when providing the NVM data to the FW.
1467         */
1468        if (fw_entry->size > NVM_HEADER_SIZE &&
1469            dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1470            dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1471                file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
1472                IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1473                IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1474                         le32_to_cpu(dword_buff[3]));
1475
1476                /* nvm file validation, dword_buff[2] holds the file version */
1477                if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1478                    CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
1479                    le32_to_cpu(dword_buff[2]) < 0xE4A) {
1480                        ret = -EFAULT;
1481                        goto out;
1482                }
1483        } else {
1484                file_sec = (void *)fw_entry->data;
1485        }
1486
1487        while (true) {
1488                if (file_sec->data > eof) {
1489                        IWL_ERR(trans,
1490                                "ERROR - NVM file too short for section header\n");
1491                        ret = -EINVAL;
1492                        break;
1493                }
1494
1495                /* check for EOF marker */
1496                if (!file_sec->word1 && !file_sec->word2) {
1497                        ret = 0;
1498                        break;
1499                }
1500
1501                if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1502                        section_size =
1503                                2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1504                        section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1505                } else {
1506                        section_size = 2 * EXT_NVM_WORD2_LEN(
1507                                                le16_to_cpu(file_sec->word2));
1508                        section_id = EXT_NVM_WORD1_ID(
1509                                                le16_to_cpu(file_sec->word1));
1510                }
1511
1512                if (section_size > max_section_size) {
1513                        IWL_ERR(trans, "ERROR - section too large (%d)\n",
1514                                section_size);
1515                        ret = -EINVAL;
1516                        break;
1517                }
1518
1519                if (!section_size) {
1520                        IWL_ERR(trans, "ERROR - section empty\n");
1521                        ret = -EINVAL;
1522                        break;
1523                }
1524
1525                if (file_sec->data + section_size > eof) {
1526                        IWL_ERR(trans,
1527                                "ERROR - NVM file too short for section (%d bytes)\n",
1528                                section_size);
1529                        ret = -EINVAL;
1530                        break;
1531                }
1532
1533                if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1534                         "Invalid NVM section ID %d\n", section_id)) {
1535                        ret = -EINVAL;
1536                        break;
1537                }
1538
1539                temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1540                if (!temp) {
1541                        ret = -ENOMEM;
1542                        break;
1543                }
1544
1545                iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1546
1547                kfree(nvm_sections[section_id].data);
1548                nvm_sections[section_id].data = temp;
1549                nvm_sections[section_id].length = section_size;
1550
1551                /* advance to the next section */
1552                file_sec = (void *)(file_sec->data + section_size);
1553        }
1554out:
1555        release_firmware(fw_entry);
1556        return ret;
1557}
1558IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
1559
1560struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
1561                                 const struct iwl_fw *fw)
1562{
1563        struct iwl_nvm_get_info cmd = {};
1564        struct iwl_nvm_data *nvm;
1565        struct iwl_host_cmd hcmd = {
1566                .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
1567                .data = { &cmd, },
1568                .len = { sizeof(cmd) },
1569                .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
1570        };
1571        int  ret;
1572        bool empty_otp;
1573        u32 mac_flags;
1574        u32 sbands_flags = 0;
1575        /*
1576         * All the values in iwl_nvm_get_info_rsp v4 are the same as
1577         * in v3, except for the channel profile part of the
1578         * regulatory.  So we can just access the new struct, with the
1579         * exception of the latter.
1580         */
1581        struct iwl_nvm_get_info_rsp *rsp;
1582        struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
1583        bool v4 = fw_has_api(&fw->ucode_capa,
1584                             IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
1585        size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
1586        void *channel_profile;
1587
1588        ret = iwl_trans_send_cmd(trans, &hcmd);
1589        if (ret)
1590                return ERR_PTR(ret);
1591
1592        if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
1593                 "Invalid payload len in NVM response from FW %d",
1594                 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
1595                ret = -EINVAL;
1596                goto out;
1597        }
1598
1599        rsp = (void *)hcmd.resp_pkt->data;
1600        empty_otp = !!(le32_to_cpu(rsp->general.flags) &
1601                       NVM_GENERAL_FLAGS_EMPTY_OTP);
1602        if (empty_otp)
1603                IWL_INFO(trans, "OTP is empty\n");
1604
1605        nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
1606        if (!nvm) {
1607                ret = -ENOMEM;
1608                goto out;
1609        }
1610
1611        iwl_set_hw_address_from_csr(trans, nvm);
1612        /* TODO: if platform NVM has MAC address - override it here */
1613
1614        if (!is_valid_ether_addr(nvm->hw_addr)) {
1615                IWL_ERR(trans, "no valid mac address was found\n");
1616                ret = -EINVAL;
1617                goto err_free;
1618        }
1619
1620        IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
1621
1622        /* Initialize general data */
1623        nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
1624        nvm->n_hw_addrs = rsp->general.n_hw_addrs;
1625        if (nvm->n_hw_addrs == 0)
1626                IWL_WARN(trans,
1627                         "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
1628                         empty_otp);
1629
1630        /* Initialize MAC sku data */
1631        mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
1632        nvm->sku_cap_11ac_enable =
1633                !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
1634        nvm->sku_cap_11n_enable =
1635                !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
1636        nvm->sku_cap_11ax_enable =
1637                !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
1638        nvm->sku_cap_band_24ghz_enable =
1639                !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
1640        nvm->sku_cap_band_52ghz_enable =
1641                !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
1642        nvm->sku_cap_mimo_disabled =
1643                !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
1644
1645        /* Initialize PHY sku data */
1646        nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
1647        nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
1648
1649        if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
1650            fw_has_capa(&fw->ucode_capa,
1651                        IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
1652                nvm->lar_enabled = true;
1653                sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1654        }
1655
1656        rsp_v3 = (void *)rsp;
1657        channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
1658                          (void *)rsp_v3->regulatory.channel_profile;
1659
1660        iwl_init_sbands(trans, nvm,
1661                        channel_profile,
1662                        nvm->valid_tx_ant & fw->valid_tx_ant,
1663                        nvm->valid_rx_ant & fw->valid_rx_ant,
1664                        sbands_flags, v4);
1665
1666        iwl_free_resp(&hcmd);
1667        return nvm;
1668
1669err_free:
1670        kfree(nvm);
1671out:
1672        iwl_free_resp(&hcmd);
1673        return ERR_PTR(ret);
1674}
1675IWL_EXPORT_SYMBOL(iwl_get_nvm);
1676