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5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/msi.h>
11#include <linux/of_device.h>
12#include <linux/of_pci.h>
13#include <linux/pci_hotplug.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/cpumask.h>
17#include <linux/aer.h>
18#include <linux/acpi.h>
19#include <linux/hypervisor.h>
20#include <linux/irqdomain.h>
21#include <linux/pm_runtime.h>
22#include "pci.h"
23
24#define CARDBUS_LATENCY_TIMER 176
25#define CARDBUS_RESERVE_BUSNR 3
26
27static struct resource busn_resource = {
28 .name = "PCI busn",
29 .start = 0,
30 .end = 255,
31 .flags = IORESOURCE_BUS,
32};
33
34
35LIST_HEAD(pci_root_buses);
36EXPORT_SYMBOL(pci_root_buses);
37
38static LIST_HEAD(pci_domain_busn_res_list);
39
40struct pci_domain_busn_res {
41 struct list_head list;
42 struct resource res;
43 int domain_nr;
44};
45
46static struct resource *get_pci_domain_busn_res(int domain_nr)
47{
48 struct pci_domain_busn_res *r;
49
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
52 return &r->res;
53
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 if (!r)
56 return NULL;
57
58 r->domain_nr = domain_nr;
59 r->res.start = 0;
60 r->res.end = 0xff;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
62
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
64
65 return &r->res;
66}
67
68
69
70
71
72
73int no_pci_devices(void)
74{
75 struct device *dev;
76 int no_devices;
77
78 dev = bus_find_next_device(&pci_bus_type, NULL);
79 no_devices = (dev == NULL);
80 put_device(dev);
81 return no_devices;
82}
83EXPORT_SYMBOL(no_pci_devices);
84
85
86
87
88static void release_pcibus_dev(struct device *dev)
89{
90 struct pci_bus *pci_bus = to_pci_bus(dev);
91
92 put_device(pci_bus->bridge);
93 pci_bus_remove_resources(pci_bus);
94 pci_release_bus_of_node(pci_bus);
95 kfree(pci_bus);
96}
97
98static struct class pcibus_class = {
99 .name = "pci_bus",
100 .dev_release = &release_pcibus_dev,
101 .dev_groups = pcibus_groups,
102};
103
104static int __init pcibus_class_init(void)
105{
106 return class_register(&pcibus_class);
107}
108postcore_initcall(pcibus_class_init);
109
110static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111{
112 u64 size = mask & maxbase;
113 if (!size)
114 return 0;
115
116
117
118
119
120 size = size & ~(size-1);
121
122
123
124
125
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
127 return 0;
128
129 return size;
130}
131
132static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
133{
134 u32 mem_type;
135 unsigned long flags;
136
137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
139 flags |= IORESOURCE_IO;
140 return flags;
141 }
142
143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
144 flags |= IORESOURCE_MEM;
145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
146 flags |= IORESOURCE_PREFETCH;
147
148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 switch (mem_type) {
150 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 break;
152 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
153
154 break;
155 case PCI_BASE_ADDRESS_MEM_TYPE_64:
156 flags |= IORESOURCE_MEM_64;
157 break;
158 default:
159
160 break;
161 }
162 return flags;
163}
164
165#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
166
167
168
169
170
171
172
173
174
175
176int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
177 struct resource *res, unsigned int pos)
178{
179 u32 l = 0, sz = 0, mask;
180 u64 l64, sz64, mask64;
181 u16 orig_cmd;
182 struct pci_bus_region region, inverted_region;
183
184 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
185
186
187 if (!dev->mmio_always_on) {
188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
189 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
190 pci_write_config_word(dev, PCI_COMMAND,
191 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
192 }
193 }
194
195 res->name = pci_name(dev);
196
197 pci_read_config_dword(dev, pos, &l);
198 pci_write_config_dword(dev, pos, l | mask);
199 pci_read_config_dword(dev, pos, &sz);
200 pci_write_config_dword(dev, pos, l);
201
202
203
204
205
206
207
208 if (sz == 0xffffffff)
209 sz = 0;
210
211
212
213
214
215 if (l == 0xffffffff)
216 l = 0;
217
218 if (type == pci_bar_unknown) {
219 res->flags = decode_bar(dev, l);
220 res->flags |= IORESOURCE_SIZEALIGN;
221 if (res->flags & IORESOURCE_IO) {
222 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
223 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
224 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
225 } else {
226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
229 }
230 } else {
231 if (l & PCI_ROM_ADDRESS_ENABLE)
232 res->flags |= IORESOURCE_ROM_ENABLE;
233 l64 = l & PCI_ROM_ADDRESS_MASK;
234 sz64 = sz & PCI_ROM_ADDRESS_MASK;
235 mask64 = PCI_ROM_ADDRESS_MASK;
236 }
237
238 if (res->flags & IORESOURCE_MEM_64) {
239 pci_read_config_dword(dev, pos + 4, &l);
240 pci_write_config_dword(dev, pos + 4, ~0);
241 pci_read_config_dword(dev, pos + 4, &sz);
242 pci_write_config_dword(dev, pos + 4, l);
243
244 l64 |= ((u64)l << 32);
245 sz64 |= ((u64)sz << 32);
246 mask64 |= ((u64)~0 << 32);
247 }
248
249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
251
252 if (!sz64)
253 goto fail;
254
255 sz64 = pci_size(l64, sz64, mask64);
256 if (!sz64) {
257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
258 pos);
259 goto fail;
260 }
261
262 if (res->flags & IORESOURCE_MEM_64) {
263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
264 && sz64 > 0x100000000ULL) {
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 res->start = 0;
267 res->end = 0;
268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
269 pos, (unsigned long long)sz64);
270 goto out;
271 }
272
273 if ((sizeof(pci_bus_addr_t) < 8) && l) {
274
275 res->flags |= IORESOURCE_UNSET;
276 res->start = 0;
277 res->end = sz64 - 1;
278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
279 pos, (unsigned long long)l64);
280 goto out;
281 }
282 }
283
284 region.start = l64;
285 region.end = l64 + sz64 - 1;
286
287 pcibios_bus_to_resource(dev->bus, res, ®ion);
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
289
290
291
292
293
294
295
296
297
298
299
300
301 if (inverted_region.start != region.start) {
302 res->flags |= IORESOURCE_UNSET;
303 res->start = 0;
304 res->end = region.end - region.start;
305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
306 pos, (unsigned long long)region.start);
307 }
308
309 goto out;
310
311
312fail:
313 res->flags = 0;
314out:
315 if (res->flags)
316 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
317
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
319}
320
321static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322{
323 unsigned int pos, reg;
324
325 if (dev->non_compliant_bars)
326 return;
327
328
329 if (dev->is_virtfn)
330 return;
331
332 for (pos = 0; pos < howmany; pos++) {
333 struct resource *res = &dev->resource[pos];
334 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
336 }
337
338 if (rom) {
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
340 dev->rom_base_reg = rom;
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
343 __pci_read_base(dev, pci_bar_mem32, res, rom);
344 }
345}
346
347static void pci_read_bridge_windows(struct pci_dev *bridge)
348{
349 u16 io;
350 u32 pmem, tmp;
351
352 pci_read_config_word(bridge, PCI_IO_BASE, &io);
353 if (!io) {
354 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
355 pci_read_config_word(bridge, PCI_IO_BASE, &io);
356 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
357 }
358 if (io)
359 bridge->io_window = 1;
360
361
362
363
364
365
366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
367 return;
368
369 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
370 if (!pmem) {
371 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
372 0xffe0fff0);
373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
374 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
375 }
376 if (!pmem)
377 return;
378
379 bridge->pref_window = 1;
380
381 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
382
383
384
385
386
387
388 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
389 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
390 0xffffffff);
391 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
392 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
393 if (tmp)
394 bridge->pref_64_window = 1;
395 }
396}
397
398static void pci_read_bridge_io(struct pci_bus *child)
399{
400 struct pci_dev *dev = child->self;
401 u8 io_base_lo, io_limit_lo;
402 unsigned long io_mask, io_granularity, base, limit;
403 struct pci_bus_region region;
404 struct resource *res;
405
406 io_mask = PCI_IO_RANGE_MASK;
407 io_granularity = 0x1000;
408 if (dev->io_window_1k) {
409
410 io_mask = PCI_IO_1K_RANGE_MASK;
411 io_granularity = 0x400;
412 }
413
414 res = child->resource[0];
415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
417 base = (io_base_lo & io_mask) << 8;
418 limit = (io_limit_lo & io_mask) << 8;
419
420 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
421 u16 io_base_hi, io_limit_hi;
422
423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
425 base |= ((unsigned long) io_base_hi << 16);
426 limit |= ((unsigned long) io_limit_hi << 16);
427 }
428
429 if (base <= limit) {
430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
431 region.start = base;
432 region.end = limit + io_granularity - 1;
433 pcibios_bus_to_resource(dev->bus, res, ®ion);
434 pci_info(dev, " bridge window %pR\n", res);
435 }
436}
437
438static void pci_read_bridge_mmio(struct pci_bus *child)
439{
440 struct pci_dev *dev = child->self;
441 u16 mem_base_lo, mem_limit_lo;
442 unsigned long base, limit;
443 struct pci_bus_region region;
444 struct resource *res;
445
446 res = child->resource[1];
447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
449 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
450 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 if (base <= limit) {
452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
453 region.start = base;
454 region.end = limit + 0xfffff;
455 pcibios_bus_to_resource(dev->bus, res, ®ion);
456 pci_info(dev, " bridge window %pR\n", res);
457 }
458}
459
460static void pci_read_bridge_mmio_pref(struct pci_bus *child)
461{
462 struct pci_dev *dev = child->self;
463 u16 mem_base_lo, mem_limit_lo;
464 u64 base64, limit64;
465 pci_bus_addr_t base, limit;
466 struct pci_bus_region region;
467 struct resource *res;
468
469 res = child->resource[2];
470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
472 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
473 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
474
475 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
476 u32 mem_base_hi, mem_limit_hi;
477
478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
480
481
482
483
484
485
486 if (mem_base_hi <= mem_limit_hi) {
487 base64 |= (u64) mem_base_hi << 32;
488 limit64 |= (u64) mem_limit_hi << 32;
489 }
490 }
491
492 base = (pci_bus_addr_t) base64;
493 limit = (pci_bus_addr_t) limit64;
494
495 if (base != base64) {
496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
497 (unsigned long long) base64);
498 return;
499 }
500
501 if (base <= limit) {
502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
503 IORESOURCE_MEM | IORESOURCE_PREFETCH;
504 if (res->flags & PCI_PREF_RANGE_TYPE_64)
505 res->flags |= IORESOURCE_MEM_64;
506 region.start = base;
507 region.end = limit + 0xfffff;
508 pcibios_bus_to_resource(dev->bus, res, ®ion);
509 pci_info(dev, " bridge window %pR\n", res);
510 }
511}
512
513void pci_read_bridge_bases(struct pci_bus *child)
514{
515 struct pci_dev *dev = child->self;
516 struct resource *res;
517 int i;
518
519 if (pci_is_root_bus(child))
520 return;
521
522 pci_info(dev, "PCI bridge to %pR%s\n",
523 &child->busn_res,
524 dev->transparent ? " (subtractive decode)" : "");
525
526 pci_bus_remove_resources(child);
527 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
529
530 pci_read_bridge_io(child);
531 pci_read_bridge_mmio(child);
532 pci_read_bridge_mmio_pref(child);
533
534 if (dev->transparent) {
535 pci_bus_for_each_resource(child->parent, res, i) {
536 if (res && res->flags) {
537 pci_bus_add_resource(child, res,
538 PCI_SUBTRACTIVE_DECODE);
539 pci_info(dev, " bridge window %pR (subtractive decode)\n",
540 res);
541 }
542 }
543 }
544}
545
546static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
547{
548 struct pci_bus *b;
549
550 b = kzalloc(sizeof(*b), GFP_KERNEL);
551 if (!b)
552 return NULL;
553
554 INIT_LIST_HEAD(&b->node);
555 INIT_LIST_HEAD(&b->children);
556 INIT_LIST_HEAD(&b->devices);
557 INIT_LIST_HEAD(&b->slots);
558 INIT_LIST_HEAD(&b->resources);
559 b->max_bus_speed = PCI_SPEED_UNKNOWN;
560 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
561#ifdef CONFIG_PCI_DOMAINS_GENERIC
562 if (parent)
563 b->domain_nr = parent->domain_nr;
564#endif
565 return b;
566}
567
568static void pci_release_host_bridge_dev(struct device *dev)
569{
570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
571
572 if (bridge->release_fn)
573 bridge->release_fn(bridge);
574
575 pci_free_resource_list(&bridge->windows);
576 pci_free_resource_list(&bridge->dma_ranges);
577 kfree(bridge);
578}
579
580static void pci_init_host_bridge(struct pci_host_bridge *bridge)
581{
582 INIT_LIST_HEAD(&bridge->windows);
583 INIT_LIST_HEAD(&bridge->dma_ranges);
584
585
586
587
588
589
590
591 bridge->native_aer = 1;
592 bridge->native_pcie_hotplug = 1;
593 bridge->native_shpc_hotplug = 1;
594 bridge->native_pme = 1;
595 bridge->native_ltr = 1;
596 bridge->native_dpc = 1;
597
598 device_initialize(&bridge->dev);
599}
600
601struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
602{
603 struct pci_host_bridge *bridge;
604
605 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
606 if (!bridge)
607 return NULL;
608
609 pci_init_host_bridge(bridge);
610 bridge->dev.release = pci_release_host_bridge_dev;
611
612 return bridge;
613}
614EXPORT_SYMBOL(pci_alloc_host_bridge);
615
616static void devm_pci_alloc_host_bridge_release(void *data)
617{
618 pci_free_host_bridge(data);
619}
620
621struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
622 size_t priv)
623{
624 int ret;
625 struct pci_host_bridge *bridge;
626
627 bridge = pci_alloc_host_bridge(priv);
628 if (!bridge)
629 return NULL;
630
631 bridge->dev.parent = dev;
632
633 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
634 bridge);
635 if (ret)
636 return NULL;
637
638 ret = devm_of_pci_bridge_init(dev, bridge);
639 if (ret)
640 return NULL;
641
642 return bridge;
643}
644EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
645
646void pci_free_host_bridge(struct pci_host_bridge *bridge)
647{
648 put_device(&bridge->dev);
649}
650EXPORT_SYMBOL(pci_free_host_bridge);
651
652
653static const unsigned char pcix_bus_speed[] = {
654 PCI_SPEED_UNKNOWN,
655 PCI_SPEED_66MHz_PCIX,
656 PCI_SPEED_100MHz_PCIX,
657 PCI_SPEED_133MHz_PCIX,
658 PCI_SPEED_UNKNOWN,
659 PCI_SPEED_66MHz_PCIX_ECC,
660 PCI_SPEED_100MHz_PCIX_ECC,
661 PCI_SPEED_133MHz_PCIX_ECC,
662 PCI_SPEED_UNKNOWN,
663 PCI_SPEED_66MHz_PCIX_266,
664 PCI_SPEED_100MHz_PCIX_266,
665 PCI_SPEED_133MHz_PCIX_266,
666 PCI_SPEED_UNKNOWN,
667 PCI_SPEED_66MHz_PCIX_533,
668 PCI_SPEED_100MHz_PCIX_533,
669 PCI_SPEED_133MHz_PCIX_533
670};
671
672
673const unsigned char pcie_link_speed[] = {
674 PCI_SPEED_UNKNOWN,
675 PCIE_SPEED_2_5GT,
676 PCIE_SPEED_5_0GT,
677 PCIE_SPEED_8_0GT,
678 PCIE_SPEED_16_0GT,
679 PCIE_SPEED_32_0GT,
680 PCIE_SPEED_64_0GT,
681 PCI_SPEED_UNKNOWN,
682 PCI_SPEED_UNKNOWN,
683 PCI_SPEED_UNKNOWN,
684 PCI_SPEED_UNKNOWN,
685 PCI_SPEED_UNKNOWN,
686 PCI_SPEED_UNKNOWN,
687 PCI_SPEED_UNKNOWN,
688 PCI_SPEED_UNKNOWN,
689 PCI_SPEED_UNKNOWN
690};
691EXPORT_SYMBOL_GPL(pcie_link_speed);
692
693const char *pci_speed_string(enum pci_bus_speed speed)
694{
695
696 static const char *speed_strings[] = {
697 "33 MHz PCI",
698 "66 MHz PCI",
699 "66 MHz PCI-X",
700 "100 MHz PCI-X",
701 "133 MHz PCI-X",
702 NULL,
703 NULL,
704 NULL,
705 NULL,
706 "66 MHz PCI-X 266",
707 "100 MHz PCI-X 266",
708 "133 MHz PCI-X 266",
709 "Unknown AGP",
710 "1x AGP",
711 "2x AGP",
712 "4x AGP",
713 "8x AGP",
714 "66 MHz PCI-X 533",
715 "100 MHz PCI-X 533",
716 "133 MHz PCI-X 533",
717 "2.5 GT/s PCIe",
718 "5.0 GT/s PCIe",
719 "8.0 GT/s PCIe",
720 "16.0 GT/s PCIe",
721 "32.0 GT/s PCIe",
722 "64.0 GT/s PCIe",
723 };
724
725 if (speed < ARRAY_SIZE(speed_strings))
726 return speed_strings[speed];
727 return "Unknown";
728}
729EXPORT_SYMBOL_GPL(pci_speed_string);
730
731void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
732{
733 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
734}
735EXPORT_SYMBOL_GPL(pcie_update_link_speed);
736
737static unsigned char agp_speeds[] = {
738 AGP_UNKNOWN,
739 AGP_1X,
740 AGP_2X,
741 AGP_4X,
742 AGP_8X
743};
744
745static enum pci_bus_speed agp_speed(int agp3, int agpstat)
746{
747 int index = 0;
748
749 if (agpstat & 4)
750 index = 3;
751 else if (agpstat & 2)
752 index = 2;
753 else if (agpstat & 1)
754 index = 1;
755 else
756 goto out;
757
758 if (agp3) {
759 index += 2;
760 if (index == 5)
761 index = 0;
762 }
763
764 out:
765 return agp_speeds[index];
766}
767
768static void pci_set_bus_speed(struct pci_bus *bus)
769{
770 struct pci_dev *bridge = bus->self;
771 int pos;
772
773 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
774 if (!pos)
775 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
776 if (pos) {
777 u32 agpstat, agpcmd;
778
779 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
780 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
781
782 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
783 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
784 }
785
786 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
787 if (pos) {
788 u16 status;
789 enum pci_bus_speed max;
790
791 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
792 &status);
793
794 if (status & PCI_X_SSTATUS_533MHZ) {
795 max = PCI_SPEED_133MHz_PCIX_533;
796 } else if (status & PCI_X_SSTATUS_266MHZ) {
797 max = PCI_SPEED_133MHz_PCIX_266;
798 } else if (status & PCI_X_SSTATUS_133MHZ) {
799 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
800 max = PCI_SPEED_133MHz_PCIX_ECC;
801 else
802 max = PCI_SPEED_133MHz_PCIX;
803 } else {
804 max = PCI_SPEED_66MHz_PCIX;
805 }
806
807 bus->max_bus_speed = max;
808 bus->cur_bus_speed = pcix_bus_speed[
809 (status & PCI_X_SSTATUS_FREQ) >> 6];
810
811 return;
812 }
813
814 if (pci_is_pcie(bridge)) {
815 u32 linkcap;
816 u16 linksta;
817
818 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
819 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
820 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
821
822 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
823 pcie_update_link_speed(bus, linksta);
824 }
825}
826
827static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
828{
829 struct irq_domain *d;
830
831
832
833
834
835 d = pci_host_bridge_of_msi_domain(bus);
836 if (!d)
837 d = pci_host_bridge_acpi_msi_domain(bus);
838
839#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
840
841
842
843
844 if (!d) {
845 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
846
847 if (fwnode)
848 d = irq_find_matching_fwnode(fwnode,
849 DOMAIN_BUS_PCI_MSI);
850 }
851#endif
852
853 return d;
854}
855
856static void pci_set_bus_msi_domain(struct pci_bus *bus)
857{
858 struct irq_domain *d;
859 struct pci_bus *b;
860
861
862
863
864
865
866 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
867 if (b->self)
868 d = dev_get_msi_domain(&b->self->dev);
869 }
870
871 if (!d)
872 d = pci_host_bridge_msi_domain(b);
873
874 dev_set_msi_domain(&bus->dev, d);
875}
876
877static int pci_register_host_bridge(struct pci_host_bridge *bridge)
878{
879 struct device *parent = bridge->dev.parent;
880 struct resource_entry *window, *n;
881 struct pci_bus *bus, *b;
882 resource_size_t offset;
883 LIST_HEAD(resources);
884 struct resource *res;
885 char addr[64], *fmt;
886 const char *name;
887 int err;
888
889 bus = pci_alloc_bus(NULL);
890 if (!bus)
891 return -ENOMEM;
892
893 bridge->bus = bus;
894
895
896 list_splice_init(&bridge->windows, &resources);
897 bus->sysdata = bridge->sysdata;
898 bus->ops = bridge->ops;
899 bus->number = bus->busn_res.start = bridge->busnr;
900#ifdef CONFIG_PCI_DOMAINS_GENERIC
901 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
902#endif
903
904 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
905 if (b) {
906
907 dev_dbg(&b->dev, "bus already known\n");
908 err = -EEXIST;
909 goto free;
910 }
911
912 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
913 bridge->busnr);
914
915 err = pcibios_root_bridge_prepare(bridge);
916 if (err)
917 goto free;
918
919 err = device_add(&bridge->dev);
920 if (err) {
921 put_device(&bridge->dev);
922 goto free;
923 }
924 bus->bridge = get_device(&bridge->dev);
925 device_enable_async_suspend(bus->bridge);
926 pci_set_bus_of_node(bus);
927 pci_set_bus_msi_domain(bus);
928 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&
929 !pci_host_of_has_msi_map(parent))
930 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
931
932 if (!parent)
933 set_dev_node(bus->bridge, pcibus_to_node(bus));
934
935 bus->dev.class = &pcibus_class;
936 bus->dev.parent = bus->bridge;
937
938 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
939 name = dev_name(&bus->dev);
940
941 err = device_register(&bus->dev);
942 if (err)
943 goto unregister;
944
945 pcibios_add_bus(bus);
946
947 if (bus->ops->add_bus) {
948 err = bus->ops->add_bus(bus);
949 if (WARN_ON(err < 0))
950 dev_err(&bus->dev, "failed to add bus: %d\n", err);
951 }
952
953
954 pci_create_legacy_files(bus);
955
956 if (parent)
957 dev_info(parent, "PCI host bridge to bus %s\n", name);
958 else
959 pr_info("PCI host bridge to bus %s\n", name);
960
961 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
962 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
963
964
965 resource_list_for_each_entry_safe(window, n, &resources) {
966 list_move_tail(&window->node, &bridge->windows);
967 offset = window->offset;
968 res = window->res;
969
970 if (res->flags & IORESOURCE_BUS)
971 pci_bus_insert_busn_res(bus, bus->number, res->end);
972 else
973 pci_bus_add_resource(bus, res, 0);
974
975 if (offset) {
976 if (resource_type(res) == IORESOURCE_IO)
977 fmt = " (bus address [%#06llx-%#06llx])";
978 else
979 fmt = " (bus address [%#010llx-%#010llx])";
980
981 snprintf(addr, sizeof(addr), fmt,
982 (unsigned long long)(res->start - offset),
983 (unsigned long long)(res->end - offset));
984 } else
985 addr[0] = '\0';
986
987 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
988 }
989
990 down_write(&pci_bus_sem);
991 list_add_tail(&bus->node, &pci_root_buses);
992 up_write(&pci_bus_sem);
993
994 return 0;
995
996unregister:
997 put_device(&bridge->dev);
998 device_del(&bridge->dev);
999
1000free:
1001 kfree(bus);
1002 return err;
1003}
1004
1005static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1006{
1007 int pos;
1008 u32 status;
1009
1010
1011
1012
1013
1014 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1015 return false;
1016
1017
1018
1019
1020
1021
1022 if (pci_is_pcie(bridge) &&
1023 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1024 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1025 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1026 return true;
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1037 if (!pos)
1038 return false;
1039
1040 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1041 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1042}
1043
1044static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1045 struct pci_dev *bridge, int busnr)
1046{
1047 struct pci_bus *child;
1048 struct pci_host_bridge *host;
1049 int i;
1050 int ret;
1051
1052
1053 child = pci_alloc_bus(parent);
1054 if (!child)
1055 return NULL;
1056
1057 child->parent = parent;
1058 child->sysdata = parent->sysdata;
1059 child->bus_flags = parent->bus_flags;
1060
1061 host = pci_find_host_bridge(parent);
1062 if (host->child_ops)
1063 child->ops = host->child_ops;
1064 else
1065 child->ops = parent->ops;
1066
1067
1068
1069
1070
1071 child->dev.class = &pcibus_class;
1072 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1073
1074
1075 child->number = child->busn_res.start = busnr;
1076 child->primary = parent->busn_res.start;
1077 child->busn_res.end = 0xff;
1078
1079 if (!bridge) {
1080 child->dev.parent = parent->bridge;
1081 goto add_dev;
1082 }
1083
1084 child->self = bridge;
1085 child->bridge = get_device(&bridge->dev);
1086 child->dev.parent = child->bridge;
1087 pci_set_bus_of_node(child);
1088 pci_set_bus_speed(child);
1089
1090
1091
1092
1093
1094
1095 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1096 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1097 pci_info(child, "extended config space not accessible\n");
1098 }
1099
1100
1101 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1102 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1103 child->resource[i]->name = child->name;
1104 }
1105 bridge->subordinate = child;
1106
1107add_dev:
1108 pci_set_bus_msi_domain(child);
1109 ret = device_register(&child->dev);
1110 WARN_ON(ret < 0);
1111
1112 pcibios_add_bus(child);
1113
1114 if (child->ops->add_bus) {
1115 ret = child->ops->add_bus(child);
1116 if (WARN_ON(ret < 0))
1117 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1118 }
1119
1120
1121 pci_create_legacy_files(child);
1122
1123 return child;
1124}
1125
1126struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1127 int busnr)
1128{
1129 struct pci_bus *child;
1130
1131 child = pci_alloc_child_bus(parent, dev, busnr);
1132 if (child) {
1133 down_write(&pci_bus_sem);
1134 list_add_tail(&child->node, &parent->children);
1135 up_write(&pci_bus_sem);
1136 }
1137 return child;
1138}
1139EXPORT_SYMBOL(pci_add_new_bus);
1140
1141static void pci_enable_crs(struct pci_dev *pdev)
1142{
1143 u16 root_cap = 0;
1144
1145
1146 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1147 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1148 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1149 PCI_EXP_RTCTL_CRSSVE);
1150}
1151
1152static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1153 unsigned int available_buses);
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1166{
1167 int ea, offset;
1168 u32 dw;
1169 u8 ea_sec, ea_sub;
1170
1171 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1172 return false;
1173
1174
1175 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1176 if (!ea)
1177 return false;
1178
1179 offset = ea + PCI_EA_FIRST_ENT;
1180 pci_read_config_dword(dev, offset, &dw);
1181 ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1182 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1183 if (ea_sec == 0 || ea_sub < ea_sec)
1184 return false;
1185
1186 *sec = ea_sec;
1187 *sub = ea_sub;
1188 return true;
1189}
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1215 int max, unsigned int available_buses,
1216 int pass)
1217{
1218 struct pci_bus *child;
1219 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1220 u32 buses, i, j = 0;
1221 u16 bctl;
1222 u8 primary, secondary, subordinate;
1223 int broken = 0;
1224 bool fixed_buses;
1225 u8 fixed_sec, fixed_sub;
1226 int next_busnr;
1227
1228
1229
1230
1231
1232 pm_runtime_get_sync(&dev->dev);
1233
1234 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1235 primary = buses & 0xFF;
1236 secondary = (buses >> 8) & 0xFF;
1237 subordinate = (buses >> 16) & 0xFF;
1238
1239 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1240 secondary, subordinate, pass);
1241
1242 if (!primary && (primary != bus->number) && secondary && subordinate) {
1243 pci_warn(dev, "Primary bus is hard wired to 0\n");
1244 primary = bus->number;
1245 }
1246
1247
1248 if (!pass &&
1249 (primary != bus->number || secondary <= bus->number ||
1250 secondary > subordinate)) {
1251 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1252 secondary, subordinate);
1253 broken = 1;
1254 }
1255
1256
1257
1258
1259
1260 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1261 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1262 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1263
1264 pci_enable_crs(dev);
1265
1266 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1267 !is_cardbus && !broken) {
1268 unsigned int cmax;
1269
1270
1271
1272
1273
1274 if (pass)
1275 goto out;
1276
1277
1278
1279
1280
1281
1282
1283 child = pci_find_bus(pci_domain_nr(bus), secondary);
1284 if (!child) {
1285 child = pci_add_new_bus(bus, dev, secondary);
1286 if (!child)
1287 goto out;
1288 child->primary = primary;
1289 pci_bus_insert_busn_res(child, secondary, subordinate);
1290 child->bridge_ctl = bctl;
1291 }
1292
1293 cmax = pci_scan_child_bus(child);
1294 if (cmax > subordinate)
1295 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1296 subordinate, cmax);
1297
1298
1299 if (subordinate > max)
1300 max = subordinate;
1301 } else {
1302
1303
1304
1305
1306
1307 if (!pass) {
1308 if (pcibios_assign_all_busses() || broken || is_cardbus)
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1319 buses & ~0xffffff);
1320 goto out;
1321 }
1322
1323
1324 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1325
1326
1327 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1328 if (fixed_buses)
1329 next_busnr = fixed_sec;
1330 else
1331 next_busnr = max + 1;
1332
1333
1334
1335
1336
1337
1338 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1339 if (!child) {
1340 child = pci_add_new_bus(bus, dev, next_busnr);
1341 if (!child)
1342 goto out;
1343 pci_bus_insert_busn_res(child, next_busnr,
1344 bus->busn_res.end);
1345 }
1346 max++;
1347 if (available_buses)
1348 available_buses--;
1349
1350 buses = (buses & 0xff000000)
1351 | ((unsigned int)(child->primary) << 0)
1352 | ((unsigned int)(child->busn_res.start) << 8)
1353 | ((unsigned int)(child->busn_res.end) << 16);
1354
1355
1356
1357
1358
1359 if (is_cardbus) {
1360 buses &= ~0xff000000;
1361 buses |= CARDBUS_LATENCY_TIMER << 24;
1362 }
1363
1364
1365 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1366
1367 if (!is_cardbus) {
1368 child->bridge_ctl = bctl;
1369 max = pci_scan_child_bus_extend(child, available_buses);
1370 } else {
1371
1372
1373
1374
1375
1376
1377 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1378 struct pci_bus *parent = bus;
1379 if (pci_find_bus(pci_domain_nr(bus),
1380 max+i+1))
1381 break;
1382 while (parent->parent) {
1383 if ((!pcibios_assign_all_busses()) &&
1384 (parent->busn_res.end > max) &&
1385 (parent->busn_res.end <= max+i)) {
1386 j = 1;
1387 }
1388 parent = parent->parent;
1389 }
1390 if (j) {
1391
1392
1393
1394
1395
1396
1397 i /= 2;
1398 break;
1399 }
1400 }
1401 max += i;
1402 }
1403
1404
1405
1406
1407
1408
1409 if (fixed_buses)
1410 max = fixed_sub;
1411 pci_bus_update_busn_res_end(child, max);
1412 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1413 }
1414
1415 sprintf(child->name,
1416 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1417 pci_domain_nr(bus), child->number);
1418
1419
1420 while (bus->parent) {
1421 if ((child->busn_res.end > bus->busn_res.end) ||
1422 (child->number > bus->busn_res.end) ||
1423 (child->number < bus->number) ||
1424 (child->busn_res.end < bus->number)) {
1425 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1426 &child->busn_res);
1427 break;
1428 }
1429 bus = bus->parent;
1430 }
1431
1432out:
1433 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1434
1435 pm_runtime_put(&dev->dev);
1436
1437 return max;
1438}
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1460{
1461 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1462}
1463EXPORT_SYMBOL(pci_scan_bridge);
1464
1465
1466
1467
1468
1469static void pci_read_irq(struct pci_dev *dev)
1470{
1471 unsigned char irq;
1472
1473
1474 if (dev->is_virtfn) {
1475 dev->pin = 0;
1476 dev->irq = 0;
1477 return;
1478 }
1479
1480 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1481 dev->pin = irq;
1482 if (irq)
1483 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1484 dev->irq = irq;
1485}
1486
1487void set_pcie_port_type(struct pci_dev *pdev)
1488{
1489 int pos;
1490 u16 reg16;
1491 int type;
1492 struct pci_dev *parent;
1493
1494 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1495 if (!pos)
1496 return;
1497
1498 pdev->pcie_cap = pos;
1499 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1500 pdev->pcie_flags_reg = reg16;
1501 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1502 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1503
1504 parent = pci_upstream_bridge(pdev);
1505 if (!parent)
1506 return;
1507
1508
1509
1510
1511
1512
1513 type = pci_pcie_type(pdev);
1514 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1515
1516
1517
1518
1519
1520 if (pcie_downstream_port(parent)) {
1521 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1522 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1523 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1524 }
1525 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1526
1527
1528
1529
1530
1531 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1532 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1533 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1534 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1535 }
1536 }
1537}
1538
1539void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1540{
1541 u32 reg32;
1542
1543 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1544 if (reg32 & PCI_EXP_SLTCAP_HPC)
1545 pdev->is_hotplug_bridge = 1;
1546}
1547
1548static void set_pcie_thunderbolt(struct pci_dev *dev)
1549{
1550 int vsec = 0;
1551 u32 header;
1552
1553 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1554 PCI_EXT_CAP_ID_VNDR))) {
1555 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1556
1557
1558 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1559 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1560 dev->is_thunderbolt = 1;
1561 return;
1562 }
1563 }
1564}
1565
1566static void set_pcie_untrusted(struct pci_dev *dev)
1567{
1568 struct pci_dev *parent;
1569
1570
1571
1572
1573
1574 parent = pci_upstream_bridge(dev);
1575 if (parent && (parent->untrusted || parent->external_facing))
1576 dev->untrusted = true;
1577}
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1596{
1597#ifdef CONFIG_PCI_QUIRKS
1598 int pos;
1599 u32 header, tmp;
1600
1601 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1602
1603 for (pos = PCI_CFG_SPACE_SIZE;
1604 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1605 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1606 || header != tmp)
1607 return false;
1608 }
1609
1610 return true;
1611#else
1612 return false;
1613#endif
1614}
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627static int pci_cfg_space_size_ext(struct pci_dev *dev)
1628{
1629 u32 status;
1630 int pos = PCI_CFG_SPACE_SIZE;
1631
1632 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1633 return PCI_CFG_SPACE_SIZE;
1634 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1635 return PCI_CFG_SPACE_SIZE;
1636
1637 return PCI_CFG_SPACE_EXP_SIZE;
1638}
1639
1640int pci_cfg_space_size(struct pci_dev *dev)
1641{
1642 int pos;
1643 u32 status;
1644 u16 class;
1645
1646#ifdef CONFIG_PCI_IOV
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657 if (dev->is_virtfn)
1658 return PCI_CFG_SPACE_EXP_SIZE;
1659#endif
1660
1661 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1662 return PCI_CFG_SPACE_SIZE;
1663
1664 class = dev->class >> 8;
1665 if (class == PCI_CLASS_BRIDGE_HOST)
1666 return pci_cfg_space_size_ext(dev);
1667
1668 if (pci_is_pcie(dev))
1669 return pci_cfg_space_size_ext(dev);
1670
1671 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1672 if (!pos)
1673 return PCI_CFG_SPACE_SIZE;
1674
1675 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1676 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1677 return pci_cfg_space_size_ext(dev);
1678
1679 return PCI_CFG_SPACE_SIZE;
1680}
1681
1682static u32 pci_class(struct pci_dev *dev)
1683{
1684 u32 class;
1685
1686#ifdef CONFIG_PCI_IOV
1687 if (dev->is_virtfn)
1688 return dev->physfn->sriov->class;
1689#endif
1690 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1691 return class;
1692}
1693
1694static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1695{
1696#ifdef CONFIG_PCI_IOV
1697 if (dev->is_virtfn) {
1698 *vendor = dev->physfn->sriov->subsystem_vendor;
1699 *device = dev->physfn->sriov->subsystem_device;
1700 return;
1701 }
1702#endif
1703 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1704 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1705}
1706
1707static u8 pci_hdr_type(struct pci_dev *dev)
1708{
1709 u8 hdr_type;
1710
1711#ifdef CONFIG_PCI_IOV
1712 if (dev->is_virtfn)
1713 return dev->physfn->sriov->hdr_type;
1714#endif
1715 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1716 return hdr_type;
1717}
1718
1719#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1720
1721
1722
1723
1724
1725
1726
1727
1728static int pci_intx_mask_broken(struct pci_dev *dev)
1729{
1730 u16 orig, toggle, new;
1731
1732 pci_read_config_word(dev, PCI_COMMAND, &orig);
1733 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1734 pci_write_config_word(dev, PCI_COMMAND, toggle);
1735 pci_read_config_word(dev, PCI_COMMAND, &new);
1736
1737 pci_write_config_word(dev, PCI_COMMAND, orig);
1738
1739
1740
1741
1742
1743
1744 if (new != toggle)
1745 return 1;
1746 return 0;
1747}
1748
1749static void early_dump_pci_device(struct pci_dev *pdev)
1750{
1751 u32 value[256 / 4];
1752 int i;
1753
1754 pci_info(pdev, "config space:\n");
1755
1756 for (i = 0; i < 256; i += 4)
1757 pci_read_config_dword(pdev, i, &value[i / 4]);
1758
1759 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1760 value, 256, false);
1761}
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773int pci_setup_device(struct pci_dev *dev)
1774{
1775 u32 class;
1776 u16 cmd;
1777 u8 hdr_type;
1778 int pos = 0;
1779 struct pci_bus_region region;
1780 struct resource *res;
1781
1782 hdr_type = pci_hdr_type(dev);
1783
1784 dev->sysdata = dev->bus->sysdata;
1785 dev->dev.parent = dev->bus->bridge;
1786 dev->dev.bus = &pci_bus_type;
1787 dev->hdr_type = hdr_type & 0x7f;
1788 dev->multifunction = !!(hdr_type & 0x80);
1789 dev->error_state = pci_channel_io_normal;
1790 set_pcie_port_type(dev);
1791
1792 pci_dev_assign_slot(dev);
1793
1794
1795
1796
1797
1798 dev->dma_mask = 0xffffffff;
1799
1800 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1801 dev->bus->number, PCI_SLOT(dev->devfn),
1802 PCI_FUNC(dev->devfn));
1803
1804 class = pci_class(dev);
1805
1806 dev->revision = class & 0xff;
1807 dev->class = class >> 8;
1808
1809 if (pci_early_dump)
1810 early_dump_pci_device(dev);
1811
1812
1813 dev->cfg_size = pci_cfg_space_size(dev);
1814
1815
1816 set_pcie_thunderbolt(dev);
1817
1818 set_pcie_untrusted(dev);
1819
1820
1821 dev->current_state = PCI_UNKNOWN;
1822
1823
1824 pci_fixup_device(pci_fixup_early, dev);
1825
1826 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1827 dev->vendor, dev->device, dev->hdr_type, dev->class);
1828
1829
1830 class = dev->class >> 8;
1831
1832 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1833 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1834 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1835 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1836 cmd &= ~PCI_COMMAND_IO;
1837 cmd &= ~PCI_COMMAND_MEMORY;
1838 pci_write_config_word(dev, PCI_COMMAND, cmd);
1839 }
1840 }
1841
1842 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1843
1844 switch (dev->hdr_type) {
1845 case PCI_HEADER_TYPE_NORMAL:
1846 if (class == PCI_CLASS_BRIDGE_PCI)
1847 goto bad;
1848 pci_read_irq(dev);
1849 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1850
1851 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1852
1853
1854
1855
1856
1857
1858
1859 if (class == PCI_CLASS_STORAGE_IDE) {
1860 u8 progif;
1861 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1862 if ((progif & 1) == 0) {
1863 region.start = 0x1F0;
1864 region.end = 0x1F7;
1865 res = &dev->resource[0];
1866 res->flags = LEGACY_IO_RESOURCE;
1867 pcibios_bus_to_resource(dev->bus, res, ®ion);
1868 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1869 res);
1870 region.start = 0x3F6;
1871 region.end = 0x3F6;
1872 res = &dev->resource[1];
1873 res->flags = LEGACY_IO_RESOURCE;
1874 pcibios_bus_to_resource(dev->bus, res, ®ion);
1875 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1876 res);
1877 }
1878 if ((progif & 4) == 0) {
1879 region.start = 0x170;
1880 region.end = 0x177;
1881 res = &dev->resource[2];
1882 res->flags = LEGACY_IO_RESOURCE;
1883 pcibios_bus_to_resource(dev->bus, res, ®ion);
1884 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1885 res);
1886 region.start = 0x376;
1887 region.end = 0x376;
1888 res = &dev->resource[3];
1889 res->flags = LEGACY_IO_RESOURCE;
1890 pcibios_bus_to_resource(dev->bus, res, ®ion);
1891 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1892 res);
1893 }
1894 }
1895 break;
1896
1897 case PCI_HEADER_TYPE_BRIDGE:
1898
1899
1900
1901
1902
1903 pci_read_irq(dev);
1904 dev->transparent = ((dev->class & 0xff) == 1);
1905 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1906 pci_read_bridge_windows(dev);
1907 set_pcie_hotplug_bridge(dev);
1908 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1909 if (pos) {
1910 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1911 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1912 }
1913 break;
1914
1915 case PCI_HEADER_TYPE_CARDBUS:
1916 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1917 goto bad;
1918 pci_read_irq(dev);
1919 pci_read_bases(dev, 1, 0);
1920 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1921 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1922 break;
1923
1924 default:
1925 pci_err(dev, "unknown header type %02x, ignoring device\n",
1926 dev->hdr_type);
1927 return -EIO;
1928
1929 bad:
1930 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1931 dev->class, dev->hdr_type);
1932 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1933 }
1934
1935
1936 return 0;
1937}
1938
1939static void pci_configure_mps(struct pci_dev *dev)
1940{
1941 struct pci_dev *bridge = pci_upstream_bridge(dev);
1942 int mps, mpss, p_mps, rc;
1943
1944 if (!pci_is_pcie(dev))
1945 return;
1946
1947
1948 if (dev->is_virtfn)
1949 return;
1950
1951
1952
1953
1954
1955 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
1956 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1957 mps = 128;
1958 else
1959 mps = 128 << dev->pcie_mpss;
1960 rc = pcie_set_mps(dev, mps);
1961 if (rc) {
1962 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1963 mps);
1964 }
1965 return;
1966 }
1967
1968 if (!bridge || !pci_is_pcie(bridge))
1969 return;
1970
1971 mps = pcie_get_mps(dev);
1972 p_mps = pcie_get_mps(bridge);
1973
1974 if (mps == p_mps)
1975 return;
1976
1977 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1978 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1979 mps, pci_name(bridge), p_mps);
1980 return;
1981 }
1982
1983
1984
1985
1986
1987 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1988 return;
1989
1990 mpss = 128 << dev->pcie_mpss;
1991 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
1992 pcie_set_mps(bridge, mpss);
1993 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
1994 mpss, p_mps, 128 << bridge->pcie_mpss);
1995 p_mps = pcie_get_mps(bridge);
1996 }
1997
1998 rc = pcie_set_mps(dev, p_mps);
1999 if (rc) {
2000 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2001 p_mps);
2002 return;
2003 }
2004
2005 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2006 p_mps, mps, mpss);
2007}
2008
2009int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2010{
2011 struct pci_host_bridge *host;
2012 u32 cap;
2013 u16 ctl;
2014 int ret;
2015
2016 if (!pci_is_pcie(dev))
2017 return 0;
2018
2019 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2020 if (ret)
2021 return 0;
2022
2023 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2024 return 0;
2025
2026 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2027 if (ret)
2028 return 0;
2029
2030 host = pci_find_host_bridge(dev->bus);
2031 if (!host)
2032 return 0;
2033
2034
2035
2036
2037
2038 if (host->no_ext_tags) {
2039 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2040 pci_info(dev, "disabling Extended Tags\n");
2041 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2042 PCI_EXP_DEVCTL_EXT_TAG);
2043 }
2044 return 0;
2045 }
2046
2047 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2048 pci_info(dev, "enabling Extended Tags\n");
2049 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2050 PCI_EXP_DEVCTL_EXT_TAG);
2051 }
2052 return 0;
2053}
2054
2055
2056
2057
2058
2059
2060
2061bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2062{
2063 u16 v;
2064
2065 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2066
2067 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2068}
2069EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2070
2071static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2072{
2073 struct pci_dev *root;
2074
2075
2076 if (dev->is_virtfn)
2077 return;
2078
2079 if (!pcie_relaxed_ordering_enabled(dev))
2080 return;
2081
2082
2083
2084
2085
2086 root = pcie_find_root_port(dev);
2087 if (!root)
2088 return;
2089
2090 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2091 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2092 PCI_EXP_DEVCTL_RELAX_EN);
2093 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2094 }
2095}
2096
2097static void pci_configure_ltr(struct pci_dev *dev)
2098{
2099#ifdef CONFIG_PCIEASPM
2100 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2101 struct pci_dev *bridge;
2102 u32 cap, ctl;
2103
2104 if (!pci_is_pcie(dev))
2105 return;
2106
2107
2108 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2109
2110 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2111 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2112 return;
2113
2114 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2115 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2116 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2117 dev->ltr_path = 1;
2118 return;
2119 }
2120
2121 bridge = pci_upstream_bridge(dev);
2122 if (bridge && bridge->ltr_path)
2123 dev->ltr_path = 1;
2124
2125 return;
2126 }
2127
2128 if (!host->native_ltr)
2129 return;
2130
2131
2132
2133
2134
2135
2136 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2137 ((bridge = pci_upstream_bridge(dev)) &&
2138 bridge->ltr_path)) {
2139 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2140 PCI_EXP_DEVCTL2_LTR_EN);
2141 dev->ltr_path = 1;
2142 }
2143#endif
2144}
2145
2146static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2147{
2148#ifdef CONFIG_PCI_PASID
2149 struct pci_dev *bridge;
2150 int pcie_type;
2151 u32 cap;
2152
2153 if (!pci_is_pcie(dev))
2154 return;
2155
2156 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2157 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2158 return;
2159
2160 pcie_type = pci_pcie_type(dev);
2161 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2162 pcie_type == PCI_EXP_TYPE_RC_END)
2163 dev->eetlp_prefix_path = 1;
2164 else {
2165 bridge = pci_upstream_bridge(dev);
2166 if (bridge && bridge->eetlp_prefix_path)
2167 dev->eetlp_prefix_path = 1;
2168 }
2169#endif
2170}
2171
2172static void pci_configure_serr(struct pci_dev *dev)
2173{
2174 u16 control;
2175
2176 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2177
2178
2179
2180
2181
2182 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2183 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2184 control |= PCI_BRIDGE_CTL_SERR;
2185 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2186 }
2187 }
2188}
2189
2190static void pci_configure_device(struct pci_dev *dev)
2191{
2192 pci_configure_mps(dev);
2193 pci_configure_extended_tags(dev, NULL);
2194 pci_configure_relaxed_ordering(dev);
2195 pci_configure_ltr(dev);
2196 pci_configure_eetlp_prefix(dev);
2197 pci_configure_serr(dev);
2198
2199 pci_acpi_program_hp_params(dev);
2200}
2201
2202static void pci_release_capabilities(struct pci_dev *dev)
2203{
2204 pci_aer_exit(dev);
2205 pci_rcec_exit(dev);
2206 pci_vpd_release(dev);
2207 pci_iov_release(dev);
2208 pci_free_cap_save_buffers(dev);
2209}
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219static void pci_release_dev(struct device *dev)
2220{
2221 struct pci_dev *pci_dev;
2222
2223 pci_dev = to_pci_dev(dev);
2224 pci_release_capabilities(pci_dev);
2225 pci_release_of_node(pci_dev);
2226 pcibios_release_device(pci_dev);
2227 pci_bus_put(pci_dev->bus);
2228 kfree(pci_dev->driver_override);
2229 bitmap_free(pci_dev->dma_alias_mask);
2230 kfree(pci_dev);
2231}
2232
2233struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2234{
2235 struct pci_dev *dev;
2236
2237 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2238 if (!dev)
2239 return NULL;
2240
2241 INIT_LIST_HEAD(&dev->bus_list);
2242 dev->dev.type = &pci_dev_type;
2243 dev->bus = pci_bus_get(bus);
2244
2245 return dev;
2246}
2247EXPORT_SYMBOL(pci_alloc_dev);
2248
2249static bool pci_bus_crs_vendor_id(u32 l)
2250{
2251 return (l & 0xffff) == 0x0001;
2252}
2253
2254static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2255 int timeout)
2256{
2257 int delay = 1;
2258
2259 if (!pci_bus_crs_vendor_id(*l))
2260 return true;
2261
2262 if (!timeout)
2263 return false;
2264
2265
2266
2267
2268
2269
2270 while (pci_bus_crs_vendor_id(*l)) {
2271 if (delay > timeout) {
2272 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2273 pci_domain_nr(bus), bus->number,
2274 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2275
2276 return false;
2277 }
2278 if (delay >= 1000)
2279 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2280 pci_domain_nr(bus), bus->number,
2281 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2282
2283 msleep(delay);
2284 delay *= 2;
2285
2286 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2287 return false;
2288 }
2289
2290 if (delay >= 1000)
2291 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2292 pci_domain_nr(bus), bus->number,
2293 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2294
2295 return true;
2296}
2297
2298bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2299 int timeout)
2300{
2301 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2302 return false;
2303
2304
2305 if (*l == 0xffffffff || *l == 0x00000000 ||
2306 *l == 0x0000ffff || *l == 0xffff0000)
2307 return false;
2308
2309 if (pci_bus_crs_vendor_id(*l))
2310 return pci_bus_wait_crs(bus, devfn, l, timeout);
2311
2312 return true;
2313}
2314
2315bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2316 int timeout)
2317{
2318#ifdef CONFIG_PCI_QUIRKS
2319 struct pci_dev *bridge = bus->self;
2320
2321
2322
2323
2324
2325 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2326 bridge->device == 0x80b5)
2327 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2328#endif
2329
2330 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2331}
2332EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2333
2334
2335
2336
2337
2338static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2339{
2340 struct pci_dev *dev;
2341 u32 l;
2342
2343 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2344 return NULL;
2345
2346 dev = pci_alloc_dev(bus);
2347 if (!dev)
2348 return NULL;
2349
2350 dev->devfn = devfn;
2351 dev->vendor = l & 0xffff;
2352 dev->device = (l >> 16) & 0xffff;
2353
2354 pci_set_of_node(dev);
2355
2356 if (pci_setup_device(dev)) {
2357 pci_release_of_node(dev);
2358 pci_bus_put(dev->bus);
2359 kfree(dev);
2360 return NULL;
2361 }
2362
2363 return dev;
2364}
2365
2366void pcie_report_downtraining(struct pci_dev *dev)
2367{
2368 if (!pci_is_pcie(dev))
2369 return;
2370
2371
2372 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2373 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2374 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2375 return;
2376
2377
2378 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2379 return;
2380
2381
2382 __pcie_print_link_status(dev, false);
2383}
2384
2385static void pci_init_capabilities(struct pci_dev *dev)
2386{
2387 pci_ea_init(dev);
2388 pci_msi_init(dev);
2389 pci_msix_init(dev);
2390
2391
2392 pci_allocate_cap_save_buffers(dev);
2393
2394 pci_pm_init(dev);
2395 pci_vpd_init(dev);
2396 pci_configure_ari(dev);
2397 pci_iov_init(dev);
2398 pci_ats_init(dev);
2399 pci_pri_init(dev);
2400 pci_pasid_init(dev);
2401 pci_acs_init(dev);
2402 pci_ptm_init(dev);
2403 pci_aer_init(dev);
2404 pci_dpc_init(dev);
2405 pci_rcec_init(dev);
2406
2407 pcie_report_downtraining(dev);
2408
2409 if (pci_probe_reset_function(dev) == 0)
2410 dev->reset_fn = 1;
2411}
2412
2413
2414
2415
2416
2417
2418static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2419{
2420 struct irq_domain *d;
2421
2422
2423
2424
2425
2426 d = dev_get_msi_domain(&dev->dev);
2427 if (d)
2428 return d;
2429
2430
2431
2432
2433
2434 d = pci_msi_get_device_domain(dev);
2435 if (d)
2436 return d;
2437
2438 return NULL;
2439}
2440
2441static void pci_set_msi_domain(struct pci_dev *dev)
2442{
2443 struct irq_domain *d;
2444
2445
2446
2447
2448
2449
2450 d = pci_dev_msi_domain(dev);
2451 if (!d)
2452 d = dev_get_msi_domain(&dev->bus->dev);
2453
2454 dev_set_msi_domain(&dev->dev, d);
2455}
2456
2457void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2458{
2459 int ret;
2460
2461 pci_configure_device(dev);
2462
2463 device_initialize(&dev->dev);
2464 dev->dev.release = pci_release_dev;
2465
2466 set_dev_node(&dev->dev, pcibus_to_node(bus));
2467 dev->dev.dma_mask = &dev->dma_mask;
2468 dev->dev.dma_parms = &dev->dma_parms;
2469 dev->dev.coherent_dma_mask = 0xffffffffull;
2470
2471 dma_set_max_seg_size(&dev->dev, 65536);
2472 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2473
2474
2475 pci_fixup_device(pci_fixup_header, dev);
2476
2477 pci_reassigndev_resource_alignment(dev);
2478
2479 dev->state_saved = false;
2480
2481 pci_init_capabilities(dev);
2482
2483
2484
2485
2486
2487 down_write(&pci_bus_sem);
2488 list_add_tail(&dev->bus_list, &bus->devices);
2489 up_write(&pci_bus_sem);
2490
2491 ret = pcibios_add_device(dev);
2492 WARN_ON(ret < 0);
2493
2494
2495 pci_set_msi_domain(dev);
2496
2497
2498 dev->match_driver = false;
2499 ret = device_add(&dev->dev);
2500 WARN_ON(ret < 0);
2501}
2502
2503struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2504{
2505 struct pci_dev *dev;
2506
2507 dev = pci_get_slot(bus, devfn);
2508 if (dev) {
2509 pci_dev_put(dev);
2510 return dev;
2511 }
2512
2513 dev = pci_scan_device(bus, devfn);
2514 if (!dev)
2515 return NULL;
2516
2517 pci_device_add(dev, bus);
2518
2519 return dev;
2520}
2521EXPORT_SYMBOL(pci_scan_single_device);
2522
2523static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2524{
2525 int pos;
2526 u16 cap = 0;
2527 unsigned next_fn;
2528
2529 if (pci_ari_enabled(bus)) {
2530 if (!dev)
2531 return 0;
2532 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2533 if (!pos)
2534 return 0;
2535
2536 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2537 next_fn = PCI_ARI_CAP_NFN(cap);
2538 if (next_fn <= fn)
2539 return 0;
2540
2541 return next_fn;
2542 }
2543
2544
2545 if (!dev || dev->multifunction)
2546 return (fn + 1) % 8;
2547
2548 return 0;
2549}
2550
2551static int only_one_child(struct pci_bus *bus)
2552{
2553 struct pci_dev *bridge = bus->self;
2554
2555
2556
2557
2558
2559 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2560 return 0;
2561
2562
2563
2564
2565
2566
2567 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2568 return 1;
2569
2570 return 0;
2571}
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584int pci_scan_slot(struct pci_bus *bus, int devfn)
2585{
2586 unsigned fn, nr = 0;
2587 struct pci_dev *dev;
2588
2589 if (only_one_child(bus) && (devfn > 0))
2590 return 0;
2591
2592 dev = pci_scan_single_device(bus, devfn);
2593 if (!dev)
2594 return 0;
2595 if (!pci_dev_is_added(dev))
2596 nr++;
2597
2598 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2599 dev = pci_scan_single_device(bus, devfn + fn);
2600 if (dev) {
2601 if (!pci_dev_is_added(dev))
2602 nr++;
2603 dev->multifunction = 1;
2604 }
2605 }
2606
2607
2608 if (bus->self && nr)
2609 pcie_aspm_init_link_state(bus->self);
2610
2611 return nr;
2612}
2613EXPORT_SYMBOL(pci_scan_slot);
2614
2615static int pcie_find_smpss(struct pci_dev *dev, void *data)
2616{
2617 u8 *smpss = data;
2618
2619 if (!pci_is_pcie(dev))
2620 return 0;
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637 if (dev->is_hotplug_bridge &&
2638 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2639 *smpss = 0;
2640
2641 if (*smpss > dev->pcie_mpss)
2642 *smpss = dev->pcie_mpss;
2643
2644 return 0;
2645}
2646
2647static void pcie_write_mps(struct pci_dev *dev, int mps)
2648{
2649 int rc;
2650
2651 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2652 mps = 128 << dev->pcie_mpss;
2653
2654 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2655 dev->bus->self)
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670 mps = min(mps, pcie_get_mps(dev->bus->self));
2671 }
2672
2673 rc = pcie_set_mps(dev, mps);
2674 if (rc)
2675 pci_err(dev, "Failed attempting to set the MPS\n");
2676}
2677
2678static void pcie_write_mrrs(struct pci_dev *dev)
2679{
2680 int rc, mrrs;
2681
2682
2683
2684
2685
2686 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2687 return;
2688
2689
2690
2691
2692
2693
2694
2695 mrrs = pcie_get_mps(dev);
2696
2697
2698
2699
2700
2701
2702
2703 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2704 rc = pcie_set_readrq(dev, mrrs);
2705 if (!rc)
2706 break;
2707
2708 pci_warn(dev, "Failed attempting to set the MRRS\n");
2709 mrrs /= 2;
2710 }
2711
2712 if (mrrs < 128)
2713 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2714}
2715
2716static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2717{
2718 int mps, orig_mps;
2719
2720 if (!pci_is_pcie(dev))
2721 return 0;
2722
2723 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2724 pcie_bus_config == PCIE_BUS_DEFAULT)
2725 return 0;
2726
2727 mps = 128 << *(u8 *)data;
2728 orig_mps = pcie_get_mps(dev);
2729
2730 pcie_write_mps(dev, mps);
2731 pcie_write_mrrs(dev);
2732
2733 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2734 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2735 orig_mps, pcie_get_readrq(dev));
2736
2737 return 0;
2738}
2739
2740
2741
2742
2743
2744
2745void pcie_bus_configure_settings(struct pci_bus *bus)
2746{
2747 u8 smpss = 0;
2748
2749 if (!bus->self)
2750 return;
2751
2752 if (!pci_is_pcie(bus->self))
2753 return;
2754
2755
2756
2757
2758
2759
2760 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2761 smpss = 0;
2762
2763 if (pcie_bus_config == PCIE_BUS_SAFE) {
2764 smpss = bus->self->pcie_mpss;
2765
2766 pcie_find_smpss(bus->self, &smpss);
2767 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2768 }
2769
2770 pcie_bus_configure_set(bus->self, &smpss);
2771 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2772}
2773EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2774
2775
2776
2777
2778
2779void __weak pcibios_fixup_bus(struct pci_bus *bus)
2780{
2781
2782}
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2797 unsigned int available_buses)
2798{
2799 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2800 unsigned int start = bus->busn_res.start;
2801 unsigned int devfn, fn, cmax, max = start;
2802 struct pci_dev *dev;
2803 int nr_devs;
2804
2805 dev_dbg(&bus->dev, "scanning bus\n");
2806
2807
2808 for (devfn = 0; devfn < 256; devfn += 8) {
2809 nr_devs = pci_scan_slot(bus, devfn);
2810
2811
2812
2813
2814
2815
2816 if (jailhouse_paravirt() && nr_devs == 0) {
2817 for (fn = 1; fn < 8; fn++) {
2818 dev = pci_scan_single_device(bus, devfn + fn);
2819 if (dev)
2820 dev->multifunction = 1;
2821 }
2822 }
2823 }
2824
2825
2826 used_buses = pci_iov_bus_range(bus);
2827 max += used_buses;
2828
2829
2830
2831
2832
2833 if (!bus->is_added) {
2834 dev_dbg(&bus->dev, "fixups for bus\n");
2835 pcibios_fixup_bus(bus);
2836 bus->is_added = 1;
2837 }
2838
2839
2840
2841
2842
2843
2844 for_each_pci_bridge(dev, bus) {
2845 if (dev->is_hotplug_bridge)
2846 hotplug_bridges++;
2847 else
2848 normal_bridges++;
2849 }
2850
2851
2852
2853
2854
2855
2856 for_each_pci_bridge(dev, bus) {
2857 cmax = max;
2858 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2859
2860
2861
2862
2863
2864 used_buses++;
2865 if (cmax - max > 1)
2866 used_buses += cmax - max - 1;
2867 }
2868
2869
2870 for_each_pci_bridge(dev, bus) {
2871 unsigned int buses = 0;
2872
2873 if (!hotplug_bridges && normal_bridges == 1) {
2874
2875
2876
2877
2878
2879
2880
2881 buses = available_buses;
2882 } else if (dev->is_hotplug_bridge) {
2883
2884
2885
2886
2887
2888 buses = available_buses / hotplug_bridges;
2889 buses = min(buses, available_buses - used_buses + 1);
2890 }
2891
2892 cmax = max;
2893 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2894
2895 if (max - cmax > 1)
2896 used_buses += max - cmax - 1;
2897 }
2898
2899
2900
2901
2902
2903
2904 if (bus->self && bus->self->is_hotplug_bridge) {
2905 used_buses = max_t(unsigned int, available_buses,
2906 pci_hotplug_bus_size - 1);
2907 if (max - start < used_buses) {
2908 max = start + used_buses;
2909
2910
2911 if (max > bus->busn_res.end)
2912 max = bus->busn_res.end;
2913
2914 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2915 &bus->busn_res, max - start);
2916 }
2917 }
2918
2919
2920
2921
2922
2923
2924
2925
2926 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2927 return max;
2928}
2929
2930
2931
2932
2933
2934
2935
2936
2937unsigned int pci_scan_child_bus(struct pci_bus *bus)
2938{
2939 return pci_scan_child_bus_extend(bus, 0);
2940}
2941EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2942
2943
2944
2945
2946
2947
2948
2949
2950int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2951{
2952 return 0;
2953}
2954
2955void __weak pcibios_add_bus(struct pci_bus *bus)
2956{
2957}
2958
2959void __weak pcibios_remove_bus(struct pci_bus *bus)
2960{
2961}
2962
2963struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2964 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2965{
2966 int error;
2967 struct pci_host_bridge *bridge;
2968
2969 bridge = pci_alloc_host_bridge(0);
2970 if (!bridge)
2971 return NULL;
2972
2973 bridge->dev.parent = parent;
2974
2975 list_splice_init(resources, &bridge->windows);
2976 bridge->sysdata = sysdata;
2977 bridge->busnr = bus;
2978 bridge->ops = ops;
2979
2980 error = pci_register_host_bridge(bridge);
2981 if (error < 0)
2982 goto err_out;
2983
2984 return bridge->bus;
2985
2986err_out:
2987 put_device(&bridge->dev);
2988 return NULL;
2989}
2990EXPORT_SYMBOL_GPL(pci_create_root_bus);
2991
2992int pci_host_probe(struct pci_host_bridge *bridge)
2993{
2994 struct pci_bus *bus, *child;
2995 int ret;
2996
2997 ret = pci_scan_root_bus_bridge(bridge);
2998 if (ret < 0) {
2999 dev_err(bridge->dev.parent, "Scanning root bridge failed");
3000 return ret;
3001 }
3002
3003 bus = bridge->bus;
3004
3005
3006
3007
3008
3009
3010 if (pci_has_flag(PCI_PROBE_ONLY)) {
3011 pci_bus_claim_resources(bus);
3012 } else {
3013 pci_bus_size_bridges(bus);
3014 pci_bus_assign_resources(bus);
3015
3016 list_for_each_entry(child, &bus->children, node)
3017 pcie_bus_configure_settings(child);
3018 }
3019
3020 pci_bus_add_devices(bus);
3021 return 0;
3022}
3023EXPORT_SYMBOL_GPL(pci_host_probe);
3024
3025int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3026{
3027 struct resource *res = &b->busn_res;
3028 struct resource *parent_res, *conflict;
3029
3030 res->start = bus;
3031 res->end = bus_max;
3032 res->flags = IORESOURCE_BUS;
3033
3034 if (!pci_is_root_bus(b))
3035 parent_res = &b->parent->busn_res;
3036 else {
3037 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3038 res->flags |= IORESOURCE_PCI_FIXED;
3039 }
3040
3041 conflict = request_resource_conflict(parent_res, res);
3042
3043 if (conflict)
3044 dev_info(&b->dev,
3045 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3046 res, pci_is_root_bus(b) ? "domain " : "",
3047 parent_res, conflict->name, conflict);
3048
3049 return conflict == NULL;
3050}
3051
3052int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3053{
3054 struct resource *res = &b->busn_res;
3055 struct resource old_res = *res;
3056 resource_size_t size;
3057 int ret;
3058
3059 if (res->start > bus_max)
3060 return -EINVAL;
3061
3062 size = bus_max - res->start + 1;
3063 ret = adjust_resource(res, res->start, size);
3064 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3065 &old_res, ret ? "can not be" : "is", bus_max);
3066
3067 if (!ret && !res->parent)
3068 pci_bus_insert_busn_res(b, res->start, res->end);
3069
3070 return ret;
3071}
3072
3073void pci_bus_release_busn_res(struct pci_bus *b)
3074{
3075 struct resource *res = &b->busn_res;
3076 int ret;
3077
3078 if (!res->flags || !res->parent)
3079 return;
3080
3081 ret = release_resource(res);
3082 dev_info(&b->dev, "busn_res: %pR %s released\n",
3083 res, ret ? "can not be" : "is");
3084}
3085
3086int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3087{
3088 struct resource_entry *window;
3089 bool found = false;
3090 struct pci_bus *b;
3091 int max, bus, ret;
3092
3093 if (!bridge)
3094 return -EINVAL;
3095
3096 resource_list_for_each_entry(window, &bridge->windows)
3097 if (window->res->flags & IORESOURCE_BUS) {
3098 bridge->busnr = window->res->start;
3099 found = true;
3100 break;
3101 }
3102
3103 ret = pci_register_host_bridge(bridge);
3104 if (ret < 0)
3105 return ret;
3106
3107 b = bridge->bus;
3108 bus = bridge->busnr;
3109
3110 if (!found) {
3111 dev_info(&b->dev,
3112 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3113 bus);
3114 pci_bus_insert_busn_res(b, bus, 255);
3115 }
3116
3117 max = pci_scan_child_bus(b);
3118
3119 if (!found)
3120 pci_bus_update_busn_res_end(b, max);
3121
3122 return 0;
3123}
3124EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3125
3126struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3127 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3128{
3129 struct resource_entry *window;
3130 bool found = false;
3131 struct pci_bus *b;
3132 int max;
3133
3134 resource_list_for_each_entry(window, resources)
3135 if (window->res->flags & IORESOURCE_BUS) {
3136 found = true;
3137 break;
3138 }
3139
3140 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3141 if (!b)
3142 return NULL;
3143
3144 if (!found) {
3145 dev_info(&b->dev,
3146 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3147 bus);
3148 pci_bus_insert_busn_res(b, bus, 255);
3149 }
3150
3151 max = pci_scan_child_bus(b);
3152
3153 if (!found)
3154 pci_bus_update_busn_res_end(b, max);
3155
3156 return b;
3157}
3158EXPORT_SYMBOL(pci_scan_root_bus);
3159
3160struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3161 void *sysdata)
3162{
3163 LIST_HEAD(resources);
3164 struct pci_bus *b;
3165
3166 pci_add_resource(&resources, &ioport_resource);
3167 pci_add_resource(&resources, &iomem_resource);
3168 pci_add_resource(&resources, &busn_resource);
3169 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3170 if (b) {
3171 pci_scan_child_bus(b);
3172 } else {
3173 pci_free_resource_list(&resources);
3174 }
3175 return b;
3176}
3177EXPORT_SYMBOL(pci_scan_bus);
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3191{
3192 unsigned int max;
3193 struct pci_bus *bus = bridge->subordinate;
3194
3195 max = pci_scan_child_bus(bus);
3196
3197 pci_assign_unassigned_bridge_resources(bridge);
3198
3199 pci_bus_add_devices(bus);
3200
3201 return max;
3202}
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213unsigned int pci_rescan_bus(struct pci_bus *bus)
3214{
3215 unsigned int max;
3216
3217 max = pci_scan_child_bus(bus);
3218 pci_assign_unassigned_bus_resources(bus);
3219 pci_bus_add_devices(bus);
3220
3221 return max;
3222}
3223EXPORT_SYMBOL_GPL(pci_rescan_bus);
3224
3225
3226
3227
3228
3229static DEFINE_MUTEX(pci_rescan_remove_lock);
3230
3231void pci_lock_rescan_remove(void)
3232{
3233 mutex_lock(&pci_rescan_remove_lock);
3234}
3235EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3236
3237void pci_unlock_rescan_remove(void)
3238{
3239 mutex_unlock(&pci_rescan_remove_lock);
3240}
3241EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3242
3243static int __init pci_sort_bf_cmp(const struct device *d_a,
3244 const struct device *d_b)
3245{
3246 const struct pci_dev *a = to_pci_dev(d_a);
3247 const struct pci_dev *b = to_pci_dev(d_b);
3248
3249 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3250 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3251
3252 if (a->bus->number < b->bus->number) return -1;
3253 else if (a->bus->number > b->bus->number) return 1;
3254
3255 if (a->devfn < b->devfn) return -1;
3256 else if (a->devfn > b->devfn) return 1;
3257
3258 return 0;
3259}
3260
3261void __init pci_sort_breadthfirst(void)
3262{
3263 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3264}
3265
3266int pci_hp_add_bridge(struct pci_dev *dev)
3267{
3268 struct pci_bus *parent = dev->bus;
3269 int busnr, start = parent->busn_res.start;
3270 unsigned int available_buses = 0;
3271 int end = parent->busn_res.end;
3272
3273 for (busnr = start; busnr <= end; busnr++) {
3274 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3275 break;
3276 }
3277 if (busnr-- > end) {
3278 pci_err(dev, "No bus number available for hot-added bridge\n");
3279 return -1;
3280 }
3281
3282
3283 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3284
3285
3286
3287
3288
3289 available_buses = end - busnr;
3290
3291
3292 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3293
3294 if (!dev->subordinate)
3295 return -1;
3296
3297 return 0;
3298}
3299EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
3300