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12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/io.h>
15#include <linux/slab.h>
16#include <linux/err.h>
17#include <linux/list.h>
18#include <linux/interrupt.h>
19
20#include <linux/irqchip/chained_irq.h>
21
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
26
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/pinctrl/pinconf-generic.h>
30
31#include <linux/platform_data/pinctrl-single.h>
32
33#include "core.h"
34#include "devicetree.h"
35#include "pinconf.h"
36#include "pinmux.h"
37
38#define DRIVER_NAME "pinctrl-single"
39#define PCS_OFF_DISABLED ~0U
40
41
42
43
44
45
46
47struct pcs_func_vals {
48 void __iomem *reg;
49 unsigned val;
50 unsigned mask;
51};
52
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61
62struct pcs_conf_vals {
63 enum pin_config_param param;
64 unsigned val;
65 unsigned enable;
66 unsigned disable;
67 unsigned mask;
68};
69
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73
74
75struct pcs_conf_type {
76 const char *name;
77 enum pin_config_param param;
78};
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90
91struct pcs_function {
92 const char *name;
93 struct pcs_func_vals *vals;
94 unsigned nvals;
95 const char **pgnames;
96 int npgnames;
97 struct pcs_conf_vals *conf;
98 int nconfs;
99 struct list_head node;
100};
101
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108
109struct pcs_gpiofunc_range {
110 unsigned offset;
111 unsigned npins;
112 unsigned gpiofunc;
113 struct list_head node;
114};
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124
125struct pcs_data {
126 struct pinctrl_pin_desc *pa;
127 int cur;
128};
129
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137
138struct pcs_soc_data {
139 unsigned flags;
140 int irq;
141 unsigned irq_enable_mask;
142 unsigned irq_status_mask;
143 void (*rearm)(void);
144};
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175
176struct pcs_device {
177 struct resource *res;
178 void __iomem *base;
179 void *saved_vals;
180 unsigned size;
181 struct device *dev;
182 struct device_node *np;
183 struct pinctrl_dev *pctl;
184 unsigned flags;
185#define PCS_CONTEXT_LOSS_OFF (1 << 3)
186#define PCS_QUIRK_SHARED_IRQ (1 << 2)
187#define PCS_FEAT_IRQ (1 << 1)
188#define PCS_FEAT_PINCONF (1 << 0)
189 struct property *missing_nr_pinctrl_cells;
190 struct pcs_soc_data socdata;
191 raw_spinlock_t lock;
192 struct mutex mutex;
193 unsigned width;
194 unsigned fmask;
195 unsigned fshift;
196 unsigned foff;
197 unsigned fmax;
198 bool bits_per_mux;
199 unsigned bits_per_pin;
200 struct pcs_data pins;
201 struct list_head gpiofuncs;
202 struct list_head irqs;
203 struct irq_chip chip;
204 struct irq_domain *domain;
205 struct pinctrl_desc desc;
206 unsigned (*read)(void __iomem *reg);
207 void (*write)(unsigned val, void __iomem *reg);
208};
209
210#define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
211#define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
212#define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
213
214static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
215 unsigned long *config);
216static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
217 unsigned long *configs, unsigned num_configs);
218
219static enum pin_config_param pcs_bias[] = {
220 PIN_CONFIG_BIAS_PULL_DOWN,
221 PIN_CONFIG_BIAS_PULL_UP,
222};
223
224
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227
228
229static struct lock_class_key pcs_lock_class;
230
231
232static struct lock_class_key pcs_request_class;
233
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242
243static unsigned __maybe_unused pcs_readb(void __iomem *reg)
244{
245 return readb(reg);
246}
247
248static unsigned __maybe_unused pcs_readw(void __iomem *reg)
249{
250 return readw(reg);
251}
252
253static unsigned __maybe_unused pcs_readl(void __iomem *reg)
254{
255 return readl(reg);
256}
257
258static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
259{
260 writeb(val, reg);
261}
262
263static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
264{
265 writew(val, reg);
266}
267
268static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
269{
270 writel(val, reg);
271}
272
273static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
274 unsigned int pin)
275{
276 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
277
278 if (pcs->bits_per_mux) {
279 unsigned int pin_offset_bytes;
280
281 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
282 return (pin_offset_bytes / mux_bytes) * mux_bytes;
283 }
284
285 return pin * mux_bytes;
286}
287
288static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
289 unsigned int pin)
290{
291 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
292}
293
294static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
295 struct seq_file *s,
296 unsigned pin)
297{
298 struct pcs_device *pcs;
299 unsigned int val;
300 unsigned long offset;
301 size_t pa;
302
303 pcs = pinctrl_dev_get_drvdata(pctldev);
304
305 offset = pcs_pin_reg_offset_get(pcs, pin);
306 val = pcs->read(pcs->base + offset);
307
308 if (pcs->bits_per_mux)
309 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
310
311 pa = pcs->res->start + offset;
312
313 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
314}
315
316static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
317 struct pinctrl_map *map, unsigned num_maps)
318{
319 struct pcs_device *pcs;
320
321 pcs = pinctrl_dev_get_drvdata(pctldev);
322 devm_kfree(pcs->dev, map);
323}
324
325static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
326 struct device_node *np_config,
327 struct pinctrl_map **map, unsigned *num_maps);
328
329static const struct pinctrl_ops pcs_pinctrl_ops = {
330 .get_groups_count = pinctrl_generic_get_group_count,
331 .get_group_name = pinctrl_generic_get_group_name,
332 .get_group_pins = pinctrl_generic_get_group_pins,
333 .pin_dbg_show = pcs_pin_dbg_show,
334 .dt_node_to_map = pcs_dt_node_to_map,
335 .dt_free_map = pcs_dt_free_map,
336};
337
338static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
339 struct pcs_function **func)
340{
341 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
342 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
343 const struct pinctrl_setting_mux *setting;
344 struct function_desc *function;
345 unsigned fselector;
346
347
348 setting = pdesc->mux_setting;
349 if (!setting)
350 return -ENOTSUPP;
351 fselector = setting->func;
352 function = pinmux_generic_get_function(pctldev, fselector);
353 *func = function->data;
354 if (!(*func)) {
355 dev_err(pcs->dev, "%s could not find function%i\n",
356 __func__, fselector);
357 return -ENOTSUPP;
358 }
359 return 0;
360}
361
362static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
363 unsigned group)
364{
365 struct pcs_device *pcs;
366 struct function_desc *function;
367 struct pcs_function *func;
368 int i;
369
370 pcs = pinctrl_dev_get_drvdata(pctldev);
371
372 if (!pcs->fmask)
373 return 0;
374 function = pinmux_generic_get_function(pctldev, fselector);
375 func = function->data;
376 if (!func)
377 return -EINVAL;
378
379 dev_dbg(pcs->dev, "enabling %s function%i\n",
380 func->name, fselector);
381
382 for (i = 0; i < func->nvals; i++) {
383 struct pcs_func_vals *vals;
384 unsigned long flags;
385 unsigned val, mask;
386
387 vals = &func->vals[i];
388 raw_spin_lock_irqsave(&pcs->lock, flags);
389 val = pcs->read(vals->reg);
390
391 if (pcs->bits_per_mux)
392 mask = vals->mask;
393 else
394 mask = pcs->fmask;
395
396 val &= ~mask;
397 val |= (vals->val & mask);
398 pcs->write(val, vals->reg);
399 raw_spin_unlock_irqrestore(&pcs->lock, flags);
400 }
401
402 return 0;
403}
404
405static int pcs_request_gpio(struct pinctrl_dev *pctldev,
406 struct pinctrl_gpio_range *range, unsigned pin)
407{
408 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
409 struct pcs_gpiofunc_range *frange = NULL;
410 struct list_head *pos, *tmp;
411 unsigned data;
412
413
414 if (!pcs->fmask)
415 return -ENOTSUPP;
416
417 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
418 u32 offset;
419
420 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
421 if (pin >= frange->offset + frange->npins
422 || pin < frange->offset)
423 continue;
424
425 offset = pcs_pin_reg_offset_get(pcs, pin);
426
427 if (pcs->bits_per_mux) {
428 int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
429
430 data = pcs->read(pcs->base + offset);
431 data &= ~(pcs->fmask << pin_shift);
432 data |= frange->gpiofunc << pin_shift;
433 pcs->write(data, pcs->base + offset);
434 } else {
435 data = pcs->read(pcs->base + offset);
436 data &= ~pcs->fmask;
437 data |= frange->gpiofunc;
438 pcs->write(data, pcs->base + offset);
439 }
440 break;
441 }
442 return 0;
443}
444
445static const struct pinmux_ops pcs_pinmux_ops = {
446 .get_functions_count = pinmux_generic_get_function_count,
447 .get_function_name = pinmux_generic_get_function_name,
448 .get_function_groups = pinmux_generic_get_function_groups,
449 .set_mux = pcs_set_mux,
450 .gpio_request_enable = pcs_request_gpio,
451};
452
453
454static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
455{
456 unsigned long config;
457 int i;
458 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
459 config = pinconf_to_config_packed(pcs_bias[i], 0);
460 pcs_pinconf_set(pctldev, pin, &config, 1);
461 }
462}
463
464
465
466
467
468static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
469{
470 unsigned long config;
471 int i;
472
473 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
474 config = pinconf_to_config_packed(pcs_bias[i], 0);
475 if (!pcs_pinconf_get(pctldev, pin, &config))
476 goto out;
477 }
478 return true;
479out:
480 return false;
481}
482
483static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
484 unsigned pin, unsigned long *config)
485{
486 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
487 struct pcs_function *func;
488 enum pin_config_param param;
489 unsigned offset = 0, data = 0, i, j, ret;
490
491 ret = pcs_get_function(pctldev, pin, &func);
492 if (ret)
493 return ret;
494
495 for (i = 0; i < func->nconfs; i++) {
496 param = pinconf_to_config_param(*config);
497 if (param == PIN_CONFIG_BIAS_DISABLE) {
498 if (pcs_pinconf_bias_disable(pctldev, pin)) {
499 *config = 0;
500 return 0;
501 } else {
502 return -ENOTSUPP;
503 }
504 } else if (param != func->conf[i].param) {
505 continue;
506 }
507
508 offset = pin * (pcs->width / BITS_PER_BYTE);
509 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
510 switch (func->conf[i].param) {
511
512 case PIN_CONFIG_BIAS_PULL_DOWN:
513 case PIN_CONFIG_BIAS_PULL_UP:
514 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
515 if ((data != func->conf[i].enable) ||
516 (data == func->conf[i].disable))
517 return -ENOTSUPP;
518 *config = 0;
519 break;
520
521 case PIN_CONFIG_INPUT_SCHMITT:
522 for (j = 0; j < func->nconfs; j++) {
523 switch (func->conf[j].param) {
524 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
525 if (data != func->conf[j].enable)
526 return -ENOTSUPP;
527 break;
528 default:
529 break;
530 }
531 }
532 *config = data;
533 break;
534 case PIN_CONFIG_DRIVE_STRENGTH:
535 case PIN_CONFIG_SLEW_RATE:
536 case PIN_CONFIG_MODE_LOW_POWER:
537 default:
538 *config = data;
539 break;
540 }
541 return 0;
542 }
543 return -ENOTSUPP;
544}
545
546static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
547 unsigned pin, unsigned long *configs,
548 unsigned num_configs)
549{
550 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
551 struct pcs_function *func;
552 unsigned offset = 0, shift = 0, i, data, ret;
553 u32 arg;
554 int j;
555
556 ret = pcs_get_function(pctldev, pin, &func);
557 if (ret)
558 return ret;
559
560 for (j = 0; j < num_configs; j++) {
561 for (i = 0; i < func->nconfs; i++) {
562 if (pinconf_to_config_param(configs[j])
563 != func->conf[i].param)
564 continue;
565
566 offset = pin * (pcs->width / BITS_PER_BYTE);
567 data = pcs->read(pcs->base + offset);
568 arg = pinconf_to_config_argument(configs[j]);
569 switch (func->conf[i].param) {
570
571 case PIN_CONFIG_INPUT_SCHMITT:
572 case PIN_CONFIG_DRIVE_STRENGTH:
573 case PIN_CONFIG_SLEW_RATE:
574 case PIN_CONFIG_MODE_LOW_POWER:
575 shift = ffs(func->conf[i].mask) - 1;
576 data &= ~func->conf[i].mask;
577 data |= (arg << shift) & func->conf[i].mask;
578 break;
579
580 case PIN_CONFIG_BIAS_DISABLE:
581 pcs_pinconf_clear_bias(pctldev, pin);
582 break;
583 case PIN_CONFIG_BIAS_PULL_DOWN:
584 case PIN_CONFIG_BIAS_PULL_UP:
585 if (arg)
586 pcs_pinconf_clear_bias(pctldev, pin);
587 fallthrough;
588 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
589 data &= ~func->conf[i].mask;
590 if (arg)
591 data |= func->conf[i].enable;
592 else
593 data |= func->conf[i].disable;
594 break;
595 default:
596 return -ENOTSUPP;
597 }
598 pcs->write(data, pcs->base + offset);
599
600 break;
601 }
602 if (i >= func->nconfs)
603 return -ENOTSUPP;
604 }
605
606 return 0;
607}
608
609static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
610 unsigned group, unsigned long *config)
611{
612 const unsigned *pins;
613 unsigned npins, old = 0;
614 int i, ret;
615
616 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
617 if (ret)
618 return ret;
619 for (i = 0; i < npins; i++) {
620 if (pcs_pinconf_get(pctldev, pins[i], config))
621 return -ENOTSUPP;
622
623 if (i && (old != *config))
624 return -ENOTSUPP;
625 old = *config;
626 }
627 return 0;
628}
629
630static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
631 unsigned group, unsigned long *configs,
632 unsigned num_configs)
633{
634 const unsigned *pins;
635 unsigned npins;
636 int i, ret;
637
638 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
639 if (ret)
640 return ret;
641 for (i = 0; i < npins; i++) {
642 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
643 return -ENOTSUPP;
644 }
645 return 0;
646}
647
648static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
649 struct seq_file *s, unsigned pin)
650{
651}
652
653static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
654 struct seq_file *s, unsigned selector)
655{
656}
657
658static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
659 struct seq_file *s,
660 unsigned long config)
661{
662 pinconf_generic_dump_config(pctldev, s, config);
663}
664
665static const struct pinconf_ops pcs_pinconf_ops = {
666 .pin_config_get = pcs_pinconf_get,
667 .pin_config_set = pcs_pinconf_set,
668 .pin_config_group_get = pcs_pinconf_group_get,
669 .pin_config_group_set = pcs_pinconf_group_set,
670 .pin_config_dbg_show = pcs_pinconf_dbg_show,
671 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
672 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
673 .is_generic = true,
674};
675
676
677
678
679
680
681static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
682{
683 struct pcs_soc_data *pcs_soc = &pcs->socdata;
684 struct pinctrl_pin_desc *pin;
685 int i;
686
687 i = pcs->pins.cur;
688 if (i >= pcs->desc.npins) {
689 dev_err(pcs->dev, "too many pins, max %i\n",
690 pcs->desc.npins);
691 return -ENOMEM;
692 }
693
694 if (pcs_soc->irq_enable_mask) {
695 unsigned val;
696
697 val = pcs->read(pcs->base + offset);
698 if (val & pcs_soc->irq_enable_mask) {
699 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
700 (unsigned long)pcs->res->start + offset, val);
701 val &= ~pcs_soc->irq_enable_mask;
702 pcs->write(val, pcs->base + offset);
703 }
704 }
705
706 pin = &pcs->pins.pa[i];
707 pin->number = i;
708 pcs->pins.cur++;
709
710 return i;
711}
712
713
714
715
716
717
718
719
720
721
722static int pcs_allocate_pin_table(struct pcs_device *pcs)
723{
724 int mux_bytes, nr_pins, i;
725
726 mux_bytes = pcs->width / BITS_PER_BYTE;
727
728 if (pcs->bits_per_mux) {
729 pcs->bits_per_pin = fls(pcs->fmask);
730 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
731 } else {
732 nr_pins = pcs->size / mux_bytes;
733 }
734
735 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
736 pcs->pins.pa = devm_kcalloc(pcs->dev,
737 nr_pins, sizeof(*pcs->pins.pa),
738 GFP_KERNEL);
739 if (!pcs->pins.pa)
740 return -ENOMEM;
741
742 pcs->desc.pins = pcs->pins.pa;
743 pcs->desc.npins = nr_pins;
744
745 for (i = 0; i < pcs->desc.npins; i++) {
746 unsigned offset;
747 int res;
748
749 offset = pcs_pin_reg_offset_get(pcs, i);
750 res = pcs_add_pin(pcs, offset);
751 if (res < 0) {
752 dev_err(pcs->dev, "error adding pins: %i\n", res);
753 return res;
754 }
755 }
756
757 return 0;
758}
759
760
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765
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769
770
771
772static int pcs_add_function(struct pcs_device *pcs,
773 struct pcs_function **fcn,
774 const char *name,
775 struct pcs_func_vals *vals,
776 unsigned int nvals,
777 const char **pgnames,
778 unsigned int npgnames)
779{
780 struct pcs_function *function;
781 int selector;
782
783 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
784 if (!function)
785 return -ENOMEM;
786
787 function->vals = vals;
788 function->nvals = nvals;
789 function->name = name;
790
791 selector = pinmux_generic_add_function(pcs->pctl, name,
792 pgnames, npgnames,
793 function);
794 if (selector < 0) {
795 devm_kfree(pcs->dev, function);
796 *fcn = NULL;
797 } else {
798 *fcn = function;
799 }
800
801 return selector;
802}
803
804
805
806
807
808
809
810
811static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
812{
813 unsigned index;
814
815 if (offset >= pcs->size) {
816 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
817 offset, pcs->size);
818 return -EINVAL;
819 }
820
821 if (pcs->bits_per_mux)
822 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
823 else
824 index = offset / (pcs->width / BITS_PER_BYTE);
825
826 return index;
827}
828
829
830
831
832
833
834static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
835{
836 int ret = -EINVAL;
837
838 if (data == enable)
839 ret = 1;
840 else if (data == disable)
841 ret = 0;
842 return ret;
843}
844
845static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
846 unsigned value, unsigned enable, unsigned disable,
847 unsigned mask)
848{
849 (*conf)->param = param;
850 (*conf)->val = value;
851 (*conf)->enable = enable;
852 (*conf)->disable = disable;
853 (*conf)->mask = mask;
854 (*conf)++;
855}
856
857static void add_setting(unsigned long **setting, enum pin_config_param param,
858 unsigned arg)
859{
860 **setting = pinconf_to_config_packed(param, arg);
861 (*setting)++;
862}
863
864
865static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
866 const char *name, enum pin_config_param param,
867 struct pcs_conf_vals **conf, unsigned long **settings)
868{
869 unsigned value[2], shift;
870 int ret;
871
872 ret = of_property_read_u32_array(np, name, value, 2);
873 if (ret)
874 return;
875
876 value[0] &= value[1];
877 shift = ffs(value[1]) - 1;
878
879 add_config(conf, param, value[0], 0, 0, value[1]);
880 add_setting(settings, param, value[0] >> shift);
881}
882
883
884static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
885 const char *name, enum pin_config_param param,
886 struct pcs_conf_vals **conf, unsigned long **settings)
887{
888 unsigned value[4];
889 int ret;
890
891
892 ret = of_property_read_u32_array(np, name, value, 4);
893 if (ret)
894 return;
895 if (!value[3]) {
896 dev_err(pcs->dev, "mask field of the property can't be 0\n");
897 return;
898 }
899 value[0] &= value[3];
900 value[1] &= value[3];
901 value[2] &= value[3];
902 ret = pcs_config_match(value[0], value[1], value[2]);
903 if (ret < 0)
904 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
905 add_config(conf, param, value[0], value[1], value[2], value[3]);
906 add_setting(settings, param, ret);
907}
908
909static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
910 struct pcs_function *func,
911 struct pinctrl_map **map)
912
913{
914 struct pinctrl_map *m = *map;
915 int i = 0, nconfs = 0;
916 unsigned long *settings = NULL, *s = NULL;
917 struct pcs_conf_vals *conf = NULL;
918 static const struct pcs_conf_type prop2[] = {
919 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
920 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
921 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
922 { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, },
923 };
924 static const struct pcs_conf_type prop4[] = {
925 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
926 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
927 { "pinctrl-single,input-schmitt-enable",
928 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
929 };
930
931
932 if (!PCS_HAS_PINCONF)
933 return -ENOTSUPP;
934
935
936 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
937 if (of_find_property(np, prop2[i].name, NULL))
938 nconfs++;
939 }
940 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
941 if (of_find_property(np, prop4[i].name, NULL))
942 nconfs++;
943 }
944 if (!nconfs)
945 return -ENOTSUPP;
946
947 func->conf = devm_kcalloc(pcs->dev,
948 nconfs, sizeof(struct pcs_conf_vals),
949 GFP_KERNEL);
950 if (!func->conf)
951 return -ENOMEM;
952 func->nconfs = nconfs;
953 conf = &(func->conf[0]);
954 m++;
955 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
956 GFP_KERNEL);
957 if (!settings)
958 return -ENOMEM;
959 s = &settings[0];
960
961 for (i = 0; i < ARRAY_SIZE(prop2); i++)
962 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
963 &conf, &s);
964 for (i = 0; i < ARRAY_SIZE(prop4); i++)
965 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
966 &conf, &s);
967 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
968 m->data.configs.group_or_pin = np->name;
969 m->data.configs.configs = settings;
970 m->data.configs.num_configs = nconfs;
971 return 0;
972}
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
994 struct device_node *np,
995 struct pinctrl_map **map,
996 unsigned *num_maps,
997 const char **pgnames)
998{
999 const char *name = "pinctrl-single,pins";
1000 struct pcs_func_vals *vals;
1001 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1002 struct pcs_function *function = NULL;
1003
1004 rows = pinctrl_count_index_with_args(np, name);
1005 if (rows <= 0) {
1006 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1007 return -EINVAL;
1008 }
1009
1010 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1011 if (!vals)
1012 return -ENOMEM;
1013
1014 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1015 if (!pins)
1016 goto free_vals;
1017
1018 for (i = 0; i < rows; i++) {
1019 struct of_phandle_args pinctrl_spec;
1020 unsigned int offset;
1021 int pin;
1022
1023 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1024 if (res)
1025 return res;
1026
1027 if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1028 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1029 pinctrl_spec.args_count);
1030 break;
1031 }
1032
1033 offset = pinctrl_spec.args[0];
1034 vals[found].reg = pcs->base + offset;
1035
1036 switch (pinctrl_spec.args_count) {
1037 case 2:
1038 vals[found].val = pinctrl_spec.args[1];
1039 break;
1040 case 3:
1041 vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1042 break;
1043 }
1044
1045 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1046 pinctrl_spec.np, offset, vals[found].val);
1047
1048 pin = pcs_get_pin_by_offset(pcs, offset);
1049 if (pin < 0) {
1050 dev_err(pcs->dev,
1051 "could not add functions for %pOFn %ux\n",
1052 np, offset);
1053 break;
1054 }
1055 pins[found++] = pin;
1056 }
1057
1058 pgnames[0] = np->name;
1059 mutex_lock(&pcs->mutex);
1060 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1061 pgnames, 1);
1062 if (fsel < 0) {
1063 res = fsel;
1064 goto free_pins;
1065 }
1066
1067 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1068 if (gsel < 0) {
1069 res = gsel;
1070 goto free_function;
1071 }
1072
1073 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1074 (*map)->data.mux.group = np->name;
1075 (*map)->data.mux.function = np->name;
1076
1077 if (PCS_HAS_PINCONF && function) {
1078 res = pcs_parse_pinconf(pcs, np, function, map);
1079 if (res == 0)
1080 *num_maps = 2;
1081 else if (res == -ENOTSUPP)
1082 *num_maps = 1;
1083 else
1084 goto free_pingroups;
1085 } else {
1086 *num_maps = 1;
1087 }
1088 mutex_unlock(&pcs->mutex);
1089
1090 return 0;
1091
1092free_pingroups:
1093 pinctrl_generic_remove_group(pcs->pctl, gsel);
1094 *num_maps = 1;
1095free_function:
1096 pinmux_generic_remove_function(pcs->pctl, fsel);
1097free_pins:
1098 mutex_unlock(&pcs->mutex);
1099 devm_kfree(pcs->dev, pins);
1100
1101free_vals:
1102 devm_kfree(pcs->dev, vals);
1103
1104 return res;
1105}
1106
1107static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1108 struct device_node *np,
1109 struct pinctrl_map **map,
1110 unsigned *num_maps,
1111 const char **pgnames)
1112{
1113 const char *name = "pinctrl-single,bits";
1114 struct pcs_func_vals *vals;
1115 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1116 int npins_in_row;
1117 struct pcs_function *function = NULL;
1118
1119 rows = pinctrl_count_index_with_args(np, name);
1120 if (rows <= 0) {
1121 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1122 return -EINVAL;
1123 }
1124
1125 npins_in_row = pcs->width / pcs->bits_per_pin;
1126
1127 vals = devm_kzalloc(pcs->dev,
1128 array3_size(rows, npins_in_row, sizeof(*vals)),
1129 GFP_KERNEL);
1130 if (!vals)
1131 return -ENOMEM;
1132
1133 pins = devm_kzalloc(pcs->dev,
1134 array3_size(rows, npins_in_row, sizeof(*pins)),
1135 GFP_KERNEL);
1136 if (!pins)
1137 goto free_vals;
1138
1139 for (i = 0; i < rows; i++) {
1140 struct of_phandle_args pinctrl_spec;
1141 unsigned offset, val;
1142 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1143 unsigned pin_num_from_lsb;
1144 int pin;
1145
1146 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1147 if (res)
1148 return res;
1149
1150 if (pinctrl_spec.args_count < 3) {
1151 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1152 pinctrl_spec.args_count);
1153 break;
1154 }
1155
1156
1157 offset = pinctrl_spec.args[0];
1158 val = pinctrl_spec.args[1];
1159 mask = pinctrl_spec.args[2];
1160
1161 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1162 pinctrl_spec.np, offset, val, mask);
1163
1164
1165 while (mask) {
1166 bit_pos = __ffs(mask);
1167 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1168 mask_pos = ((pcs->fmask) << bit_pos);
1169 val_pos = val & mask_pos;
1170 submask = mask & mask_pos;
1171
1172 if ((mask & mask_pos) == 0) {
1173 dev_err(pcs->dev,
1174 "Invalid mask for %pOFn at 0x%x\n",
1175 np, offset);
1176 break;
1177 }
1178
1179 mask &= ~mask_pos;
1180
1181 if (submask != mask_pos) {
1182 dev_warn(pcs->dev,
1183 "Invalid submask 0x%x for %pOFn at 0x%x\n",
1184 submask, np, offset);
1185 continue;
1186 }
1187
1188 vals[found].mask = submask;
1189 vals[found].reg = pcs->base + offset;
1190 vals[found].val = val_pos;
1191
1192 pin = pcs_get_pin_by_offset(pcs, offset);
1193 if (pin < 0) {
1194 dev_err(pcs->dev,
1195 "could not add functions for %pOFn %ux\n",
1196 np, offset);
1197 break;
1198 }
1199 pins[found++] = pin + pin_num_from_lsb;
1200 }
1201 }
1202
1203 pgnames[0] = np->name;
1204 mutex_lock(&pcs->mutex);
1205 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1206 pgnames, 1);
1207 if (fsel < 0) {
1208 res = fsel;
1209 goto free_pins;
1210 }
1211
1212 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1213 if (gsel < 0) {
1214 res = gsel;
1215 goto free_function;
1216 }
1217
1218 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1219 (*map)->data.mux.group = np->name;
1220 (*map)->data.mux.function = np->name;
1221
1222 if (PCS_HAS_PINCONF) {
1223 dev_err(pcs->dev, "pinconf not supported\n");
1224 goto free_pingroups;
1225 }
1226
1227 *num_maps = 1;
1228 mutex_unlock(&pcs->mutex);
1229
1230 return 0;
1231
1232free_pingroups:
1233 pinctrl_generic_remove_group(pcs->pctl, gsel);
1234 *num_maps = 1;
1235free_function:
1236 pinmux_generic_remove_function(pcs->pctl, fsel);
1237free_pins:
1238 mutex_unlock(&pcs->mutex);
1239 devm_kfree(pcs->dev, pins);
1240
1241free_vals:
1242 devm_kfree(pcs->dev, vals);
1243
1244 return res;
1245}
1246
1247
1248
1249
1250
1251
1252
1253static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1254 struct device_node *np_config,
1255 struct pinctrl_map **map, unsigned *num_maps)
1256{
1257 struct pcs_device *pcs;
1258 const char **pgnames;
1259 int ret;
1260
1261 pcs = pinctrl_dev_get_drvdata(pctldev);
1262
1263
1264 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1265 if (!*map)
1266 return -ENOMEM;
1267
1268 *num_maps = 0;
1269
1270 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1271 if (!pgnames) {
1272 ret = -ENOMEM;
1273 goto free_map;
1274 }
1275
1276 if (pcs->bits_per_mux) {
1277 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1278 num_maps, pgnames);
1279 if (ret < 0) {
1280 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1281 np_config);
1282 goto free_pgnames;
1283 }
1284 } else {
1285 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1286 num_maps, pgnames);
1287 if (ret < 0) {
1288 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1289 np_config);
1290 goto free_pgnames;
1291 }
1292 }
1293
1294 return 0;
1295
1296free_pgnames:
1297 devm_kfree(pcs->dev, pgnames);
1298free_map:
1299 devm_kfree(pcs->dev, *map);
1300
1301 return ret;
1302}
1303
1304
1305
1306
1307
1308static void pcs_irq_free(struct pcs_device *pcs)
1309{
1310 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1311
1312 if (pcs_soc->irq < 0)
1313 return;
1314
1315 if (pcs->domain)
1316 irq_domain_remove(pcs->domain);
1317
1318 if (PCS_QUIRK_HAS_SHARED_IRQ)
1319 free_irq(pcs_soc->irq, pcs_soc);
1320 else
1321 irq_set_chained_handler(pcs_soc->irq, NULL);
1322}
1323
1324
1325
1326
1327
1328static void pcs_free_resources(struct pcs_device *pcs)
1329{
1330 pcs_irq_free(pcs);
1331 pinctrl_unregister(pcs->pctl);
1332
1333#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1334 if (pcs->missing_nr_pinctrl_cells)
1335 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1336#endif
1337}
1338
1339static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1340{
1341 const char *propname = "pinctrl-single,gpio-range";
1342 const char *cellname = "#pinctrl-single,gpio-range-cells";
1343 struct of_phandle_args gpiospec;
1344 struct pcs_gpiofunc_range *range;
1345 int ret, i;
1346
1347 for (i = 0; ; i++) {
1348 ret = of_parse_phandle_with_args(node, propname, cellname,
1349 i, &gpiospec);
1350
1351 if (ret) {
1352 ret = 0;
1353 break;
1354 }
1355 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1356 if (!range) {
1357 ret = -ENOMEM;
1358 break;
1359 }
1360 range->offset = gpiospec.args[0];
1361 range->npins = gpiospec.args[1];
1362 range->gpiofunc = gpiospec.args[2];
1363 mutex_lock(&pcs->mutex);
1364 list_add_tail(&range->node, &pcs->gpiofuncs);
1365 mutex_unlock(&pcs->mutex);
1366 }
1367 return ret;
1368}
1369
1370
1371
1372
1373
1374
1375
1376
1377struct pcs_interrupt {
1378 void __iomem *reg;
1379 irq_hw_number_t hwirq;
1380 unsigned int irq;
1381 struct list_head node;
1382};
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1394 int irq, const bool enable)
1395{
1396 struct pcs_device *pcs;
1397 struct list_head *pos;
1398 unsigned mask;
1399
1400 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1401 list_for_each(pos, &pcs->irqs) {
1402 struct pcs_interrupt *pcswi;
1403 unsigned soc_mask;
1404
1405 pcswi = list_entry(pos, struct pcs_interrupt, node);
1406 if (irq != pcswi->irq)
1407 continue;
1408
1409 soc_mask = pcs_soc->irq_enable_mask;
1410 raw_spin_lock(&pcs->lock);
1411 mask = pcs->read(pcswi->reg);
1412 if (enable)
1413 mask |= soc_mask;
1414 else
1415 mask &= ~soc_mask;
1416 pcs->write(mask, pcswi->reg);
1417
1418
1419 mask = pcs->read(pcswi->reg);
1420 raw_spin_unlock(&pcs->lock);
1421 }
1422
1423 if (pcs_soc->rearm)
1424 pcs_soc->rearm();
1425}
1426
1427
1428
1429
1430
1431static void pcs_irq_mask(struct irq_data *d)
1432{
1433 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1434
1435 pcs_irq_set(pcs_soc, d->irq, false);
1436}
1437
1438
1439
1440
1441
1442static void pcs_irq_unmask(struct irq_data *d)
1443{
1444 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1445
1446 pcs_irq_set(pcs_soc, d->irq, true);
1447}
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1458{
1459 if (state)
1460 pcs_irq_unmask(d);
1461 else
1462 pcs_irq_mask(d);
1463
1464 return 0;
1465}
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1476{
1477 struct pcs_device *pcs;
1478 struct list_head *pos;
1479 int count = 0;
1480
1481 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1482 list_for_each(pos, &pcs->irqs) {
1483 struct pcs_interrupt *pcswi;
1484 unsigned mask;
1485
1486 pcswi = list_entry(pos, struct pcs_interrupt, node);
1487 raw_spin_lock(&pcs->lock);
1488 mask = pcs->read(pcswi->reg);
1489 raw_spin_unlock(&pcs->lock);
1490 if (mask & pcs_soc->irq_status_mask) {
1491 generic_handle_irq(irq_find_mapping(pcs->domain,
1492 pcswi->hwirq));
1493 count++;
1494 }
1495 }
1496
1497 return count;
1498}
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508static irqreturn_t pcs_irq_handler(int irq, void *d)
1509{
1510 struct pcs_soc_data *pcs_soc = d;
1511
1512 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1513}
1514
1515
1516
1517
1518
1519
1520
1521
1522static void pcs_irq_chain_handler(struct irq_desc *desc)
1523{
1524 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1525 struct irq_chip *chip;
1526
1527 chip = irq_desc_get_chip(desc);
1528 chained_irq_enter(chip, desc);
1529 pcs_irq_handle(pcs_soc);
1530
1531 chained_irq_exit(chip, desc);
1532}
1533
1534static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1535 irq_hw_number_t hwirq)
1536{
1537 struct pcs_soc_data *pcs_soc = d->host_data;
1538 struct pcs_device *pcs;
1539 struct pcs_interrupt *pcswi;
1540
1541 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1542 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1543 if (!pcswi)
1544 return -ENOMEM;
1545
1546 pcswi->reg = pcs->base + hwirq;
1547 pcswi->hwirq = hwirq;
1548 pcswi->irq = irq;
1549
1550 mutex_lock(&pcs->mutex);
1551 list_add_tail(&pcswi->node, &pcs->irqs);
1552 mutex_unlock(&pcs->mutex);
1553
1554 irq_set_chip_data(irq, pcs_soc);
1555 irq_set_chip_and_handler(irq, &pcs->chip,
1556 handle_level_irq);
1557 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1558 irq_set_noprobe(irq);
1559
1560 return 0;
1561}
1562
1563static const struct irq_domain_ops pcs_irqdomain_ops = {
1564 .map = pcs_irqdomain_map,
1565 .xlate = irq_domain_xlate_onecell,
1566};
1567
1568
1569
1570
1571
1572
1573static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1574 struct device_node *np)
1575{
1576 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1577 const char *name = "pinctrl";
1578 int num_irqs;
1579
1580 if (!pcs_soc->irq_enable_mask ||
1581 !pcs_soc->irq_status_mask) {
1582 pcs_soc->irq = -1;
1583 return -EINVAL;
1584 }
1585
1586 INIT_LIST_HEAD(&pcs->irqs);
1587 pcs->chip.name = name;
1588 pcs->chip.irq_ack = pcs_irq_mask;
1589 pcs->chip.irq_mask = pcs_irq_mask;
1590 pcs->chip.irq_unmask = pcs_irq_unmask;
1591 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1592
1593 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1594 int res;
1595
1596 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1597 IRQF_SHARED | IRQF_NO_SUSPEND |
1598 IRQF_NO_THREAD,
1599 name, pcs_soc);
1600 if (res) {
1601 pcs_soc->irq = -1;
1602 return res;
1603 }
1604 } else {
1605 irq_set_chained_handler_and_data(pcs_soc->irq,
1606 pcs_irq_chain_handler,
1607 pcs_soc);
1608 }
1609
1610
1611
1612
1613
1614
1615
1616 num_irqs = pcs->size;
1617
1618 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1619 &pcs_irqdomain_ops,
1620 pcs_soc);
1621 if (!pcs->domain) {
1622 irq_set_chained_handler(pcs_soc->irq, NULL);
1623 return -EINVAL;
1624 }
1625
1626 return 0;
1627}
1628
1629#ifdef CONFIG_PM
1630static int pcs_save_context(struct pcs_device *pcs)
1631{
1632 int i, mux_bytes;
1633 u64 *regsl;
1634 u32 *regsw;
1635 u16 *regshw;
1636
1637 mux_bytes = pcs->width / BITS_PER_BYTE;
1638
1639 if (!pcs->saved_vals) {
1640 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1641 if (!pcs->saved_vals)
1642 return -ENOMEM;
1643 }
1644
1645 switch (pcs->width) {
1646 case 64:
1647 regsl = pcs->saved_vals;
1648 for (i = 0; i < pcs->size; i += mux_bytes)
1649 *regsl++ = pcs->read(pcs->base + i);
1650 break;
1651 case 32:
1652 regsw = pcs->saved_vals;
1653 for (i = 0; i < pcs->size; i += mux_bytes)
1654 *regsw++ = pcs->read(pcs->base + i);
1655 break;
1656 case 16:
1657 regshw = pcs->saved_vals;
1658 for (i = 0; i < pcs->size; i += mux_bytes)
1659 *regshw++ = pcs->read(pcs->base + i);
1660 break;
1661 }
1662
1663 return 0;
1664}
1665
1666static void pcs_restore_context(struct pcs_device *pcs)
1667{
1668 int i, mux_bytes;
1669 u64 *regsl;
1670 u32 *regsw;
1671 u16 *regshw;
1672
1673 mux_bytes = pcs->width / BITS_PER_BYTE;
1674
1675 switch (pcs->width) {
1676 case 64:
1677 regsl = pcs->saved_vals;
1678 for (i = 0; i < pcs->size; i += mux_bytes)
1679 pcs->write(*regsl++, pcs->base + i);
1680 break;
1681 case 32:
1682 regsw = pcs->saved_vals;
1683 for (i = 0; i < pcs->size; i += mux_bytes)
1684 pcs->write(*regsw++, pcs->base + i);
1685 break;
1686 case 16:
1687 regshw = pcs->saved_vals;
1688 for (i = 0; i < pcs->size; i += mux_bytes)
1689 pcs->write(*regshw++, pcs->base + i);
1690 break;
1691 }
1692}
1693
1694static int pinctrl_single_suspend(struct platform_device *pdev,
1695 pm_message_t state)
1696{
1697 struct pcs_device *pcs;
1698
1699 pcs = platform_get_drvdata(pdev);
1700 if (!pcs)
1701 return -EINVAL;
1702
1703 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1704 int ret;
1705
1706 ret = pcs_save_context(pcs);
1707 if (ret < 0)
1708 return ret;
1709 }
1710
1711 return pinctrl_force_sleep(pcs->pctl);
1712}
1713
1714static int pinctrl_single_resume(struct platform_device *pdev)
1715{
1716 struct pcs_device *pcs;
1717
1718 pcs = platform_get_drvdata(pdev);
1719 if (!pcs)
1720 return -EINVAL;
1721
1722 if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1723 pcs_restore_context(pcs);
1724
1725 return pinctrl_force_default(pcs->pctl);
1726}
1727#endif
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1740 struct device_node *np,
1741 int cells)
1742{
1743 struct property *p;
1744 const char *name = "#pinctrl-cells";
1745 int error;
1746 u32 val;
1747
1748 error = of_property_read_u32(np, name, &val);
1749 if (!error)
1750 return 0;
1751
1752 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1753 name, cells);
1754
1755 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1756 if (!p)
1757 return -ENOMEM;
1758
1759 p->length = sizeof(__be32);
1760 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1761 if (!p->value)
1762 return -ENOMEM;
1763 *(__be32 *)p->value = cpu_to_be32(cells);
1764
1765 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1766 if (!p->name)
1767 return -ENOMEM;
1768
1769 pcs->missing_nr_pinctrl_cells = p;
1770
1771#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1772 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1773#endif
1774
1775 return error;
1776}
1777
1778static int pcs_probe(struct platform_device *pdev)
1779{
1780 struct device_node *np = pdev->dev.of_node;
1781 struct pcs_pdata *pdata;
1782 struct resource *res;
1783 struct pcs_device *pcs;
1784 const struct pcs_soc_data *soc;
1785 int ret;
1786
1787 soc = of_device_get_match_data(&pdev->dev);
1788 if (WARN_ON(!soc))
1789 return -EINVAL;
1790
1791 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1792 if (!pcs)
1793 return -ENOMEM;
1794
1795 pcs->dev = &pdev->dev;
1796 pcs->np = np;
1797 raw_spin_lock_init(&pcs->lock);
1798 mutex_init(&pcs->mutex);
1799 INIT_LIST_HEAD(&pcs->gpiofuncs);
1800 pcs->flags = soc->flags;
1801 memcpy(&pcs->socdata, soc, sizeof(*soc));
1802
1803 ret = of_property_read_u32(np, "pinctrl-single,register-width",
1804 &pcs->width);
1805 if (ret) {
1806 dev_err(pcs->dev, "register width not specified\n");
1807
1808 return ret;
1809 }
1810
1811 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1812 &pcs->fmask);
1813 if (!ret) {
1814 pcs->fshift = __ffs(pcs->fmask);
1815 pcs->fmax = pcs->fmask >> pcs->fshift;
1816 } else {
1817
1818 pcs->fmask = 0;
1819 pcs->fshift = 0;
1820 pcs->fmax = 0;
1821 }
1822
1823 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1824 &pcs->foff);
1825 if (ret)
1826 pcs->foff = PCS_OFF_DISABLED;
1827
1828 pcs->bits_per_mux = of_property_read_bool(np,
1829 "pinctrl-single,bit-per-mux");
1830 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1831 pcs->bits_per_mux ? 2 : 1);
1832 if (ret) {
1833 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1834
1835 return ret;
1836 }
1837
1838 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1839 if (!res) {
1840 dev_err(pcs->dev, "could not get resource\n");
1841 return -ENODEV;
1842 }
1843
1844 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1845 resource_size(res), DRIVER_NAME);
1846 if (!pcs->res) {
1847 dev_err(pcs->dev, "could not get mem_region\n");
1848 return -EBUSY;
1849 }
1850
1851 pcs->size = resource_size(pcs->res);
1852 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1853 if (!pcs->base) {
1854 dev_err(pcs->dev, "could not ioremap\n");
1855 return -ENODEV;
1856 }
1857
1858 platform_set_drvdata(pdev, pcs);
1859
1860 switch (pcs->width) {
1861 case 8:
1862 pcs->read = pcs_readb;
1863 pcs->write = pcs_writeb;
1864 break;
1865 case 16:
1866 pcs->read = pcs_readw;
1867 pcs->write = pcs_writew;
1868 break;
1869 case 32:
1870 pcs->read = pcs_readl;
1871 pcs->write = pcs_writel;
1872 break;
1873 default:
1874 break;
1875 }
1876
1877 pcs->desc.name = DRIVER_NAME;
1878 pcs->desc.pctlops = &pcs_pinctrl_ops;
1879 pcs->desc.pmxops = &pcs_pinmux_ops;
1880 if (PCS_HAS_PINCONF)
1881 pcs->desc.confops = &pcs_pinconf_ops;
1882 pcs->desc.owner = THIS_MODULE;
1883
1884 ret = pcs_allocate_pin_table(pcs);
1885 if (ret < 0)
1886 goto free;
1887
1888 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1889 if (ret) {
1890 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1891 goto free;
1892 }
1893
1894 ret = pcs_add_gpio_func(np, pcs);
1895 if (ret < 0)
1896 goto free;
1897
1898 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1899 if (pcs->socdata.irq)
1900 pcs->flags |= PCS_FEAT_IRQ;
1901
1902
1903 pdata = dev_get_platdata(&pdev->dev);
1904 if (pdata) {
1905 if (pdata->rearm)
1906 pcs->socdata.rearm = pdata->rearm;
1907 if (pdata->irq) {
1908 pcs->socdata.irq = pdata->irq;
1909 pcs->flags |= PCS_FEAT_IRQ;
1910 }
1911 }
1912
1913 if (PCS_HAS_IRQ) {
1914 ret = pcs_irq_init_chained_handler(pcs, np);
1915 if (ret < 0)
1916 dev_warn(pcs->dev, "initialized with no interrupts\n");
1917 }
1918
1919 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1920
1921 return pinctrl_enable(pcs->pctl);
1922
1923free:
1924 pcs_free_resources(pcs);
1925
1926 return ret;
1927}
1928
1929static int pcs_remove(struct platform_device *pdev)
1930{
1931 struct pcs_device *pcs = platform_get_drvdata(pdev);
1932
1933 if (!pcs)
1934 return 0;
1935
1936 pcs_free_resources(pcs);
1937
1938 return 0;
1939}
1940
1941static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1942 .flags = PCS_QUIRK_SHARED_IRQ,
1943 .irq_enable_mask = (1 << 14),
1944 .irq_status_mask = (1 << 15),
1945};
1946
1947static const struct pcs_soc_data pinctrl_single_dra7 = {
1948 .irq_enable_mask = (1 << 24),
1949 .irq_status_mask = (1 << 25),
1950};
1951
1952static const struct pcs_soc_data pinctrl_single_am437x = {
1953 .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1954 .irq_enable_mask = (1 << 29),
1955 .irq_status_mask = (1 << 30),
1956};
1957
1958static const struct pcs_soc_data pinctrl_single = {
1959};
1960
1961static const struct pcs_soc_data pinconf_single = {
1962 .flags = PCS_FEAT_PINCONF,
1963};
1964
1965static const struct of_device_id pcs_of_match[] = {
1966 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1967 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1968 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1969 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1970 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1971 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1972 { .compatible = "pinconf-single", .data = &pinconf_single },
1973 { },
1974};
1975MODULE_DEVICE_TABLE(of, pcs_of_match);
1976
1977static struct platform_driver pcs_driver = {
1978 .probe = pcs_probe,
1979 .remove = pcs_remove,
1980 .driver = {
1981 .name = DRIVER_NAME,
1982 .of_match_table = pcs_of_match,
1983 },
1984#ifdef CONFIG_PM
1985 .suspend = pinctrl_single_suspend,
1986 .resume = pinctrl_single_resume,
1987#endif
1988};
1989
1990module_platform_driver(pcs_driver);
1991
1992MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1993MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1994MODULE_LICENSE("GPL v2");
1995