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47#include <linux/module.h>
48#include <linux/reboot.h>
49#include <linux/spinlock.h>
50#include <linux/pci_ids.h>
51#include <linux/interrupt.h>
52#include <linux/moduleparam.h>
53#include <linux/errno.h>
54#include <linux/types.h>
55#include <linux/delay.h>
56#include <linux/dma-mapping.h>
57#include <linux/timer.h>
58#include <linux/slab.h>
59#include <linux/pci.h>
60#include <linux/aer.h>
61#include <linux/circ_buf.h>
62#include <asm/dma.h>
63#include <asm/io.h>
64#include <linux/uaccess.h>
65#include <scsi/scsi_host.h>
66#include <scsi/scsi.h>
67#include <scsi/scsi_cmnd.h>
68#include <scsi/scsi_tcq.h>
69#include <scsi/scsi_device.h>
70#include <scsi/scsi_transport.h>
71#include <scsi/scsicam.h>
72#include "arcmsr.h"
73MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
74MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
75MODULE_LICENSE("Dual BSD/GPL");
76MODULE_VERSION(ARCMSR_DRIVER_VERSION);
77
78static int msix_enable = 1;
79module_param(msix_enable, int, S_IRUGO);
80MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)");
81
82static int msi_enable = 1;
83module_param(msi_enable, int, S_IRUGO);
84MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)");
85
86static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
87module_param(host_can_queue, int, S_IRUGO);
88MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128");
89
90static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
91module_param(cmd_per_lun, int, S_IRUGO);
92MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32");
93
94static int dma_mask_64 = 0;
95module_param(dma_mask_64, int, S_IRUGO);
96MODULE_PARM_DESC(dma_mask_64, " set DMA mask to 64 bits(0 ~ 1), dma_mask_64=1(64 bits), =0(32 bits)");
97
98static int set_date_time = 0;
99module_param(set_date_time, int, S_IRUGO);
100MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable");
101
102static int cmd_timeout = ARCMSR_DEFAULT_TIMEOUT;
103module_param(cmd_timeout, int, S_IRUGO);
104MODULE_PARM_DESC(cmd_timeout, " scsi cmd timeout(0 ~ 120 sec.), default is 90");
105
106#define ARCMSR_SLEEPTIME 10
107#define ARCMSR_RETRYCOUNT 12
108
109static wait_queue_head_t wait_q;
110static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
111 struct scsi_cmnd *cmd);
112static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
113static int arcmsr_abort(struct scsi_cmnd *);
114static int arcmsr_bus_reset(struct scsi_cmnd *);
115static int arcmsr_bios_param(struct scsi_device *sdev,
116 struct block_device *bdev, sector_t capacity, int *info);
117static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
118static int arcmsr_probe(struct pci_dev *pdev,
119 const struct pci_device_id *id);
120static int __maybe_unused arcmsr_suspend(struct device *dev);
121static int __maybe_unused arcmsr_resume(struct device *dev);
122static void arcmsr_remove(struct pci_dev *pdev);
123static void arcmsr_shutdown(struct pci_dev *pdev);
124static void arcmsr_iop_init(struct AdapterControlBlock *acb);
125static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
126static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
127static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
128 u32 intmask_org);
129static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
130static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
131static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
132static void arcmsr_request_device_map(struct timer_list *t);
133static void arcmsr_message_isr_bh_fn(struct work_struct *work);
134static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
135static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
136static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
137static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
138static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb);
139static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb);
140static void arcmsr_hbaF_postqueue_isr(struct AdapterControlBlock *acb);
141static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
142static const char *arcmsr_info(struct Scsi_Host *);
143static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
144static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
145static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb);
146static void arcmsr_set_iop_datetime(struct timer_list *);
147static int arcmsr_slave_config(struct scsi_device *sdev);
148static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
149{
150 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
151 queue_depth = ARCMSR_MAX_CMD_PERLUN;
152 return scsi_change_queue_depth(sdev, queue_depth);
153}
154
155static struct scsi_host_template arcmsr_scsi_host_template = {
156 .module = THIS_MODULE,
157 .name = "Areca SAS/SATA RAID driver",
158 .info = arcmsr_info,
159 .queuecommand = arcmsr_queue_command,
160 .eh_abort_handler = arcmsr_abort,
161 .eh_bus_reset_handler = arcmsr_bus_reset,
162 .bios_param = arcmsr_bios_param,
163 .slave_configure = arcmsr_slave_config,
164 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
165 .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD,
166 .this_id = ARCMSR_SCSI_INITIATOR_ID,
167 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
168 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
169 .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN,
170 .shost_attrs = arcmsr_host_attrs,
171 .no_write_same = 1,
172};
173
174static struct pci_device_id arcmsr_device_id_table[] = {
175 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
176 .driver_data = ACB_ADAPTER_TYPE_A},
177 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
178 .driver_data = ACB_ADAPTER_TYPE_A},
179 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
180 .driver_data = ACB_ADAPTER_TYPE_A},
181 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
182 .driver_data = ACB_ADAPTER_TYPE_A},
183 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
184 .driver_data = ACB_ADAPTER_TYPE_A},
185 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
186 .driver_data = ACB_ADAPTER_TYPE_B},
187 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
188 .driver_data = ACB_ADAPTER_TYPE_B},
189 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
190 .driver_data = ACB_ADAPTER_TYPE_B},
191 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203),
192 .driver_data = ACB_ADAPTER_TYPE_B},
193 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
194 .driver_data = ACB_ADAPTER_TYPE_A},
195 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
196 .driver_data = ACB_ADAPTER_TYPE_D},
197 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
198 .driver_data = ACB_ADAPTER_TYPE_A},
199 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
200 .driver_data = ACB_ADAPTER_TYPE_A},
201 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
202 .driver_data = ACB_ADAPTER_TYPE_A},
203 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
204 .driver_data = ACB_ADAPTER_TYPE_A},
205 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
206 .driver_data = ACB_ADAPTER_TYPE_A},
207 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
208 .driver_data = ACB_ADAPTER_TYPE_A},
209 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
210 .driver_data = ACB_ADAPTER_TYPE_A},
211 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
212 .driver_data = ACB_ADAPTER_TYPE_A},
213 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
214 .driver_data = ACB_ADAPTER_TYPE_A},
215 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
216 .driver_data = ACB_ADAPTER_TYPE_C},
217 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884),
218 .driver_data = ACB_ADAPTER_TYPE_E},
219 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1886),
220 .driver_data = ACB_ADAPTER_TYPE_F},
221 {0, 0},
222};
223MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
224
225static SIMPLE_DEV_PM_OPS(arcmsr_pm_ops, arcmsr_suspend, arcmsr_resume);
226
227static struct pci_driver arcmsr_pci_driver = {
228 .name = "arcmsr",
229 .id_table = arcmsr_device_id_table,
230 .probe = arcmsr_probe,
231 .remove = arcmsr_remove,
232 .driver.pm = &arcmsr_pm_ops,
233 .shutdown = arcmsr_shutdown,
234};
235
236
237
238
239
240static void arcmsr_free_io_queue(struct AdapterControlBlock *acb)
241{
242 switch (acb->adapter_type) {
243 case ACB_ADAPTER_TYPE_B:
244 case ACB_ADAPTER_TYPE_D:
245 case ACB_ADAPTER_TYPE_E:
246 case ACB_ADAPTER_TYPE_F:
247 dma_free_coherent(&acb->pdev->dev, acb->ioqueue_size,
248 acb->dma_coherent2, acb->dma_coherent_handle2);
249 break;
250 }
251}
252
253static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
254{
255 struct pci_dev *pdev = acb->pdev;
256 switch (acb->adapter_type){
257 case ACB_ADAPTER_TYPE_A:{
258 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
259 if (!acb->pmuA) {
260 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
261 return false;
262 }
263 break;
264 }
265 case ACB_ADAPTER_TYPE_B:{
266 void __iomem *mem_base0, *mem_base1;
267 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
268 if (!mem_base0) {
269 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
270 return false;
271 }
272 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
273 if (!mem_base1) {
274 iounmap(mem_base0);
275 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
276 return false;
277 }
278 acb->mem_base0 = mem_base0;
279 acb->mem_base1 = mem_base1;
280 break;
281 }
282 case ACB_ADAPTER_TYPE_C:{
283 acb->pmuC = ioremap(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
284 if (!acb->pmuC) {
285 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
286 return false;
287 }
288 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
289 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);
290 return true;
291 }
292 break;
293 }
294 case ACB_ADAPTER_TYPE_D: {
295 void __iomem *mem_base0;
296 unsigned long addr, range;
297
298 addr = (unsigned long)pci_resource_start(pdev, 0);
299 range = pci_resource_len(pdev, 0);
300 mem_base0 = ioremap(addr, range);
301 if (!mem_base0) {
302 pr_notice("arcmsr%d: memory mapping region fail\n",
303 acb->host->host_no);
304 return false;
305 }
306 acb->mem_base0 = mem_base0;
307 break;
308 }
309 case ACB_ADAPTER_TYPE_E: {
310 acb->pmuE = ioremap(pci_resource_start(pdev, 1),
311 pci_resource_len(pdev, 1));
312 if (!acb->pmuE) {
313 pr_notice("arcmsr%d: memory mapping region fail \n",
314 acb->host->host_no);
315 return false;
316 }
317 writel(0, &acb->pmuE->host_int_status);
318 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell);
319 acb->in_doorbell = 0;
320 acb->out_doorbell = 0;
321 break;
322 }
323 case ACB_ADAPTER_TYPE_F: {
324 acb->pmuF = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
325 if (!acb->pmuF) {
326 pr_notice("arcmsr%d: memory mapping region fail\n",
327 acb->host->host_no);
328 return false;
329 }
330 writel(0, &acb->pmuF->host_int_status);
331 writel(ARCMSR_HBFMU_DOORBELL_SYNC, &acb->pmuF->iobound_doorbell);
332 acb->in_doorbell = 0;
333 acb->out_doorbell = 0;
334 break;
335 }
336 }
337 return true;
338}
339
340static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
341{
342 switch (acb->adapter_type) {
343 case ACB_ADAPTER_TYPE_A:
344 iounmap(acb->pmuA);
345 break;
346 case ACB_ADAPTER_TYPE_B:
347 iounmap(acb->mem_base0);
348 iounmap(acb->mem_base1);
349 break;
350 case ACB_ADAPTER_TYPE_C:
351 iounmap(acb->pmuC);
352 break;
353 case ACB_ADAPTER_TYPE_D:
354 iounmap(acb->mem_base0);
355 break;
356 case ACB_ADAPTER_TYPE_E:
357 iounmap(acb->pmuE);
358 break;
359 case ACB_ADAPTER_TYPE_F:
360 iounmap(acb->pmuF);
361 break;
362 }
363}
364
365static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
366{
367 irqreturn_t handle_state;
368 struct AdapterControlBlock *acb = dev_id;
369
370 handle_state = arcmsr_interrupt(acb);
371 return handle_state;
372}
373
374static int arcmsr_bios_param(struct scsi_device *sdev,
375 struct block_device *bdev, sector_t capacity, int *geom)
376{
377 int heads, sectors, cylinders, total_capacity;
378
379 if (scsi_partsize(bdev, capacity, geom))
380 return 0;
381
382 total_capacity = capacity;
383 heads = 64;
384 sectors = 32;
385 cylinders = total_capacity / (heads * sectors);
386 if (cylinders > 1024) {
387 heads = 255;
388 sectors = 63;
389 cylinders = total_capacity / (heads * sectors);
390 }
391 geom[0] = heads;
392 geom[1] = sectors;
393 geom[2] = cylinders;
394 return 0;
395}
396
397static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
398{
399 struct MessageUnit_A __iomem *reg = acb->pmuA;
400 int i;
401
402 for (i = 0; i < 2000; i++) {
403 if (readl(®->outbound_intstatus) &
404 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
405 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
406 ®->outbound_intstatus);
407 return true;
408 }
409 msleep(10);
410 }
411
412 return false;
413}
414
415static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
416{
417 struct MessageUnit_B *reg = acb->pmuB;
418 int i;
419
420 for (i = 0; i < 2000; i++) {
421 if (readl(reg->iop2drv_doorbell)
422 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
423 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
424 reg->iop2drv_doorbell);
425 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
426 reg->drv2iop_doorbell);
427 return true;
428 }
429 msleep(10);
430 }
431
432 return false;
433}
434
435static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
436{
437 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
438 int i;
439
440 for (i = 0; i < 2000; i++) {
441 if (readl(&phbcmu->outbound_doorbell)
442 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
443 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
444 &phbcmu->outbound_doorbell_clear);
445 return true;
446 }
447 msleep(10);
448 }
449
450 return false;
451}
452
453static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
454{
455 struct MessageUnit_D *reg = pACB->pmuD;
456 int i;
457
458 for (i = 0; i < 2000; i++) {
459 if (readl(reg->outbound_doorbell)
460 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
461 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
462 reg->outbound_doorbell);
463 return true;
464 }
465 msleep(10);
466 }
467 return false;
468}
469
470static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB)
471{
472 int i;
473 uint32_t read_doorbell;
474 struct MessageUnit_E __iomem *phbcmu = pACB->pmuE;
475
476 for (i = 0; i < 2000; i++) {
477 read_doorbell = readl(&phbcmu->iobound_doorbell);
478 if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
479 writel(0, &phbcmu->host_int_status);
480 pACB->in_doorbell = read_doorbell;
481 return true;
482 }
483 msleep(10);
484 }
485 return false;
486}
487
488static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
489{
490 struct MessageUnit_A __iomem *reg = acb->pmuA;
491 int retry_count = 30;
492 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
493 do {
494 if (arcmsr_hbaA_wait_msgint_ready(acb))
495 break;
496 else {
497 retry_count--;
498 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
499 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
500 }
501 } while (retry_count != 0);
502}
503
504static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
505{
506 struct MessageUnit_B *reg = acb->pmuB;
507 int retry_count = 30;
508 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
509 do {
510 if (arcmsr_hbaB_wait_msgint_ready(acb))
511 break;
512 else {
513 retry_count--;
514 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
515 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
516 }
517 } while (retry_count != 0);
518}
519
520static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
521{
522 struct MessageUnit_C __iomem *reg = pACB->pmuC;
523 int retry_count = 30;
524 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
525 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
526 do {
527 if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
528 break;
529 } else {
530 retry_count--;
531 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
532 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
533 }
534 } while (retry_count != 0);
535 return;
536}
537
538static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
539{
540 int retry_count = 15;
541 struct MessageUnit_D *reg = pACB->pmuD;
542
543 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
544 do {
545 if (arcmsr_hbaD_wait_msgint_ready(pACB))
546 break;
547
548 retry_count--;
549 pr_notice("arcmsr%d: wait 'flush adapter "
550 "cache' timeout, retry count down = %d\n",
551 pACB->host->host_no, retry_count);
552 } while (retry_count != 0);
553}
554
555static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB)
556{
557 int retry_count = 30;
558 struct MessageUnit_E __iomem *reg = pACB->pmuE;
559
560 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
561 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
562 writel(pACB->out_doorbell, ®->iobound_doorbell);
563 do {
564 if (arcmsr_hbaE_wait_msgint_ready(pACB))
565 break;
566 retry_count--;
567 pr_notice("arcmsr%d: wait 'flush adapter "
568 "cache' timeout, retry count down = %d\n",
569 pACB->host->host_no, retry_count);
570 } while (retry_count != 0);
571}
572
573static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
574{
575 switch (acb->adapter_type) {
576
577 case ACB_ADAPTER_TYPE_A:
578 arcmsr_hbaA_flush_cache(acb);
579 break;
580 case ACB_ADAPTER_TYPE_B:
581 arcmsr_hbaB_flush_cache(acb);
582 break;
583 case ACB_ADAPTER_TYPE_C:
584 arcmsr_hbaC_flush_cache(acb);
585 break;
586 case ACB_ADAPTER_TYPE_D:
587 arcmsr_hbaD_flush_cache(acb);
588 break;
589 case ACB_ADAPTER_TYPE_E:
590 case ACB_ADAPTER_TYPE_F:
591 arcmsr_hbaE_flush_cache(acb);
592 break;
593 }
594}
595
596static void arcmsr_hbaB_assign_regAddr(struct AdapterControlBlock *acb)
597{
598 struct MessageUnit_B *reg = acb->pmuB;
599
600 if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) {
601 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203);
602 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203);
603 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203);
604 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203);
605 } else {
606 reg->drv2iop_doorbell= MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL);
607 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK);
608 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL);
609 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK);
610 }
611 reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER);
612 reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER);
613 reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER);
614}
615
616static void arcmsr_hbaD_assign_regAddr(struct AdapterControlBlock *acb)
617{
618 struct MessageUnit_D *reg = acb->pmuD;
619
620 reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID);
621 reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION);
622 reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK);
623 reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET);
624 reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST);
625 reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS);
626 reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE);
627 reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0);
628 reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1);
629 reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0);
630 reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1);
631 reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL);
632 reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL);
633 reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE);
634 reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW);
635 reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH);
636 reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER);
637 reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW);
638 reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH);
639 reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER);
640 reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER);
641 reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE);
642 reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE);
643 reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER);
644 reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER);
645 reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER);
646}
647
648static void arcmsr_hbaF_assign_regAddr(struct AdapterControlBlock *acb)
649{
650 dma_addr_t host_buffer_dma;
651 struct MessageUnit_F __iomem *pmuF;
652
653 memset(acb->dma_coherent2, 0xff, acb->completeQ_size);
654 acb->message_wbuffer = (uint32_t *)round_up((unsigned long)acb->dma_coherent2 +
655 acb->completeQ_size, 4);
656 acb->message_rbuffer = ((void *)acb->message_wbuffer) + 0x100;
657 acb->msgcode_rwbuffer = ((void *)acb->message_wbuffer) + 0x200;
658 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE);
659 host_buffer_dma = round_up(acb->dma_coherent_handle2 + acb->completeQ_size, 4);
660 pmuF = acb->pmuF;
661
662 writel(lower_32_bits(host_buffer_dma | 1), &pmuF->inbound_msgaddr0);
663
664 writel(upper_32_bits(host_buffer_dma), &pmuF->inbound_msgaddr1);
665
666 writel(ARCMSR_HBFMU_DOORBELL_SYNC1, &pmuF->iobound_doorbell);
667}
668
669static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb)
670{
671 bool rtn = true;
672 void *dma_coherent;
673 dma_addr_t dma_coherent_handle;
674 struct pci_dev *pdev = acb->pdev;
675
676 switch (acb->adapter_type) {
677 case ACB_ADAPTER_TYPE_B: {
678 acb->ioqueue_size = roundup(sizeof(struct MessageUnit_B), 32);
679 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
680 &dma_coherent_handle, GFP_KERNEL);
681 if (!dma_coherent) {
682 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
683 return false;
684 }
685 acb->dma_coherent_handle2 = dma_coherent_handle;
686 acb->dma_coherent2 = dma_coherent;
687 acb->pmuB = (struct MessageUnit_B *)dma_coherent;
688 arcmsr_hbaB_assign_regAddr(acb);
689 }
690 break;
691 case ACB_ADAPTER_TYPE_D: {
692 acb->ioqueue_size = roundup(sizeof(struct MessageUnit_D), 32);
693 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
694 &dma_coherent_handle, GFP_KERNEL);
695 if (!dma_coherent) {
696 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
697 return false;
698 }
699 acb->dma_coherent_handle2 = dma_coherent_handle;
700 acb->dma_coherent2 = dma_coherent;
701 acb->pmuD = (struct MessageUnit_D *)dma_coherent;
702 arcmsr_hbaD_assign_regAddr(acb);
703 }
704 break;
705 case ACB_ADAPTER_TYPE_E: {
706 uint32_t completeQ_size;
707 completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128;
708 acb->ioqueue_size = roundup(completeQ_size, 32);
709 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
710 &dma_coherent_handle, GFP_KERNEL);
711 if (!dma_coherent){
712 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
713 return false;
714 }
715 acb->dma_coherent_handle2 = dma_coherent_handle;
716 acb->dma_coherent2 = dma_coherent;
717 acb->pCompletionQ = dma_coherent;
718 acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ);
719 acb->doneq_index = 0;
720 }
721 break;
722 case ACB_ADAPTER_TYPE_F: {
723 uint32_t QueueDepth;
724 uint32_t depthTbl[] = {256, 512, 1024, 128, 64, 32};
725
726 arcmsr_wait_firmware_ready(acb);
727 QueueDepth = depthTbl[readl(&acb->pmuF->outbound_msgaddr1) & 7];
728 acb->completeQ_size = sizeof(struct deliver_completeQ) * QueueDepth + 128;
729 acb->ioqueue_size = roundup(acb->completeQ_size + MESG_RW_BUFFER_SIZE, 32);
730 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
731 &dma_coherent_handle, GFP_KERNEL);
732 if (!dma_coherent) {
733 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
734 return false;
735 }
736 acb->dma_coherent_handle2 = dma_coherent_handle;
737 acb->dma_coherent2 = dma_coherent;
738 acb->pCompletionQ = dma_coherent;
739 acb->completionQ_entry = acb->completeQ_size / sizeof(struct deliver_completeQ);
740 acb->doneq_index = 0;
741 arcmsr_hbaF_assign_regAddr(acb);
742 }
743 break;
744 default:
745 break;
746 }
747 return rtn;
748}
749
750static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
751{
752 struct pci_dev *pdev = acb->pdev;
753 void *dma_coherent;
754 dma_addr_t dma_coherent_handle;
755 struct CommandControlBlock *ccb_tmp;
756 int i = 0, j = 0;
757 unsigned long cdb_phyaddr, next_ccb_phy;
758 unsigned long roundup_ccbsize;
759 unsigned long max_xfer_len;
760 unsigned long max_sg_entrys;
761 uint32_t firm_config_version, curr_phy_upper32;
762
763 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
764 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
765 acb->devstate[i][j] = ARECA_RAID_GONE;
766
767 max_xfer_len = ARCMSR_MAX_XFER_LEN;
768 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
769 firm_config_version = acb->firm_cfg_version;
770 if((firm_config_version & 0xFF) >= 3){
771 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;
772 max_sg_entrys = (max_xfer_len/4096);
773 }
774 acb->host->max_sectors = max_xfer_len/512;
775 acb->host->sg_tablesize = max_sg_entrys;
776 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
777 acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB;
778 if (acb->adapter_type != ACB_ADAPTER_TYPE_F)
779 acb->uncache_size += acb->ioqueue_size;
780 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
781 if(!dma_coherent){
782 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
783 return -ENOMEM;
784 }
785 acb->dma_coherent = dma_coherent;
786 acb->dma_coherent_handle = dma_coherent_handle;
787 memset(dma_coherent, 0, acb->uncache_size);
788 acb->ccbsize = roundup_ccbsize;
789 ccb_tmp = dma_coherent;
790 curr_phy_upper32 = upper_32_bits(dma_coherent_handle);
791 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
792 for(i = 0; i < acb->maxFreeCCB; i++){
793 cdb_phyaddr = (unsigned long)dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
794 switch (acb->adapter_type) {
795 case ACB_ADAPTER_TYPE_A:
796 case ACB_ADAPTER_TYPE_B:
797 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
798 break;
799 case ACB_ADAPTER_TYPE_C:
800 case ACB_ADAPTER_TYPE_D:
801 case ACB_ADAPTER_TYPE_E:
802 case ACB_ADAPTER_TYPE_F:
803 ccb_tmp->cdb_phyaddr = cdb_phyaddr;
804 break;
805 }
806 acb->pccb_pool[i] = ccb_tmp;
807 ccb_tmp->acb = acb;
808 ccb_tmp->smid = (u32)i << 16;
809 INIT_LIST_HEAD(&ccb_tmp->list);
810 next_ccb_phy = dma_coherent_handle + roundup_ccbsize;
811 if (upper_32_bits(next_ccb_phy) != curr_phy_upper32) {
812 acb->maxFreeCCB = i;
813 acb->host->can_queue = i;
814 break;
815 }
816 else
817 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
818 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
819 dma_coherent_handle = next_ccb_phy;
820 }
821 if (acb->adapter_type != ACB_ADAPTER_TYPE_F) {
822 acb->dma_coherent_handle2 = dma_coherent_handle;
823 acb->dma_coherent2 = ccb_tmp;
824 }
825 switch (acb->adapter_type) {
826 case ACB_ADAPTER_TYPE_B:
827 acb->pmuB = (struct MessageUnit_B *)acb->dma_coherent2;
828 arcmsr_hbaB_assign_regAddr(acb);
829 break;
830 case ACB_ADAPTER_TYPE_D:
831 acb->pmuD = (struct MessageUnit_D *)acb->dma_coherent2;
832 arcmsr_hbaD_assign_regAddr(acb);
833 break;
834 case ACB_ADAPTER_TYPE_E:
835 acb->pCompletionQ = acb->dma_coherent2;
836 acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ);
837 acb->doneq_index = 0;
838 break;
839 }
840 return 0;
841}
842
843static void arcmsr_message_isr_bh_fn(struct work_struct *work)
844{
845 struct AdapterControlBlock *acb = container_of(work,
846 struct AdapterControlBlock, arcmsr_do_message_isr_bh);
847 char *acb_dev_map = (char *)acb->device_map;
848 uint32_t __iomem *signature = NULL;
849 char __iomem *devicemap = NULL;
850 int target, lun;
851 struct scsi_device *psdev;
852 char diff, temp;
853
854 switch (acb->adapter_type) {
855 case ACB_ADAPTER_TYPE_A: {
856 struct MessageUnit_A __iomem *reg = acb->pmuA;
857
858 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]);
859 devicemap = (char __iomem *)(®->message_rwbuffer[21]);
860 break;
861 }
862 case ACB_ADAPTER_TYPE_B: {
863 struct MessageUnit_B *reg = acb->pmuB;
864
865 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]);
866 devicemap = (char __iomem *)(®->message_rwbuffer[21]);
867 break;
868 }
869 case ACB_ADAPTER_TYPE_C: {
870 struct MessageUnit_C __iomem *reg = acb->pmuC;
871
872 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]);
873 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]);
874 break;
875 }
876 case ACB_ADAPTER_TYPE_D: {
877 struct MessageUnit_D *reg = acb->pmuD;
878
879 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]);
880 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]);
881 break;
882 }
883 case ACB_ADAPTER_TYPE_E: {
884 struct MessageUnit_E __iomem *reg = acb->pmuE;
885
886 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]);
887 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]);
888 break;
889 }
890 case ACB_ADAPTER_TYPE_F: {
891 signature = (uint32_t __iomem *)(&acb->msgcode_rwbuffer[0]);
892 devicemap = (char __iomem *)(&acb->msgcode_rwbuffer[21]);
893 break;
894 }
895 }
896 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
897 return;
898 for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
899 target++) {
900 temp = readb(devicemap);
901 diff = (*acb_dev_map) ^ temp;
902 if (diff != 0) {
903 *acb_dev_map = temp;
904 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
905 lun++) {
906 if ((diff & 0x01) == 1 &&
907 (temp & 0x01) == 1) {
908 scsi_add_device(acb->host,
909 0, target, lun);
910 } else if ((diff & 0x01) == 1
911 && (temp & 0x01) == 0) {
912 psdev = scsi_device_lookup(acb->host,
913 0, target, lun);
914 if (psdev != NULL) {
915 scsi_remove_device(psdev);
916 scsi_device_put(psdev);
917 }
918 }
919 temp >>= 1;
920 diff >>= 1;
921 }
922 }
923 devicemap++;
924 acb_dev_map++;
925 }
926 acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG;
927}
928
929static int
930arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
931{
932 unsigned long flags;
933 int nvec, i;
934
935 if (msix_enable == 0)
936 goto msi_int0;
937 nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS,
938 PCI_IRQ_MSIX);
939 if (nvec > 0) {
940 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
941 flags = 0;
942 } else {
943msi_int0:
944 if (msi_enable == 1) {
945 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
946 if (nvec == 1) {
947 dev_info(&pdev->dev, "msi enabled\n");
948 goto msi_int1;
949 }
950 }
951 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
952 if (nvec < 1)
953 return FAILED;
954msi_int1:
955 flags = IRQF_SHARED;
956 }
957
958 acb->vector_count = nvec;
959 for (i = 0; i < nvec; i++) {
960 if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt,
961 flags, "arcmsr", acb)) {
962 pr_warn("arcmsr%d: request_irq =%d failed!\n",
963 acb->host->host_no, pci_irq_vector(pdev, i));
964 goto out_free_irq;
965 }
966 }
967
968 return SUCCESS;
969out_free_irq:
970 while (--i >= 0)
971 free_irq(pci_irq_vector(pdev, i), acb);
972 pci_free_irq_vectors(pdev);
973 return FAILED;
974}
975
976static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb)
977{
978 INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
979 pacb->fw_flag = FW_NORMAL;
980 timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0);
981 pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
982 add_timer(&pacb->eternal_timer);
983}
984
985static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb)
986{
987 timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0);
988 pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000);
989 add_timer(&pacb->refresh_timer);
990}
991
992static int arcmsr_set_dma_mask(struct AdapterControlBlock *acb)
993{
994 struct pci_dev *pcidev = acb->pdev;
995
996 if (IS_DMA64) {
997 if (((acb->adapter_type == ACB_ADAPTER_TYPE_A) && !dma_mask_64) ||
998 dma_set_mask(&pcidev->dev, DMA_BIT_MASK(64)))
999 goto dma32;
1000 if (dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(64)) ||
1001 dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64))) {
1002 printk("arcmsr: set DMA 64 mask failed\n");
1003 return -ENXIO;
1004 }
1005 } else {
1006dma32:
1007 if (dma_set_mask(&pcidev->dev, DMA_BIT_MASK(32)) ||
1008 dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(32)) ||
1009 dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32))) {
1010 printk("arcmsr: set DMA 32-bit mask failed\n");
1011 return -ENXIO;
1012 }
1013 }
1014 return 0;
1015}
1016
1017static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1018{
1019 struct Scsi_Host *host;
1020 struct AdapterControlBlock *acb;
1021 uint8_t bus,dev_fun;
1022 int error;
1023 error = pci_enable_device(pdev);
1024 if(error){
1025 return -ENODEV;
1026 }
1027 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
1028 if(!host){
1029 goto pci_disable_dev;
1030 }
1031 init_waitqueue_head(&wait_q);
1032 bus = pdev->bus->number;
1033 dev_fun = pdev->devfn;
1034 acb = (struct AdapterControlBlock *) host->hostdata;
1035 memset(acb,0,sizeof(struct AdapterControlBlock));
1036 acb->pdev = pdev;
1037 acb->adapter_type = id->driver_data;
1038 if (arcmsr_set_dma_mask(acb))
1039 goto scsi_host_release;
1040 acb->host = host;
1041 host->max_lun = ARCMSR_MAX_TARGETLUN;
1042 host->max_id = ARCMSR_MAX_TARGETID;
1043 host->max_cmd_len = 16;
1044 if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD))
1045 host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
1046 host->can_queue = host_can_queue;
1047 if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN))
1048 cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
1049 host->cmd_per_lun = cmd_per_lun;
1050 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
1051 host->unique_id = (bus << 8) | dev_fun;
1052 pci_set_drvdata(pdev, host);
1053 pci_set_master(pdev);
1054 error = pci_request_regions(pdev, "arcmsr");
1055 if(error){
1056 goto scsi_host_release;
1057 }
1058 spin_lock_init(&acb->eh_lock);
1059 spin_lock_init(&acb->ccblist_lock);
1060 spin_lock_init(&acb->postq_lock);
1061 spin_lock_init(&acb->doneq_lock);
1062 spin_lock_init(&acb->rqbuffer_lock);
1063 spin_lock_init(&acb->wqbuffer_lock);
1064 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
1065 ACB_F_MESSAGE_RQBUFFER_CLEARED |
1066 ACB_F_MESSAGE_WQBUFFER_READED);
1067 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
1068 INIT_LIST_HEAD(&acb->ccb_free_list);
1069 error = arcmsr_remap_pciregion(acb);
1070 if(!error){
1071 goto pci_release_regs;
1072 }
1073 error = arcmsr_alloc_io_queue(acb);
1074 if (!error)
1075 goto unmap_pci_region;
1076 error = arcmsr_get_firmware_spec(acb);
1077 if(!error){
1078 goto free_hbb_mu;
1079 }
1080 if (acb->adapter_type != ACB_ADAPTER_TYPE_F)
1081 arcmsr_free_io_queue(acb);
1082 error = arcmsr_alloc_ccb_pool(acb);
1083 if(error){
1084 goto unmap_pci_region;
1085 }
1086 error = scsi_add_host(host, &pdev->dev);
1087 if(error){
1088 goto free_ccb_pool;
1089 }
1090 if (arcmsr_request_irq(pdev, acb) == FAILED)
1091 goto scsi_host_remove;
1092 arcmsr_iop_init(acb);
1093 arcmsr_init_get_devmap_timer(acb);
1094 if (set_date_time)
1095 arcmsr_init_set_datetime_timer(acb);
1096 if(arcmsr_alloc_sysfs_attr(acb))
1097 goto out_free_sysfs;
1098 scsi_scan_host(host);
1099 return 0;
1100out_free_sysfs:
1101 if (set_date_time)
1102 del_timer_sync(&acb->refresh_timer);
1103 del_timer_sync(&acb->eternal_timer);
1104 flush_work(&acb->arcmsr_do_message_isr_bh);
1105 arcmsr_stop_adapter_bgrb(acb);
1106 arcmsr_flush_adapter_cache(acb);
1107 arcmsr_free_irq(pdev, acb);
1108scsi_host_remove:
1109 scsi_remove_host(host);
1110free_ccb_pool:
1111 arcmsr_free_ccb_pool(acb);
1112 goto unmap_pci_region;
1113free_hbb_mu:
1114 arcmsr_free_io_queue(acb);
1115unmap_pci_region:
1116 arcmsr_unmap_pciregion(acb);
1117pci_release_regs:
1118 pci_release_regions(pdev);
1119scsi_host_release:
1120 scsi_host_put(host);
1121pci_disable_dev:
1122 pci_disable_device(pdev);
1123 return -ENODEV;
1124}
1125
1126static void arcmsr_free_irq(struct pci_dev *pdev,
1127 struct AdapterControlBlock *acb)
1128{
1129 int i;
1130
1131 for (i = 0; i < acb->vector_count; i++)
1132 free_irq(pci_irq_vector(pdev, i), acb);
1133 pci_free_irq_vectors(pdev);
1134}
1135
1136static int __maybe_unused arcmsr_suspend(struct device *dev)
1137{
1138 struct pci_dev *pdev = to_pci_dev(dev);
1139 struct Scsi_Host *host = pci_get_drvdata(pdev);
1140 struct AdapterControlBlock *acb =
1141 (struct AdapterControlBlock *)host->hostdata;
1142
1143 arcmsr_disable_outbound_ints(acb);
1144 arcmsr_free_irq(pdev, acb);
1145 del_timer_sync(&acb->eternal_timer);
1146 if (set_date_time)
1147 del_timer_sync(&acb->refresh_timer);
1148 flush_work(&acb->arcmsr_do_message_isr_bh);
1149 arcmsr_stop_adapter_bgrb(acb);
1150 arcmsr_flush_adapter_cache(acb);
1151 return 0;
1152}
1153
1154static int __maybe_unused arcmsr_resume(struct device *dev)
1155{
1156 struct pci_dev *pdev = to_pci_dev(dev);
1157 struct Scsi_Host *host = pci_get_drvdata(pdev);
1158 struct AdapterControlBlock *acb =
1159 (struct AdapterControlBlock *)host->hostdata;
1160
1161 if (arcmsr_set_dma_mask(acb))
1162 goto controller_unregister;
1163 if (arcmsr_request_irq(pdev, acb) == FAILED)
1164 goto controller_stop;
1165 switch (acb->adapter_type) {
1166 case ACB_ADAPTER_TYPE_B: {
1167 struct MessageUnit_B *reg = acb->pmuB;
1168 uint32_t i;
1169 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
1170 reg->post_qbuffer[i] = 0;
1171 reg->done_qbuffer[i] = 0;
1172 }
1173 reg->postq_index = 0;
1174 reg->doneq_index = 0;
1175 break;
1176 }
1177 case ACB_ADAPTER_TYPE_E:
1178 writel(0, &acb->pmuE->host_int_status);
1179 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell);
1180 acb->in_doorbell = 0;
1181 acb->out_doorbell = 0;
1182 acb->doneq_index = 0;
1183 break;
1184 case ACB_ADAPTER_TYPE_F:
1185 writel(0, &acb->pmuF->host_int_status);
1186 writel(ARCMSR_HBFMU_DOORBELL_SYNC, &acb->pmuF->iobound_doorbell);
1187 acb->in_doorbell = 0;
1188 acb->out_doorbell = 0;
1189 acb->doneq_index = 0;
1190 arcmsr_hbaF_assign_regAddr(acb);
1191 break;
1192 }
1193 arcmsr_iop_init(acb);
1194 arcmsr_init_get_devmap_timer(acb);
1195 if (set_date_time)
1196 arcmsr_init_set_datetime_timer(acb);
1197 return 0;
1198controller_stop:
1199 arcmsr_stop_adapter_bgrb(acb);
1200 arcmsr_flush_adapter_cache(acb);
1201controller_unregister:
1202 scsi_remove_host(host);
1203 arcmsr_free_ccb_pool(acb);
1204 if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
1205 arcmsr_free_io_queue(acb);
1206 arcmsr_unmap_pciregion(acb);
1207 scsi_host_put(host);
1208 return -ENODEV;
1209}
1210
1211static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
1212{
1213 struct MessageUnit_A __iomem *reg = acb->pmuA;
1214 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
1215 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1216 printk(KERN_NOTICE
1217 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1218 , acb->host->host_no);
1219 return false;
1220 }
1221 return true;
1222}
1223
1224static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
1225{
1226 struct MessageUnit_B *reg = acb->pmuB;
1227
1228 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
1229 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1230 printk(KERN_NOTICE
1231 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1232 , acb->host->host_no);
1233 return false;
1234 }
1235 return true;
1236}
1237static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
1238{
1239 struct MessageUnit_C __iomem *reg = pACB->pmuC;
1240 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
1241 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
1242 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
1243 printk(KERN_NOTICE
1244 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1245 , pACB->host->host_no);
1246 return false;
1247 }
1248 return true;
1249}
1250
1251static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
1252{
1253 struct MessageUnit_D *reg = pACB->pmuD;
1254
1255 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
1256 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
1257 pr_notice("arcmsr%d: wait 'abort all outstanding "
1258 "command' timeout\n", pACB->host->host_no);
1259 return false;
1260 }
1261 return true;
1262}
1263
1264static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB)
1265{
1266 struct MessageUnit_E __iomem *reg = pACB->pmuE;
1267
1268 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
1269 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1270 writel(pACB->out_doorbell, ®->iobound_doorbell);
1271 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
1272 pr_notice("arcmsr%d: wait 'abort all outstanding "
1273 "command' timeout\n", pACB->host->host_no);
1274 return false;
1275 }
1276 return true;
1277}
1278
1279static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
1280{
1281 uint8_t rtnval = 0;
1282 switch (acb->adapter_type) {
1283 case ACB_ADAPTER_TYPE_A:
1284 rtnval = arcmsr_hbaA_abort_allcmd(acb);
1285 break;
1286 case ACB_ADAPTER_TYPE_B:
1287 rtnval = arcmsr_hbaB_abort_allcmd(acb);
1288 break;
1289 case ACB_ADAPTER_TYPE_C:
1290 rtnval = arcmsr_hbaC_abort_allcmd(acb);
1291 break;
1292 case ACB_ADAPTER_TYPE_D:
1293 rtnval = arcmsr_hbaD_abort_allcmd(acb);
1294 break;
1295 case ACB_ADAPTER_TYPE_E:
1296 case ACB_ADAPTER_TYPE_F:
1297 rtnval = arcmsr_hbaE_abort_allcmd(acb);
1298 break;
1299 }
1300 return rtnval;
1301}
1302
1303static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
1304{
1305 struct scsi_cmnd *pcmd = ccb->pcmd;
1306
1307 scsi_dma_unmap(pcmd);
1308}
1309
1310static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
1311{
1312 struct AdapterControlBlock *acb = ccb->acb;
1313 struct scsi_cmnd *pcmd = ccb->pcmd;
1314 unsigned long flags;
1315 atomic_dec(&acb->ccboutstandingcount);
1316 arcmsr_pci_unmap_dma(ccb);
1317 ccb->startdone = ARCMSR_CCB_DONE;
1318 spin_lock_irqsave(&acb->ccblist_lock, flags);
1319 list_add_tail(&ccb->list, &acb->ccb_free_list);
1320 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1321 pcmd->scsi_done(pcmd);
1322}
1323
1324static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
1325{
1326
1327 struct scsi_cmnd *pcmd = ccb->pcmd;
1328 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
1329 pcmd->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
1330 if (sensebuffer) {
1331 int sense_data_length =
1332 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
1333 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
1334 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
1335 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
1336 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
1337 sensebuffer->Valid = 1;
1338 pcmd->result |= (DRIVER_SENSE << 24);
1339 }
1340}
1341
1342static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
1343{
1344 u32 orig_mask = 0;
1345 switch (acb->adapter_type) {
1346 case ACB_ADAPTER_TYPE_A : {
1347 struct MessageUnit_A __iomem *reg = acb->pmuA;
1348 orig_mask = readl(®->outbound_intmask);
1349 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
1350 ®->outbound_intmask);
1351 }
1352 break;
1353 case ACB_ADAPTER_TYPE_B : {
1354 struct MessageUnit_B *reg = acb->pmuB;
1355 orig_mask = readl(reg->iop2drv_doorbell_mask);
1356 writel(0, reg->iop2drv_doorbell_mask);
1357 }
1358 break;
1359 case ACB_ADAPTER_TYPE_C:{
1360 struct MessageUnit_C __iomem *reg = acb->pmuC;
1361
1362 orig_mask = readl(®->host_int_mask);
1363 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask);
1364 }
1365 break;
1366 case ACB_ADAPTER_TYPE_D: {
1367 struct MessageUnit_D *reg = acb->pmuD;
1368
1369 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
1370 }
1371 break;
1372 case ACB_ADAPTER_TYPE_E:
1373 case ACB_ADAPTER_TYPE_F: {
1374 struct MessageUnit_E __iomem *reg = acb->pmuE;
1375 orig_mask = readl(®->host_int_mask);
1376 writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, ®->host_int_mask);
1377 readl(®->host_int_mask);
1378 }
1379 break;
1380 }
1381 return orig_mask;
1382}
1383
1384static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
1385 struct CommandControlBlock *ccb, bool error)
1386{
1387 uint8_t id, lun;
1388 id = ccb->pcmd->device->id;
1389 lun = ccb->pcmd->device->lun;
1390 if (!error) {
1391 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
1392 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1393 ccb->pcmd->result = DID_OK << 16;
1394 arcmsr_ccb_complete(ccb);
1395 }else{
1396 switch (ccb->arcmsr_cdb.DeviceStatus) {
1397 case ARCMSR_DEV_SELECT_TIMEOUT: {
1398 acb->devstate[id][lun] = ARECA_RAID_GONE;
1399 ccb->pcmd->result = DID_NO_CONNECT << 16;
1400 arcmsr_ccb_complete(ccb);
1401 }
1402 break;
1403
1404 case ARCMSR_DEV_ABORTED:
1405
1406 case ARCMSR_DEV_INIT_FAIL: {
1407 acb->devstate[id][lun] = ARECA_RAID_GONE;
1408 ccb->pcmd->result = DID_BAD_TARGET << 16;
1409 arcmsr_ccb_complete(ccb);
1410 }
1411 break;
1412
1413 case ARCMSR_DEV_CHECK_CONDITION: {
1414 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1415 arcmsr_report_sense_info(ccb);
1416 arcmsr_ccb_complete(ccb);
1417 }
1418 break;
1419
1420 default:
1421 printk(KERN_NOTICE
1422 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
1423 but got unknown DeviceStatus = 0x%x \n"
1424 , acb->host->host_no
1425 , id
1426 , lun
1427 , ccb->arcmsr_cdb.DeviceStatus);
1428 acb->devstate[id][lun] = ARECA_RAID_GONE;
1429 ccb->pcmd->result = DID_NO_CONNECT << 16;
1430 arcmsr_ccb_complete(ccb);
1431 break;
1432 }
1433 }
1434}
1435
1436static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1437{
1438 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
1439 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
1440 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1441 if (abortcmd) {
1442 abortcmd->result |= DID_ABORT << 16;
1443 arcmsr_ccb_complete(pCCB);
1444 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
1445 acb->host->host_no, pCCB);
1446 }
1447 return;
1448 }
1449 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
1450 done acb = '0x%p'"
1451 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
1452 " ccboutstandingcount = %d \n"
1453 , acb->host->host_no
1454 , acb
1455 , pCCB
1456 , pCCB->acb
1457 , pCCB->startdone
1458 , atomic_read(&acb->ccboutstandingcount));
1459 return;
1460 }
1461 arcmsr_report_ccb_state(acb, pCCB, error);
1462}
1463
1464static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
1465{
1466 int i = 0;
1467 uint32_t flag_ccb;
1468 struct ARCMSR_CDB *pARCMSR_CDB;
1469 bool error;
1470 struct CommandControlBlock *pCCB;
1471 unsigned long ccb_cdb_phy;
1472
1473 switch (acb->adapter_type) {
1474
1475 case ACB_ADAPTER_TYPE_A: {
1476 struct MessageUnit_A __iomem *reg = acb->pmuA;
1477 uint32_t outbound_intstatus;
1478 outbound_intstatus = readl(®->outbound_intstatus) &
1479 acb->outbound_int_enable;
1480
1481 writel(outbound_intstatus, ®->outbound_intstatus);
1482 while(((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF)
1483 && (i++ < acb->maxOutstanding)) {
1484 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
1485 if (acb->cdb_phyadd_hipart)
1486 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
1487 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
1488 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1489 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1490 arcmsr_drain_donequeue(acb, pCCB, error);
1491 }
1492 }
1493 break;
1494
1495 case ACB_ADAPTER_TYPE_B: {
1496 struct MessageUnit_B *reg = acb->pmuB;
1497
1498 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
1499 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
1500 flag_ccb = reg->done_qbuffer[i];
1501 if (flag_ccb != 0) {
1502 reg->done_qbuffer[i] = 0;
1503 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
1504 if (acb->cdb_phyadd_hipart)
1505 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
1506 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
1507 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1508 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1509 arcmsr_drain_donequeue(acb, pCCB, error);
1510 }
1511 reg->post_qbuffer[i] = 0;
1512 }
1513 reg->doneq_index = 0;
1514 reg->postq_index = 0;
1515 }
1516 break;
1517 case ACB_ADAPTER_TYPE_C: {
1518 struct MessageUnit_C __iomem *reg = acb->pmuC;
1519 while ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) {
1520
1521 flag_ccb = readl(®->outbound_queueport_low);
1522 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
1523 if (acb->cdb_phyadd_hipart)
1524 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
1525 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
1526 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1527 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1528 arcmsr_drain_donequeue(acb, pCCB, error);
1529 }
1530 }
1531 break;
1532 case ACB_ADAPTER_TYPE_D: {
1533 struct MessageUnit_D *pmu = acb->pmuD;
1534 uint32_t outbound_write_pointer;
1535 uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
1536 unsigned long flags;
1537
1538 residual = atomic_read(&acb->ccboutstandingcount);
1539 for (i = 0; i < residual; i++) {
1540 spin_lock_irqsave(&acb->doneq_lock, flags);
1541 outbound_write_pointer =
1542 pmu->done_qbuffer[0].addressLow + 1;
1543 doneq_index = pmu->doneq_index;
1544 if ((doneq_index & 0xFFF) !=
1545 (outbound_write_pointer & 0xFFF)) {
1546 toggle = doneq_index & 0x4000;
1547 index_stripped = (doneq_index & 0xFFF) + 1;
1548 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
1549 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
1550 ((toggle ^ 0x4000) + 1);
1551 doneq_index = pmu->doneq_index;
1552 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1553 addressLow = pmu->done_qbuffer[doneq_index &
1554 0xFFF].addressLow;
1555 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
1556 if (acb->cdb_phyadd_hipart)
1557 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
1558 pARCMSR_CDB = (struct ARCMSR_CDB *)
1559 (acb->vir2phy_offset + ccb_cdb_phy);
1560 pCCB = container_of(pARCMSR_CDB,
1561 struct CommandControlBlock, arcmsr_cdb);
1562 error = (addressLow &
1563 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
1564 true : false;
1565 arcmsr_drain_donequeue(acb, pCCB, error);
1566 writel(doneq_index,
1567 pmu->outboundlist_read_pointer);
1568 } else {
1569 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1570 mdelay(10);
1571 }
1572 }
1573 pmu->postq_index = 0;
1574 pmu->doneq_index = 0x40FF;
1575 }
1576 break;
1577 case ACB_ADAPTER_TYPE_E:
1578 arcmsr_hbaE_postqueue_isr(acb);
1579 break;
1580 case ACB_ADAPTER_TYPE_F:
1581 arcmsr_hbaF_postqueue_isr(acb);
1582 break;
1583 }
1584}
1585
1586static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb)
1587{
1588 char *acb_dev_map = (char *)acb->device_map;
1589 int target, lun, i;
1590 struct scsi_device *psdev;
1591 struct CommandControlBlock *ccb;
1592 char temp;
1593
1594 for (i = 0; i < acb->maxFreeCCB; i++) {
1595 ccb = acb->pccb_pool[i];
1596 if (ccb->startdone == ARCMSR_CCB_START) {
1597 ccb->pcmd->result = DID_NO_CONNECT << 16;
1598 arcmsr_pci_unmap_dma(ccb);
1599 ccb->pcmd->scsi_done(ccb->pcmd);
1600 }
1601 }
1602 for (target = 0; target < ARCMSR_MAX_TARGETID; target++) {
1603 temp = *acb_dev_map;
1604 if (temp) {
1605 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
1606 if (temp & 1) {
1607 psdev = scsi_device_lookup(acb->host,
1608 0, target, lun);
1609 if (psdev != NULL) {
1610 scsi_remove_device(psdev);
1611 scsi_device_put(psdev);
1612 }
1613 }
1614 temp >>= 1;
1615 }
1616 *acb_dev_map = 0;
1617 }
1618 acb_dev_map++;
1619 }
1620}
1621
1622static void arcmsr_free_pcidev(struct AdapterControlBlock *acb)
1623{
1624 struct pci_dev *pdev;
1625 struct Scsi_Host *host;
1626
1627 host = acb->host;
1628 arcmsr_free_sysfs_attr(acb);
1629 scsi_remove_host(host);
1630 flush_work(&acb->arcmsr_do_message_isr_bh);
1631 del_timer_sync(&acb->eternal_timer);
1632 if (set_date_time)
1633 del_timer_sync(&acb->refresh_timer);
1634 pdev = acb->pdev;
1635 arcmsr_free_irq(pdev, acb);
1636 arcmsr_free_ccb_pool(acb);
1637 if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
1638 arcmsr_free_io_queue(acb);
1639 arcmsr_unmap_pciregion(acb);
1640 pci_release_regions(pdev);
1641 scsi_host_put(host);
1642 pci_disable_device(pdev);
1643}
1644
1645static void arcmsr_remove(struct pci_dev *pdev)
1646{
1647 struct Scsi_Host *host = pci_get_drvdata(pdev);
1648 struct AdapterControlBlock *acb =
1649 (struct AdapterControlBlock *) host->hostdata;
1650 int poll_count = 0;
1651 uint16_t dev_id;
1652
1653 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
1654 if (dev_id == 0xffff) {
1655 acb->acb_flags &= ~ACB_F_IOP_INITED;
1656 acb->acb_flags |= ACB_F_ADAPTER_REMOVED;
1657 arcmsr_remove_scsi_devices(acb);
1658 arcmsr_free_pcidev(acb);
1659 return;
1660 }
1661 arcmsr_free_sysfs_attr(acb);
1662 scsi_remove_host(host);
1663 flush_work(&acb->arcmsr_do_message_isr_bh);
1664 del_timer_sync(&acb->eternal_timer);
1665 if (set_date_time)
1666 del_timer_sync(&acb->refresh_timer);
1667 arcmsr_disable_outbound_ints(acb);
1668 arcmsr_stop_adapter_bgrb(acb);
1669 arcmsr_flush_adapter_cache(acb);
1670 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1671 acb->acb_flags &= ~ACB_F_IOP_INITED;
1672
1673 for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){
1674 if (!atomic_read(&acb->ccboutstandingcount))
1675 break;
1676 arcmsr_interrupt(acb);
1677 msleep(25);
1678 }
1679
1680 if (atomic_read(&acb->ccboutstandingcount)) {
1681 int i;
1682
1683 arcmsr_abort_allcmd(acb);
1684 arcmsr_done4abort_postqueue(acb);
1685 for (i = 0; i < acb->maxFreeCCB; i++) {
1686 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1687 if (ccb->startdone == ARCMSR_CCB_START) {
1688 ccb->startdone = ARCMSR_CCB_ABORTED;
1689 ccb->pcmd->result = DID_ABORT << 16;
1690 arcmsr_ccb_complete(ccb);
1691 }
1692 }
1693 }
1694 arcmsr_free_irq(pdev, acb);
1695 arcmsr_free_ccb_pool(acb);
1696 if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
1697 arcmsr_free_io_queue(acb);
1698 arcmsr_unmap_pciregion(acb);
1699 pci_release_regions(pdev);
1700 scsi_host_put(host);
1701 pci_disable_device(pdev);
1702}
1703
1704static void arcmsr_shutdown(struct pci_dev *pdev)
1705{
1706 struct Scsi_Host *host = pci_get_drvdata(pdev);
1707 struct AdapterControlBlock *acb =
1708 (struct AdapterControlBlock *)host->hostdata;
1709 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
1710 return;
1711 del_timer_sync(&acb->eternal_timer);
1712 if (set_date_time)
1713 del_timer_sync(&acb->refresh_timer);
1714 arcmsr_disable_outbound_ints(acb);
1715 arcmsr_free_irq(pdev, acb);
1716 flush_work(&acb->arcmsr_do_message_isr_bh);
1717 arcmsr_stop_adapter_bgrb(acb);
1718 arcmsr_flush_adapter_cache(acb);
1719}
1720
1721static int arcmsr_module_init(void)
1722{
1723 int error = 0;
1724 error = pci_register_driver(&arcmsr_pci_driver);
1725 return error;
1726}
1727
1728static void arcmsr_module_exit(void)
1729{
1730 pci_unregister_driver(&arcmsr_pci_driver);
1731}
1732module_init(arcmsr_module_init);
1733module_exit(arcmsr_module_exit);
1734
1735static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1736 u32 intmask_org)
1737{
1738 u32 mask;
1739 switch (acb->adapter_type) {
1740
1741 case ACB_ADAPTER_TYPE_A: {
1742 struct MessageUnit_A __iomem *reg = acb->pmuA;
1743 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
1744 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1745 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1746 writel(mask, ®->outbound_intmask);
1747 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1748 }
1749 break;
1750
1751 case ACB_ADAPTER_TYPE_B: {
1752 struct MessageUnit_B *reg = acb->pmuB;
1753 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1754 ARCMSR_IOP2DRV_DATA_READ_OK |
1755 ARCMSR_IOP2DRV_CDB_DONE |
1756 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
1757 writel(mask, reg->iop2drv_doorbell_mask);
1758 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1759 }
1760 break;
1761 case ACB_ADAPTER_TYPE_C: {
1762 struct MessageUnit_C __iomem *reg = acb->pmuC;
1763 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1764 writel(intmask_org & mask, ®->host_int_mask);
1765 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1766 }
1767 break;
1768 case ACB_ADAPTER_TYPE_D: {
1769 struct MessageUnit_D *reg = acb->pmuD;
1770
1771 mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
1772 writel(intmask_org | mask, reg->pcief0_int_enable);
1773 break;
1774 }
1775 case ACB_ADAPTER_TYPE_E:
1776 case ACB_ADAPTER_TYPE_F: {
1777 struct MessageUnit_E __iomem *reg = acb->pmuE;
1778
1779 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
1780 writel(intmask_org & mask, ®->host_int_mask);
1781 break;
1782 }
1783 }
1784}
1785
1786static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1787 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1788{
1789 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1790 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
1791 __le32 address_lo, address_hi;
1792 int arccdbsize = 0x30;
1793 __le32 length = 0;
1794 int i;
1795 struct scatterlist *sg;
1796 int nseg;
1797 ccb->pcmd = pcmd;
1798 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1799 arcmsr_cdb->TargetID = pcmd->device->id;
1800 arcmsr_cdb->LUN = pcmd->device->lun;
1801 arcmsr_cdb->Function = 1;
1802 arcmsr_cdb->msgContext = 0;
1803 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
1804
1805 nseg = scsi_dma_map(pcmd);
1806 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
1807 return FAILED;
1808 scsi_for_each_sg(pcmd, sg, nseg, i) {
1809
1810 length = cpu_to_le32(sg_dma_len(sg));
1811 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1812 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1813 if (address_hi == 0) {
1814 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1815
1816 pdma_sg->address = address_lo;
1817 pdma_sg->length = length;
1818 psge += sizeof (struct SG32ENTRY);
1819 arccdbsize += sizeof (struct SG32ENTRY);
1820 } else {
1821 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1822
1823 pdma_sg->addresshigh = address_hi;
1824 pdma_sg->address = address_lo;
1825 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1826 psge += sizeof (struct SG64ENTRY);
1827 arccdbsize += sizeof (struct SG64ENTRY);
1828 }
1829 }
1830 arcmsr_cdb->sgcount = (uint8_t)nseg;
1831 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
1832 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
1833 if ( arccdbsize > 256)
1834 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1835 if (pcmd->sc_data_direction == DMA_TO_DEVICE)
1836 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1837 ccb->arc_cdb_size = arccdbsize;
1838 return SUCCESS;
1839}
1840
1841static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1842{
1843 uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
1844 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1845 atomic_inc(&acb->ccboutstandingcount);
1846 ccb->startdone = ARCMSR_CCB_START;
1847 switch (acb->adapter_type) {
1848 case ACB_ADAPTER_TYPE_A: {
1849 struct MessageUnit_A __iomem *reg = acb->pmuA;
1850
1851 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
1852 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1853 ®->inbound_queueport);
1854 else
1855 writel(cdb_phyaddr, ®->inbound_queueport);
1856 break;
1857 }
1858
1859 case ACB_ADAPTER_TYPE_B: {
1860 struct MessageUnit_B *reg = acb->pmuB;
1861 uint32_t ending_index, index = reg->postq_index;
1862
1863 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
1864 reg->post_qbuffer[ending_index] = 0;
1865 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1866 reg->post_qbuffer[index] =
1867 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
1868 } else {
1869 reg->post_qbuffer[index] = cdb_phyaddr;
1870 }
1871 index++;
1872 index %= ARCMSR_MAX_HBB_POSTQUEUE;
1873 reg->postq_index = index;
1874 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1875 }
1876 break;
1877 case ACB_ADAPTER_TYPE_C: {
1878 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
1879 uint32_t ccb_post_stamp, arc_cdb_size;
1880
1881 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1882 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
1883 writel(upper_32_bits(ccb->cdb_phyaddr), &phbcmu->inbound_queueport_high);
1884 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1885 }
1886 break;
1887 case ACB_ADAPTER_TYPE_D: {
1888 struct MessageUnit_D *pmu = acb->pmuD;
1889 u16 index_stripped;
1890 u16 postq_index, toggle;
1891 unsigned long flags;
1892 struct InBound_SRB *pinbound_srb;
1893
1894 spin_lock_irqsave(&acb->postq_lock, flags);
1895 postq_index = pmu->postq_index;
1896 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
1897 pinbound_srb->addressHigh = upper_32_bits(ccb->cdb_phyaddr);
1898 pinbound_srb->addressLow = cdb_phyaddr;
1899 pinbound_srb->length = ccb->arc_cdb_size >> 2;
1900 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
1901 toggle = postq_index & 0x4000;
1902 index_stripped = postq_index + 1;
1903 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
1904 pmu->postq_index = index_stripped ? (index_stripped | toggle) :
1905 (toggle ^ 0x4000);
1906 writel(postq_index, pmu->inboundlist_write_pointer);
1907 spin_unlock_irqrestore(&acb->postq_lock, flags);
1908 break;
1909 }
1910 case ACB_ADAPTER_TYPE_E: {
1911 struct MessageUnit_E __iomem *pmu = acb->pmuE;
1912 u32 ccb_post_stamp, arc_cdb_size;
1913
1914 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1915 ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6));
1916 writel(0, &pmu->inbound_queueport_high);
1917 writel(ccb_post_stamp, &pmu->inbound_queueport_low);
1918 break;
1919 }
1920 case ACB_ADAPTER_TYPE_F: {
1921 struct MessageUnit_F __iomem *pmu = acb->pmuF;
1922 u32 ccb_post_stamp, arc_cdb_size;
1923
1924 if (ccb->arc_cdb_size <= 0x300)
1925 arc_cdb_size = (ccb->arc_cdb_size - 1) >> 6 | 1;
1926 else
1927 arc_cdb_size = (((ccb->arc_cdb_size + 0xff) >> 8) + 2) << 1 | 1;
1928 ccb_post_stamp = (ccb->smid | arc_cdb_size);
1929 writel(0, &pmu->inbound_queueport_high);
1930 writel(ccb_post_stamp, &pmu->inbound_queueport_low);
1931 break;
1932 }
1933 }
1934}
1935
1936static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
1937{
1938 struct MessageUnit_A __iomem *reg = acb->pmuA;
1939 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1940 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
1941 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1942 printk(KERN_NOTICE
1943 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
1944 , acb->host->host_no);
1945 }
1946}
1947
1948static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
1949{
1950 struct MessageUnit_B *reg = acb->pmuB;
1951 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1952 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1953
1954 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1955 printk(KERN_NOTICE
1956 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
1957 , acb->host->host_no);
1958 }
1959}
1960
1961static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
1962{
1963 struct MessageUnit_C __iomem *reg = pACB->pmuC;
1964 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1965 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
1966 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
1967 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
1968 printk(KERN_NOTICE
1969 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
1970 , pACB->host->host_no);
1971 }
1972 return;
1973}
1974
1975static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
1976{
1977 struct MessageUnit_D *reg = pACB->pmuD;
1978
1979 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1980 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
1981 if (!arcmsr_hbaD_wait_msgint_ready(pACB))
1982 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' "
1983 "timeout\n", pACB->host->host_no);
1984}
1985
1986static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB)
1987{
1988 struct MessageUnit_E __iomem *reg = pACB->pmuE;
1989
1990 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1991 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
1992 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1993 writel(pACB->out_doorbell, ®->iobound_doorbell);
1994 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
1995 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' "
1996 "timeout\n", pACB->host->host_no);
1997 }
1998}
1999
2000static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
2001{
2002 switch (acb->adapter_type) {
2003 case ACB_ADAPTER_TYPE_A:
2004 arcmsr_hbaA_stop_bgrb(acb);
2005 break;
2006 case ACB_ADAPTER_TYPE_B:
2007 arcmsr_hbaB_stop_bgrb(acb);
2008 break;
2009 case ACB_ADAPTER_TYPE_C:
2010 arcmsr_hbaC_stop_bgrb(acb);
2011 break;
2012 case ACB_ADAPTER_TYPE_D:
2013 arcmsr_hbaD_stop_bgrb(acb);
2014 break;
2015 case ACB_ADAPTER_TYPE_E:
2016 case ACB_ADAPTER_TYPE_F:
2017 arcmsr_hbaE_stop_bgrb(acb);
2018 break;
2019 }
2020}
2021
2022static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
2023{
2024 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
2025}
2026
2027static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
2028{
2029 switch (acb->adapter_type) {
2030 case ACB_ADAPTER_TYPE_A: {
2031 struct MessageUnit_A __iomem *reg = acb->pmuA;
2032 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell);
2033 }
2034 break;
2035 case ACB_ADAPTER_TYPE_B: {
2036 struct MessageUnit_B *reg = acb->pmuB;
2037 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
2038 }
2039 break;
2040 case ACB_ADAPTER_TYPE_C: {
2041 struct MessageUnit_C __iomem *reg = acb->pmuC;
2042
2043 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell);
2044 }
2045 break;
2046 case ACB_ADAPTER_TYPE_D: {
2047 struct MessageUnit_D *reg = acb->pmuD;
2048 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
2049 reg->inbound_doorbell);
2050 }
2051 break;
2052 case ACB_ADAPTER_TYPE_E:
2053 case ACB_ADAPTER_TYPE_F: {
2054 struct MessageUnit_E __iomem *reg = acb->pmuE;
2055 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
2056 writel(acb->out_doorbell, ®->iobound_doorbell);
2057 }
2058 break;
2059 }
2060}
2061
2062static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
2063{
2064 switch (acb->adapter_type) {
2065 case ACB_ADAPTER_TYPE_A: {
2066 struct MessageUnit_A __iomem *reg = acb->pmuA;
2067
2068
2069
2070
2071 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, ®->inbound_doorbell);
2072 }
2073 break;
2074
2075 case ACB_ADAPTER_TYPE_B: {
2076 struct MessageUnit_B *reg = acb->pmuB;
2077
2078
2079
2080
2081 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
2082 }
2083 break;
2084 case ACB_ADAPTER_TYPE_C: {
2085 struct MessageUnit_C __iomem *reg = acb->pmuC;
2086
2087
2088
2089
2090 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, ®->inbound_doorbell);
2091 }
2092 break;
2093 case ACB_ADAPTER_TYPE_D: {
2094 struct MessageUnit_D *reg = acb->pmuD;
2095 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
2096 reg->inbound_doorbell);
2097 }
2098 break;
2099 case ACB_ADAPTER_TYPE_E:
2100 case ACB_ADAPTER_TYPE_F: {
2101 struct MessageUnit_E __iomem *reg = acb->pmuE;
2102 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
2103 writel(acb->out_doorbell, ®->iobound_doorbell);
2104 }
2105 break;
2106 }
2107}
2108
2109struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
2110{
2111 struct QBUFFER __iomem *qbuffer = NULL;
2112 switch (acb->adapter_type) {
2113
2114 case ACB_ADAPTER_TYPE_A: {
2115 struct MessageUnit_A __iomem *reg = acb->pmuA;
2116 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer;
2117 }
2118 break;
2119 case ACB_ADAPTER_TYPE_B: {
2120 struct MessageUnit_B *reg = acb->pmuB;
2121 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
2122 }
2123 break;
2124 case ACB_ADAPTER_TYPE_C: {
2125 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
2126 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
2127 }
2128 break;
2129 case ACB_ADAPTER_TYPE_D: {
2130 struct MessageUnit_D *reg = acb->pmuD;
2131 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
2132 }
2133 break;
2134 case ACB_ADAPTER_TYPE_E: {
2135 struct MessageUnit_E __iomem *reg = acb->pmuE;
2136 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer;
2137 }
2138 break;
2139 case ACB_ADAPTER_TYPE_F: {
2140 qbuffer = (struct QBUFFER __iomem *)acb->message_rbuffer;
2141 }
2142 break;
2143 }
2144 return qbuffer;
2145}
2146
2147static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
2148{
2149 struct QBUFFER __iomem *pqbuffer = NULL;
2150 switch (acb->adapter_type) {
2151
2152 case ACB_ADAPTER_TYPE_A: {
2153 struct MessageUnit_A __iomem *reg = acb->pmuA;
2154 pqbuffer = (struct QBUFFER __iomem *) ®->message_wbuffer;
2155 }
2156 break;
2157 case ACB_ADAPTER_TYPE_B: {
2158 struct MessageUnit_B *reg = acb->pmuB;
2159 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
2160 }
2161 break;
2162 case ACB_ADAPTER_TYPE_C: {
2163 struct MessageUnit_C __iomem *reg = acb->pmuC;
2164 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer;
2165 }
2166 break;
2167 case ACB_ADAPTER_TYPE_D: {
2168 struct MessageUnit_D *reg = acb->pmuD;
2169 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
2170 }
2171 break;
2172 case ACB_ADAPTER_TYPE_E: {
2173 struct MessageUnit_E __iomem *reg = acb->pmuE;
2174 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer;
2175 }
2176 break;
2177 case ACB_ADAPTER_TYPE_F:
2178 pqbuffer = (struct QBUFFER __iomem *)acb->message_wbuffer;
2179 break;
2180 }
2181 return pqbuffer;
2182}
2183
2184static uint32_t
2185arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
2186 struct QBUFFER __iomem *prbuffer)
2187{
2188 uint8_t *pQbuffer;
2189 uint8_t *buf1 = NULL;
2190 uint32_t __iomem *iop_data;
2191 uint32_t iop_len, data_len, *buf2 = NULL;
2192
2193 iop_data = (uint32_t __iomem *)prbuffer->data;
2194 iop_len = readl(&prbuffer->data_len);
2195 if (iop_len > 0) {
2196 buf1 = kmalloc(128, GFP_ATOMIC);
2197 buf2 = (uint32_t *)buf1;
2198 if (buf1 == NULL)
2199 return 0;
2200 data_len = iop_len;
2201 while (data_len >= 4) {
2202 *buf2++ = readl(iop_data);
2203 iop_data++;
2204 data_len -= 4;
2205 }
2206 if (data_len)
2207 *buf2 = readl(iop_data);
2208 buf2 = (uint32_t *)buf1;
2209 }
2210 while (iop_len > 0) {
2211 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
2212 *pQbuffer = *buf1;
2213 acb->rqbuf_putIndex++;
2214
2215 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
2216 buf1++;
2217 iop_len--;
2218 }
2219 kfree(buf2);
2220
2221 arcmsr_iop_message_read(acb);
2222 return 1;
2223}
2224
2225uint32_t
2226arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
2227 struct QBUFFER __iomem *prbuffer) {
2228
2229 uint8_t *pQbuffer;
2230 uint8_t __iomem *iop_data;
2231 uint32_t iop_len;
2232
2233 if (acb->adapter_type > ACB_ADAPTER_TYPE_B)
2234 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
2235 iop_data = (uint8_t __iomem *)prbuffer->data;
2236 iop_len = readl(&prbuffer->data_len);
2237 while (iop_len > 0) {
2238 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
2239 *pQbuffer = readb(iop_data);
2240 acb->rqbuf_putIndex++;
2241 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
2242 iop_data++;
2243 iop_len--;
2244 }
2245 arcmsr_iop_message_read(acb);
2246 return 1;
2247}
2248
2249static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
2250{
2251 unsigned long flags;
2252 struct QBUFFER __iomem *prbuffer;
2253 int32_t buf_empty_len;
2254
2255 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2256 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2257 buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
2258 (ARCMSR_MAX_QBUFFER - 1);
2259 if (buf_empty_len >= readl(&prbuffer->data_len)) {
2260 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2261 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2262 } else
2263 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2264 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2265}
2266
2267static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
2268{
2269 uint8_t *pQbuffer;
2270 struct QBUFFER __iomem *pwbuffer;
2271 uint8_t *buf1 = NULL;
2272 uint32_t __iomem *iop_data;
2273 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
2274
2275 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
2276 buf1 = kmalloc(128, GFP_ATOMIC);
2277 buf2 = (uint32_t *)buf1;
2278 if (buf1 == NULL)
2279 return;
2280
2281 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
2282 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
2283 iop_data = (uint32_t __iomem *)pwbuffer->data;
2284 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
2285 && (allxfer_len < 124)) {
2286 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
2287 *buf1 = *pQbuffer;
2288 acb->wqbuf_getIndex++;
2289 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
2290 buf1++;
2291 allxfer_len++;
2292 }
2293 data_len = allxfer_len;
2294 buf1 = (uint8_t *)buf2;
2295 while (data_len >= 4) {
2296 data = *buf2++;
2297 writel(data, iop_data);
2298 iop_data++;
2299 data_len -= 4;
2300 }
2301 if (data_len) {
2302 data = *buf2;
2303 writel(data, iop_data);
2304 }
2305 writel(allxfer_len, &pwbuffer->data_len);
2306 kfree(buf1);
2307 arcmsr_iop_message_wrote(acb);
2308 }
2309}
2310
2311void
2312arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
2313{
2314 uint8_t *pQbuffer;
2315 struct QBUFFER __iomem *pwbuffer;
2316 uint8_t __iomem *iop_data;
2317 int32_t allxfer_len = 0;
2318
2319 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) {
2320 arcmsr_write_ioctldata2iop_in_DWORD(acb);
2321 return;
2322 }
2323 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
2324 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
2325 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
2326 iop_data = (uint8_t __iomem *)pwbuffer->data;
2327 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
2328 && (allxfer_len < 124)) {
2329 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
2330 writeb(*pQbuffer, iop_data);
2331 acb->wqbuf_getIndex++;
2332 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
2333 iop_data++;
2334 allxfer_len++;
2335 }
2336 writel(allxfer_len, &pwbuffer->data_len);
2337 arcmsr_iop_message_wrote(acb);
2338 }
2339}
2340
2341static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
2342{
2343 unsigned long flags;
2344
2345 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2346 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
2347 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
2348 arcmsr_write_ioctldata2iop(acb);
2349 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
2350 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
2351 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2352}
2353
2354static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
2355{
2356 uint32_t outbound_doorbell;
2357 struct MessageUnit_A __iomem *reg = acb->pmuA;
2358 outbound_doorbell = readl(®->outbound_doorbell);
2359 do {
2360 writel(outbound_doorbell, ®->outbound_doorbell);
2361 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
2362 arcmsr_iop2drv_data_wrote_handle(acb);
2363 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
2364 arcmsr_iop2drv_data_read_handle(acb);
2365 outbound_doorbell = readl(®->outbound_doorbell);
2366 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
2367 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
2368}
2369static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
2370{
2371 uint32_t outbound_doorbell;
2372 struct MessageUnit_C __iomem *reg = pACB->pmuC;
2373
2374
2375
2376
2377
2378
2379
2380 outbound_doorbell = readl(®->outbound_doorbell);
2381 do {
2382 writel(outbound_doorbell, ®->outbound_doorbell_clear);
2383 readl(®->outbound_doorbell_clear);
2384 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
2385 arcmsr_iop2drv_data_wrote_handle(pACB);
2386 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
2387 arcmsr_iop2drv_data_read_handle(pACB);
2388 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
2389 arcmsr_hbaC_message_isr(pACB);
2390 outbound_doorbell = readl(®->outbound_doorbell);
2391 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
2392 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
2393 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
2394}
2395
2396static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
2397{
2398 uint32_t outbound_doorbell;
2399 struct MessageUnit_D *pmu = pACB->pmuD;
2400
2401 outbound_doorbell = readl(pmu->outbound_doorbell);
2402 do {
2403 writel(outbound_doorbell, pmu->outbound_doorbell);
2404 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
2405 arcmsr_hbaD_message_isr(pACB);
2406 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
2407 arcmsr_iop2drv_data_wrote_handle(pACB);
2408 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
2409 arcmsr_iop2drv_data_read_handle(pACB);
2410 outbound_doorbell = readl(pmu->outbound_doorbell);
2411 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
2412 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
2413 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
2414}
2415
2416static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB)
2417{
2418 uint32_t outbound_doorbell, in_doorbell, tmp;
2419 struct MessageUnit_E __iomem *reg = pACB->pmuE;
2420
2421 in_doorbell = readl(®->iobound_doorbell);
2422 outbound_doorbell = in_doorbell ^ pACB->in_doorbell;
2423 do {
2424 writel(0, ®->host_int_status);
2425 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2426 arcmsr_iop2drv_data_wrote_handle(pACB);
2427 }
2428 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2429 arcmsr_iop2drv_data_read_handle(pACB);
2430 }
2431 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2432 arcmsr_hbaE_message_isr(pACB);
2433 }
2434 tmp = in_doorbell;
2435 in_doorbell = readl(®->iobound_doorbell);
2436 outbound_doorbell = tmp ^ in_doorbell;
2437 } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK
2438 | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK
2439 | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE));
2440 pACB->in_doorbell = in_doorbell;
2441}
2442
2443static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
2444{
2445 uint32_t flag_ccb;
2446 struct MessageUnit_A __iomem *reg = acb->pmuA;
2447 struct ARCMSR_CDB *pARCMSR_CDB;
2448 struct CommandControlBlock *pCCB;
2449 bool error;
2450 unsigned long cdb_phy_addr;
2451
2452 while ((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) {
2453 cdb_phy_addr = (flag_ccb << 5) & 0xffffffff;
2454 if (acb->cdb_phyadd_hipart)
2455 cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart;
2456 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr);
2457 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
2458 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2459 arcmsr_drain_donequeue(acb, pCCB, error);
2460 }
2461}
2462static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
2463{
2464 uint32_t index;
2465 uint32_t flag_ccb;
2466 struct MessageUnit_B *reg = acb->pmuB;
2467 struct ARCMSR_CDB *pARCMSR_CDB;
2468 struct CommandControlBlock *pCCB;
2469 bool error;
2470 unsigned long cdb_phy_addr;
2471
2472 index = reg->doneq_index;
2473 while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
2474 cdb_phy_addr = (flag_ccb << 5) & 0xffffffff;
2475 if (acb->cdb_phyadd_hipart)
2476 cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart;
2477 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr);
2478 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
2479 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2480 arcmsr_drain_donequeue(acb, pCCB, error);
2481 reg->done_qbuffer[index] = 0;
2482 index++;
2483 index %= ARCMSR_MAX_HBB_POSTQUEUE;
2484 reg->doneq_index = index;
2485 }
2486}
2487
2488static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
2489{
2490 struct MessageUnit_C __iomem *phbcmu;
2491 struct ARCMSR_CDB *arcmsr_cdb;
2492 struct CommandControlBlock *ccb;
2493 uint32_t flag_ccb, throttling = 0;
2494 unsigned long ccb_cdb_phy;
2495 int error;
2496
2497 phbcmu = acb->pmuC;
2498
2499
2500
2501 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
2502 0xFFFFFFFF) {
2503 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
2504 if (acb->cdb_phyadd_hipart)
2505 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
2506 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
2507 + ccb_cdb_phy);
2508 ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
2509 arcmsr_cdb);
2510 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2511 ? true : false;
2512
2513 arcmsr_drain_donequeue(acb, ccb, error);
2514 throttling++;
2515 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2516 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
2517 &phbcmu->inbound_doorbell);
2518 throttling = 0;
2519 }
2520 }
2521}
2522
2523static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
2524{
2525 u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
2526 uint32_t addressLow;
2527 int error;
2528 struct MessageUnit_D *pmu;
2529 struct ARCMSR_CDB *arcmsr_cdb;
2530 struct CommandControlBlock *ccb;
2531 unsigned long flags, ccb_cdb_phy;
2532
2533 spin_lock_irqsave(&acb->doneq_lock, flags);
2534 pmu = acb->pmuD;
2535 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
2536 doneq_index = pmu->doneq_index;
2537 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
2538 do {
2539 toggle = doneq_index & 0x4000;
2540 index_stripped = (doneq_index & 0xFFF) + 1;
2541 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
2542 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
2543 ((toggle ^ 0x4000) + 1);
2544 doneq_index = pmu->doneq_index;
2545 addressLow = pmu->done_qbuffer[doneq_index &
2546 0xFFF].addressLow;
2547 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
2548 if (acb->cdb_phyadd_hipart)
2549 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
2550 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
2551 + ccb_cdb_phy);
2552 ccb = container_of(arcmsr_cdb,
2553 struct CommandControlBlock, arcmsr_cdb);
2554 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2555 ? true : false;
2556 arcmsr_drain_donequeue(acb, ccb, error);
2557 writel(doneq_index, pmu->outboundlist_read_pointer);
2558 } while ((doneq_index & 0xFFF) !=
2559 (outbound_write_pointer & 0xFFF));
2560 }
2561 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
2562 pmu->outboundlist_interrupt_cause);
2563 readl(pmu->outboundlist_interrupt_cause);
2564 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2565}
2566
2567static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb)
2568{
2569 uint32_t doneq_index;
2570 uint16_t cmdSMID;
2571 int error;
2572 struct MessageUnit_E __iomem *pmu;
2573 struct CommandControlBlock *ccb;
2574 unsigned long flags;
2575
2576 spin_lock_irqsave(&acb->doneq_lock, flags);
2577 doneq_index = acb->doneq_index;
2578 pmu = acb->pmuE;
2579 while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) {
2580 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2581 ccb = acb->pccb_pool[cmdSMID];
2582 error = (acb->pCompletionQ[doneq_index].cmdFlag
2583 & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
2584 arcmsr_drain_donequeue(acb, ccb, error);
2585 doneq_index++;
2586 if (doneq_index >= acb->completionQ_entry)
2587 doneq_index = 0;
2588 }
2589 acb->doneq_index = doneq_index;
2590 writel(doneq_index, &pmu->reply_post_consumer_index);
2591 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2592}
2593
2594static void arcmsr_hbaF_postqueue_isr(struct AdapterControlBlock *acb)
2595{
2596 uint32_t doneq_index;
2597 uint16_t cmdSMID;
2598 int error;
2599 struct MessageUnit_F __iomem *phbcmu;
2600 struct CommandControlBlock *ccb;
2601 unsigned long flags;
2602
2603 spin_lock_irqsave(&acb->doneq_lock, flags);
2604 doneq_index = acb->doneq_index;
2605 phbcmu = acb->pmuF;
2606 while (1) {
2607 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2608 if (cmdSMID == 0xffff)
2609 break;
2610 ccb = acb->pccb_pool[cmdSMID];
2611 error = (acb->pCompletionQ[doneq_index].cmdFlag &
2612 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
2613 arcmsr_drain_donequeue(acb, ccb, error);
2614 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff;
2615 doneq_index++;
2616 if (doneq_index >= acb->completionQ_entry)
2617 doneq_index = 0;
2618 }
2619 acb->doneq_index = doneq_index;
2620 writel(doneq_index, &phbcmu->reply_post_consumer_index);
2621 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2622}
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
2633{
2634 struct MessageUnit_A __iomem *reg = acb->pmuA;
2635
2636 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, ®->outbound_intstatus);
2637 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2638 schedule_work(&acb->arcmsr_do_message_isr_bh);
2639}
2640static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
2641{
2642 struct MessageUnit_B *reg = acb->pmuB;
2643
2644
2645 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
2646 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2647 schedule_work(&acb->arcmsr_do_message_isr_bh);
2648}
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
2659{
2660 struct MessageUnit_C __iomem *reg = acb->pmuC;
2661
2662 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, ®->outbound_doorbell_clear);
2663 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2664 schedule_work(&acb->arcmsr_do_message_isr_bh);
2665}
2666
2667static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
2668{
2669 struct MessageUnit_D *reg = acb->pmuD;
2670
2671 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
2672 readl(reg->outbound_doorbell);
2673 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2674 schedule_work(&acb->arcmsr_do_message_isr_bh);
2675}
2676
2677static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb)
2678{
2679 struct MessageUnit_E __iomem *reg = acb->pmuE;
2680
2681 writel(0, ®->host_int_status);
2682 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2683 schedule_work(&acb->arcmsr_do_message_isr_bh);
2684}
2685
2686static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
2687{
2688 uint32_t outbound_intstatus;
2689 struct MessageUnit_A __iomem *reg = acb->pmuA;
2690 outbound_intstatus = readl(®->outbound_intstatus) &
2691 acb->outbound_int_enable;
2692 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
2693 return IRQ_NONE;
2694 do {
2695 writel(outbound_intstatus, ®->outbound_intstatus);
2696 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
2697 arcmsr_hbaA_doorbell_isr(acb);
2698 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
2699 arcmsr_hbaA_postqueue_isr(acb);
2700 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
2701 arcmsr_hbaA_message_isr(acb);
2702 outbound_intstatus = readl(®->outbound_intstatus) &
2703 acb->outbound_int_enable;
2704 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
2705 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
2706 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
2707 return IRQ_HANDLED;
2708}
2709
2710static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
2711{
2712 uint32_t outbound_doorbell;
2713 struct MessageUnit_B *reg = acb->pmuB;
2714 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2715 acb->outbound_int_enable;
2716 if (!outbound_doorbell)
2717 return IRQ_NONE;
2718 do {
2719 writel(~outbound_doorbell, reg->iop2drv_doorbell);
2720 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
2721 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
2722 arcmsr_iop2drv_data_wrote_handle(acb);
2723 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
2724 arcmsr_iop2drv_data_read_handle(acb);
2725 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
2726 arcmsr_hbaB_postqueue_isr(acb);
2727 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
2728 arcmsr_hbaB_message_isr(acb);
2729 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2730 acb->outbound_int_enable;
2731 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
2732 | ARCMSR_IOP2DRV_DATA_READ_OK
2733 | ARCMSR_IOP2DRV_CDB_DONE
2734 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
2735 return IRQ_HANDLED;
2736}
2737
2738static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
2739{
2740 uint32_t host_interrupt_status;
2741 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
2742
2743
2744
2745
2746
2747 host_interrupt_status = readl(&phbcmu->host_int_status) &
2748 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2749 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2750 if (!host_interrupt_status)
2751 return IRQ_NONE;
2752 do {
2753 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
2754 arcmsr_hbaC_doorbell_isr(pACB);
2755
2756 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
2757 arcmsr_hbaC_postqueue_isr(pACB);
2758 host_interrupt_status = readl(&phbcmu->host_int_status);
2759 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2760 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2761 return IRQ_HANDLED;
2762}
2763
2764static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
2765{
2766 u32 host_interrupt_status;
2767 struct MessageUnit_D *pmu = pACB->pmuD;
2768
2769 host_interrupt_status = readl(pmu->host_int_status) &
2770 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2771 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
2772 if (!host_interrupt_status)
2773 return IRQ_NONE;
2774 do {
2775
2776 if (host_interrupt_status &
2777 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
2778 arcmsr_hbaD_postqueue_isr(pACB);
2779 if (host_interrupt_status &
2780 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
2781 arcmsr_hbaD_doorbell_isr(pACB);
2782 host_interrupt_status = readl(pmu->host_int_status);
2783 } while (host_interrupt_status &
2784 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2785 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
2786 return IRQ_HANDLED;
2787}
2788
2789static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB)
2790{
2791 uint32_t host_interrupt_status;
2792 struct MessageUnit_E __iomem *pmu = pACB->pmuE;
2793
2794 host_interrupt_status = readl(&pmu->host_int_status) &
2795 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2796 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2797 if (!host_interrupt_status)
2798 return IRQ_NONE;
2799 do {
2800
2801 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2802 arcmsr_hbaE_doorbell_isr(pACB);
2803 }
2804
2805 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2806 arcmsr_hbaE_postqueue_isr(pACB);
2807 }
2808 host_interrupt_status = readl(&pmu->host_int_status);
2809 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2810 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2811 return IRQ_HANDLED;
2812}
2813
2814static irqreturn_t arcmsr_hbaF_handle_isr(struct AdapterControlBlock *pACB)
2815{
2816 uint32_t host_interrupt_status;
2817 struct MessageUnit_F __iomem *phbcmu = pACB->pmuF;
2818
2819 host_interrupt_status = readl(&phbcmu->host_int_status) &
2820 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2821 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2822 if (!host_interrupt_status)
2823 return IRQ_NONE;
2824 do {
2825
2826 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR)
2827 arcmsr_hbaF_postqueue_isr(pACB);
2828
2829
2830 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)
2831 arcmsr_hbaE_doorbell_isr(pACB);
2832
2833 host_interrupt_status = readl(&phbcmu->host_int_status);
2834 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2835 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2836 return IRQ_HANDLED;
2837}
2838
2839static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
2840{
2841 switch (acb->adapter_type) {
2842 case ACB_ADAPTER_TYPE_A:
2843 return arcmsr_hbaA_handle_isr(acb);
2844 case ACB_ADAPTER_TYPE_B:
2845 return arcmsr_hbaB_handle_isr(acb);
2846 case ACB_ADAPTER_TYPE_C:
2847 return arcmsr_hbaC_handle_isr(acb);
2848 case ACB_ADAPTER_TYPE_D:
2849 return arcmsr_hbaD_handle_isr(acb);
2850 case ACB_ADAPTER_TYPE_E:
2851 return arcmsr_hbaE_handle_isr(acb);
2852 case ACB_ADAPTER_TYPE_F:
2853 return arcmsr_hbaF_handle_isr(acb);
2854 default:
2855 return IRQ_NONE;
2856 }
2857}
2858
2859static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2860{
2861 if (acb) {
2862
2863 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
2864 uint32_t intmask_org;
2865 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
2866 intmask_org = arcmsr_disable_outbound_ints(acb);
2867 arcmsr_stop_adapter_bgrb(acb);
2868 arcmsr_flush_adapter_cache(acb);
2869 arcmsr_enable_outbound_ints(acb, intmask_org);
2870 }
2871 }
2872}
2873
2874
2875void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
2876{
2877 uint32_t i;
2878
2879 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2880 for (i = 0; i < 15; i++) {
2881 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2882 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2883 acb->rqbuf_getIndex = 0;
2884 acb->rqbuf_putIndex = 0;
2885 arcmsr_iop_message_read(acb);
2886 mdelay(30);
2887 } else if (acb->rqbuf_getIndex !=
2888 acb->rqbuf_putIndex) {
2889 acb->rqbuf_getIndex = 0;
2890 acb->rqbuf_putIndex = 0;
2891 mdelay(30);
2892 } else
2893 break;
2894 }
2895 }
2896}
2897
2898static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
2899 struct scsi_cmnd *cmd)
2900{
2901 char *buffer;
2902 unsigned short use_sg;
2903 int retvalue = 0, transfer_len = 0;
2904 unsigned long flags;
2905 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2906 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
2907 (uint32_t)cmd->cmnd[6] << 16 |
2908 (uint32_t)cmd->cmnd[7] << 8 |
2909 (uint32_t)cmd->cmnd[8];
2910 struct scatterlist *sg;
2911
2912 use_sg = scsi_sg_count(cmd);
2913 sg = scsi_sglist(cmd);
2914 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
2915 if (use_sg > 1) {
2916 retvalue = ARCMSR_MESSAGE_FAIL;
2917 goto message_out;
2918 }
2919 transfer_len += sg->length;
2920 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2921 retvalue = ARCMSR_MESSAGE_FAIL;
2922 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
2923 goto message_out;
2924 }
2925 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
2926 switch (controlcode) {
2927 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2928 unsigned char *ver_addr;
2929 uint8_t *ptmpQbuffer;
2930 uint32_t allxfer_len = 0;
2931 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
2932 if (!ver_addr) {
2933 retvalue = ARCMSR_MESSAGE_FAIL;
2934 pr_info("%s: memory not enough!\n", __func__);
2935 goto message_out;
2936 }
2937 ptmpQbuffer = ver_addr;
2938 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2939 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
2940 unsigned int tail = acb->rqbuf_getIndex;
2941 unsigned int head = acb->rqbuf_putIndex;
2942 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
2943
2944 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
2945 if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
2946 allxfer_len = ARCMSR_API_DATA_BUFLEN;
2947
2948 if (allxfer_len <= cnt_to_end)
2949 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
2950 else {
2951 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
2952 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
2953 }
2954 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
2955 }
2956 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
2957 allxfer_len);
2958 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2959 struct QBUFFER __iomem *prbuffer;
2960 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2961 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2962 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2963 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2964 }
2965 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2966 kfree(ver_addr);
2967 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2968 if (acb->fw_flag == FW_DEADLOCK)
2969 pcmdmessagefld->cmdmessage.ReturnCode =
2970 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2971 else
2972 pcmdmessagefld->cmdmessage.ReturnCode =
2973 ARCMSR_MESSAGE_RETURNCODE_OK;
2974 break;
2975 }
2976 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2977 unsigned char *ver_addr;
2978 uint32_t user_len;
2979 int32_t cnt2end;
2980 uint8_t *pQbuffer, *ptmpuserbuffer;
2981
2982 user_len = pcmdmessagefld->cmdmessage.Length;
2983 if (user_len > ARCMSR_API_DATA_BUFLEN) {
2984 retvalue = ARCMSR_MESSAGE_FAIL;
2985 goto message_out;
2986 }
2987
2988 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
2989 if (!ver_addr) {
2990 retvalue = ARCMSR_MESSAGE_FAIL;
2991 goto message_out;
2992 }
2993 ptmpuserbuffer = ver_addr;
2994
2995 memcpy(ptmpuserbuffer,
2996 pcmdmessagefld->messagedatabuffer, user_len);
2997 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2998 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
2999 struct SENSE_DATA *sensebuffer =
3000 (struct SENSE_DATA *)cmd->sense_buffer;
3001 arcmsr_write_ioctldata2iop(acb);
3002
3003 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
3004 sensebuffer->SenseKey = ILLEGAL_REQUEST;
3005 sensebuffer->AdditionalSenseLength = 0x0A;
3006 sensebuffer->AdditionalSenseCode = 0x20;
3007 sensebuffer->Valid = 1;
3008 retvalue = ARCMSR_MESSAGE_FAIL;
3009 } else {
3010 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
3011 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
3012 if (user_len > cnt2end) {
3013 memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
3014 ptmpuserbuffer += cnt2end;
3015 user_len -= cnt2end;
3016 acb->wqbuf_putIndex = 0;
3017 pQbuffer = acb->wqbuffer;
3018 }
3019 memcpy(pQbuffer, ptmpuserbuffer, user_len);
3020 acb->wqbuf_putIndex += user_len;
3021 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
3022 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
3023 acb->acb_flags &=
3024 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
3025 arcmsr_write_ioctldata2iop(acb);
3026 }
3027 }
3028 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
3029 kfree(ver_addr);
3030 if (acb->fw_flag == FW_DEADLOCK)
3031 pcmdmessagefld->cmdmessage.ReturnCode =
3032 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3033 else
3034 pcmdmessagefld->cmdmessage.ReturnCode =
3035 ARCMSR_MESSAGE_RETURNCODE_OK;
3036 break;
3037 }
3038 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
3039 uint8_t *pQbuffer = acb->rqbuffer;
3040
3041 arcmsr_clear_iop2drv_rqueue_buffer(acb);
3042 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
3043 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
3044 acb->rqbuf_getIndex = 0;
3045 acb->rqbuf_putIndex = 0;
3046 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
3047 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
3048 if (acb->fw_flag == FW_DEADLOCK)
3049 pcmdmessagefld->cmdmessage.ReturnCode =
3050 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3051 else
3052 pcmdmessagefld->cmdmessage.ReturnCode =
3053 ARCMSR_MESSAGE_RETURNCODE_OK;
3054 break;
3055 }
3056 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
3057 uint8_t *pQbuffer = acb->wqbuffer;
3058 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
3059 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
3060 ACB_F_MESSAGE_WQBUFFER_READED);
3061 acb->wqbuf_getIndex = 0;
3062 acb->wqbuf_putIndex = 0;
3063 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
3064 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
3065 if (acb->fw_flag == FW_DEADLOCK)
3066 pcmdmessagefld->cmdmessage.ReturnCode =
3067 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3068 else
3069 pcmdmessagefld->cmdmessage.ReturnCode =
3070 ARCMSR_MESSAGE_RETURNCODE_OK;
3071 break;
3072 }
3073 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
3074 uint8_t *pQbuffer;
3075 arcmsr_clear_iop2drv_rqueue_buffer(acb);
3076 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
3077 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
3078 acb->rqbuf_getIndex = 0;
3079 acb->rqbuf_putIndex = 0;
3080 pQbuffer = acb->rqbuffer;
3081 memset(pQbuffer, 0, sizeof(struct QBUFFER));
3082 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
3083 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
3084 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
3085 ACB_F_MESSAGE_WQBUFFER_READED);
3086 acb->wqbuf_getIndex = 0;
3087 acb->wqbuf_putIndex = 0;
3088 pQbuffer = acb->wqbuffer;
3089 memset(pQbuffer, 0, sizeof(struct QBUFFER));
3090 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
3091 if (acb->fw_flag == FW_DEADLOCK)
3092 pcmdmessagefld->cmdmessage.ReturnCode =
3093 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3094 else
3095 pcmdmessagefld->cmdmessage.ReturnCode =
3096 ARCMSR_MESSAGE_RETURNCODE_OK;
3097 break;
3098 }
3099 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
3100 if (acb->fw_flag == FW_DEADLOCK)
3101 pcmdmessagefld->cmdmessage.ReturnCode =
3102 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3103 else
3104 pcmdmessagefld->cmdmessage.ReturnCode =
3105 ARCMSR_MESSAGE_RETURNCODE_3F;
3106 break;
3107 }
3108 case ARCMSR_MESSAGE_SAY_HELLO: {
3109 int8_t *hello_string = "Hello! I am ARCMSR";
3110 if (acb->fw_flag == FW_DEADLOCK)
3111 pcmdmessagefld->cmdmessage.ReturnCode =
3112 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3113 else
3114 pcmdmessagefld->cmdmessage.ReturnCode =
3115 ARCMSR_MESSAGE_RETURNCODE_OK;
3116 memcpy(pcmdmessagefld->messagedatabuffer,
3117 hello_string, (int16_t)strlen(hello_string));
3118 break;
3119 }
3120 case ARCMSR_MESSAGE_SAY_GOODBYE: {
3121 if (acb->fw_flag == FW_DEADLOCK)
3122 pcmdmessagefld->cmdmessage.ReturnCode =
3123 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3124 else
3125 pcmdmessagefld->cmdmessage.ReturnCode =
3126 ARCMSR_MESSAGE_RETURNCODE_OK;
3127 arcmsr_iop_parking(acb);
3128 break;
3129 }
3130 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
3131 if (acb->fw_flag == FW_DEADLOCK)
3132 pcmdmessagefld->cmdmessage.ReturnCode =
3133 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3134 else
3135 pcmdmessagefld->cmdmessage.ReturnCode =
3136 ARCMSR_MESSAGE_RETURNCODE_OK;
3137 arcmsr_flush_adapter_cache(acb);
3138 break;
3139 }
3140 default:
3141 retvalue = ARCMSR_MESSAGE_FAIL;
3142 pr_info("%s: unknown controlcode!\n", __func__);
3143 }
3144message_out:
3145 if (use_sg) {
3146 struct scatterlist *sg = scsi_sglist(cmd);
3147 kunmap_atomic(buffer - sg->offset);
3148 }
3149 return retvalue;
3150}
3151
3152static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
3153{
3154 struct list_head *head;
3155 struct CommandControlBlock *ccb = NULL;
3156 unsigned long flags;
3157
3158 spin_lock_irqsave(&acb->ccblist_lock, flags);
3159 head = &acb->ccb_free_list;
3160 if (!list_empty(head)) {
3161 ccb = list_entry(head->next, struct CommandControlBlock, list);
3162 list_del_init(&ccb->list);
3163 }else{
3164 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
3165 return NULL;
3166 }
3167 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
3168 return ccb;
3169}
3170
3171static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
3172 struct scsi_cmnd *cmd)
3173{
3174 switch (cmd->cmnd[0]) {
3175 case INQUIRY: {
3176 unsigned char inqdata[36];
3177 char *buffer;
3178 struct scatterlist *sg;
3179
3180 if (cmd->device->lun) {
3181 cmd->result = (DID_TIME_OUT << 16);
3182 cmd->scsi_done(cmd);
3183 return;
3184 }
3185 inqdata[0] = TYPE_PROCESSOR;
3186
3187 inqdata[1] = 0;
3188
3189 inqdata[2] = 0;
3190
3191 inqdata[4] = 31;
3192
3193 memcpy(&inqdata[8], "Areca ", 8);
3194
3195 memcpy(&inqdata[16], "RAID controller ", 16);
3196
3197 memcpy(&inqdata[32], "R001", 4);
3198
3199 sg = scsi_sglist(cmd);
3200 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
3201
3202 memcpy(buffer, inqdata, sizeof(inqdata));
3203 sg = scsi_sglist(cmd);
3204 kunmap_atomic(buffer - sg->offset);
3205
3206 cmd->scsi_done(cmd);
3207 }
3208 break;
3209 case WRITE_BUFFER:
3210 case READ_BUFFER: {
3211 if (arcmsr_iop_message_xfer(acb, cmd))
3212 cmd->result = (DID_ERROR << 16);
3213 cmd->scsi_done(cmd);
3214 }
3215 break;
3216 default:
3217 cmd->scsi_done(cmd);
3218 }
3219}
3220
3221static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
3222 void (* done)(struct scsi_cmnd *))
3223{
3224 struct Scsi_Host *host = cmd->device->host;
3225 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
3226 struct CommandControlBlock *ccb;
3227 int target = cmd->device->id;
3228
3229 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) {
3230 cmd->result = (DID_NO_CONNECT << 16);
3231 cmd->scsi_done(cmd);
3232 return 0;
3233 }
3234 cmd->scsi_done = done;
3235 cmd->host_scribble = NULL;
3236 cmd->result = 0;
3237 if (target == 16) {
3238
3239 arcmsr_handle_virtual_command(acb, cmd);
3240 return 0;
3241 }
3242 ccb = arcmsr_get_freeccb(acb);
3243 if (!ccb)
3244 return SCSI_MLQUEUE_HOST_BUSY;
3245 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
3246 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
3247 cmd->scsi_done(cmd);
3248 return 0;
3249 }
3250 arcmsr_post_ccb(acb, ccb);
3251 return 0;
3252}
3253
3254static DEF_SCSI_QCMD(arcmsr_queue_command)
3255
3256static int arcmsr_slave_config(struct scsi_device *sdev)
3257{
3258 unsigned int dev_timeout;
3259
3260 dev_timeout = sdev->request_queue->rq_timeout;
3261 if ((cmd_timeout > 0) && ((cmd_timeout * HZ) > dev_timeout))
3262 blk_queue_rq_timeout(sdev->request_queue, cmd_timeout * HZ);
3263 return 0;
3264}
3265
3266static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer)
3267{
3268 int count;
3269 uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model;
3270 uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version;
3271 uint32_t *acb_device_map = (uint32_t *)pACB->device_map;
3272 uint32_t *firm_model = &rwbuffer[15];
3273 uint32_t *firm_version = &rwbuffer[17];
3274 uint32_t *device_map = &rwbuffer[21];
3275
3276 count = 2;
3277 while (count) {
3278 *acb_firm_model = readl(firm_model);
3279 acb_firm_model++;
3280 firm_model++;
3281 count--;
3282 }
3283 count = 4;
3284 while (count) {
3285 *acb_firm_version = readl(firm_version);
3286 acb_firm_version++;
3287 firm_version++;
3288 count--;
3289 }
3290 count = 4;
3291 while (count) {
3292 *acb_device_map = readl(device_map);
3293 acb_device_map++;
3294 device_map++;
3295 count--;
3296 }
3297 pACB->signature = readl(&rwbuffer[0]);
3298 pACB->firm_request_len = readl(&rwbuffer[1]);
3299 pACB->firm_numbers_queue = readl(&rwbuffer[2]);
3300 pACB->firm_sdram_size = readl(&rwbuffer[3]);
3301 pACB->firm_hd_channels = readl(&rwbuffer[4]);
3302 pACB->firm_cfg_version = readl(&rwbuffer[25]);
3303 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
3304 pACB->host->host_no,
3305 pACB->firm_model,
3306 pACB->firm_version);
3307}
3308
3309static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
3310{
3311 struct MessageUnit_A __iomem *reg = acb->pmuA;
3312
3313 arcmsr_wait_firmware_ready(acb);
3314 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
3315 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3316 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3317 miscellaneous data' timeout \n", acb->host->host_no);
3318 return false;
3319 }
3320 arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
3321 return true;
3322}
3323static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
3324{
3325 struct MessageUnit_B *reg = acb->pmuB;
3326
3327 arcmsr_wait_firmware_ready(acb);
3328 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
3329 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3330 printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no);
3331 return false;
3332 }
3333 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
3334 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3335 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3336 miscellaneous data' timeout \n", acb->host->host_no);
3337 return false;
3338 }
3339 arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
3340 return true;
3341}
3342
3343static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
3344{
3345 uint32_t intmask_org;
3346 struct MessageUnit_C __iomem *reg = pACB->pmuC;
3347
3348
3349 intmask_org = readl(®->host_int_mask);
3350 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask);
3351
3352 arcmsr_wait_firmware_ready(pACB);
3353
3354 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
3355 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
3356
3357 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
3358 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3359 miscellaneous data' timeout \n", pACB->host->host_no);
3360 return false;
3361 }
3362 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
3363 return true;
3364}
3365
3366static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
3367{
3368 struct MessageUnit_D *reg = acb->pmuD;
3369
3370 if (readl(acb->pmuD->outbound_doorbell) &
3371 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
3372 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
3373 acb->pmuD->outbound_doorbell);
3374 }
3375 arcmsr_wait_firmware_ready(acb);
3376
3377 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
3378
3379 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
3380 pr_notice("arcmsr%d: wait get adapter firmware "
3381 "miscellaneous data timeout\n", acb->host->host_no);
3382 return false;
3383 }
3384 arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer);
3385 return true;
3386}
3387
3388static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB)
3389{
3390 struct MessageUnit_E __iomem *reg = pACB->pmuE;
3391 uint32_t intmask_org;
3392
3393
3394 intmask_org = readl(®->host_int_mask);
3395 writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask);
3396
3397 arcmsr_wait_firmware_ready(pACB);
3398 mdelay(20);
3399
3400 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
3401
3402 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3403 writel(pACB->out_doorbell, ®->iobound_doorbell);
3404
3405 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
3406 pr_notice("arcmsr%d: wait get adapter firmware "
3407 "miscellaneous data timeout\n", pACB->host->host_no);
3408 return false;
3409 }
3410 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
3411 return true;
3412}
3413
3414static bool arcmsr_hbaF_get_config(struct AdapterControlBlock *pACB)
3415{
3416 struct MessageUnit_F __iomem *reg = pACB->pmuF;
3417 uint32_t intmask_org;
3418
3419
3420 intmask_org = readl(®->host_int_mask);
3421 writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask);
3422
3423 arcmsr_wait_firmware_ready(pACB);
3424
3425 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
3426
3427 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3428 writel(pACB->out_doorbell, ®->iobound_doorbell);
3429
3430 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
3431 pr_notice("arcmsr%d: wait get adapter firmware miscellaneous data timeout\n",
3432 pACB->host->host_no);
3433 return false;
3434 }
3435 arcmsr_get_adapter_config(pACB, pACB->msgcode_rwbuffer);
3436 return true;
3437}
3438
3439static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
3440{
3441 bool rtn = false;
3442
3443 switch (acb->adapter_type) {
3444 case ACB_ADAPTER_TYPE_A:
3445 rtn = arcmsr_hbaA_get_config(acb);
3446 break;
3447 case ACB_ADAPTER_TYPE_B:
3448 rtn = arcmsr_hbaB_get_config(acb);
3449 break;
3450 case ACB_ADAPTER_TYPE_C:
3451 rtn = arcmsr_hbaC_get_config(acb);
3452 break;
3453 case ACB_ADAPTER_TYPE_D:
3454 rtn = arcmsr_hbaD_get_config(acb);
3455 break;
3456 case ACB_ADAPTER_TYPE_E:
3457 rtn = arcmsr_hbaE_get_config(acb);
3458 break;
3459 case ACB_ADAPTER_TYPE_F:
3460 rtn = arcmsr_hbaF_get_config(acb);
3461 break;
3462 default:
3463 break;
3464 }
3465 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3466 if (acb->host->can_queue >= acb->firm_numbers_queue)
3467 acb->host->can_queue = acb->maxOutstanding;
3468 else
3469 acb->maxOutstanding = acb->host->can_queue;
3470 acb->maxFreeCCB = acb->host->can_queue;
3471 if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM)
3472 acb->maxFreeCCB += 64;
3473 return rtn;
3474}
3475
3476static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
3477 struct CommandControlBlock *poll_ccb)
3478{
3479 struct MessageUnit_A __iomem *reg = acb->pmuA;
3480 struct CommandControlBlock *ccb;
3481 struct ARCMSR_CDB *arcmsr_cdb;
3482 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
3483 int rtn;
3484 bool error;
3485 unsigned long ccb_cdb_phy;
3486
3487polling_hba_ccb_retry:
3488 poll_count++;
3489 outbound_intstatus = readl(®->outbound_intstatus) & acb->outbound_int_enable;
3490 writel(outbound_intstatus, ®->outbound_intstatus);
3491 while (1) {
3492 if ((flag_ccb = readl(®->outbound_queueport)) == 0xFFFFFFFF) {
3493 if (poll_ccb_done){
3494 rtn = SUCCESS;
3495 break;
3496 }else {
3497 msleep(25);
3498 if (poll_count > 100){
3499 rtn = FAILED;
3500 break;
3501 }
3502 goto polling_hba_ccb_retry;
3503 }
3504 }
3505 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
3506 if (acb->cdb_phyadd_hipart)
3507 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
3508 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
3509 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
3510 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
3511 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3512 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
3513 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3514 " poll command abort successfully \n"
3515 , acb->host->host_no
3516 , ccb->pcmd->device->id
3517 , (u32)ccb->pcmd->device->lun
3518 , ccb);
3519 ccb->pcmd->result = DID_ABORT << 16;
3520 arcmsr_ccb_complete(ccb);
3521 continue;
3522 }
3523 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3524 " command done ccb = '0x%p'"
3525 "ccboutstandingcount = %d \n"
3526 , acb->host->host_no
3527 , ccb
3528 , atomic_read(&acb->ccboutstandingcount));
3529 continue;
3530 }
3531 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3532 arcmsr_report_ccb_state(acb, ccb, error);
3533 }
3534 return rtn;
3535}
3536
3537static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
3538 struct CommandControlBlock *poll_ccb)
3539{
3540 struct MessageUnit_B *reg = acb->pmuB;
3541 struct ARCMSR_CDB *arcmsr_cdb;
3542 struct CommandControlBlock *ccb;
3543 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
3544 int index, rtn;
3545 bool error;
3546 unsigned long ccb_cdb_phy;
3547
3548polling_hbb_ccb_retry:
3549 poll_count++;
3550
3551 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
3552 while(1){
3553 index = reg->doneq_index;
3554 flag_ccb = reg->done_qbuffer[index];
3555 if (flag_ccb == 0) {
3556 if (poll_ccb_done){
3557 rtn = SUCCESS;
3558 break;
3559 }else {
3560 msleep(25);
3561 if (poll_count > 100){
3562 rtn = FAILED;
3563 break;
3564 }
3565 goto polling_hbb_ccb_retry;
3566 }
3567 }
3568 reg->done_qbuffer[index] = 0;
3569 index++;
3570
3571 index %= ARCMSR_MAX_HBB_POSTQUEUE;
3572 reg->doneq_index = index;
3573
3574 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
3575 if (acb->cdb_phyadd_hipart)
3576 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
3577 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
3578 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
3579 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
3580 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3581 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
3582 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3583 " poll command abort successfully \n"
3584 ,acb->host->host_no
3585 ,ccb->pcmd->device->id
3586 ,(u32)ccb->pcmd->device->lun
3587 ,ccb);
3588 ccb->pcmd->result = DID_ABORT << 16;
3589 arcmsr_ccb_complete(ccb);
3590 continue;
3591 }
3592 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3593 " command done ccb = '0x%p'"
3594 "ccboutstandingcount = %d \n"
3595 , acb->host->host_no
3596 , ccb
3597 , atomic_read(&acb->ccboutstandingcount));
3598 continue;
3599 }
3600 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3601 arcmsr_report_ccb_state(acb, ccb, error);
3602 }
3603 return rtn;
3604}
3605
3606static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
3607 struct CommandControlBlock *poll_ccb)
3608{
3609 struct MessageUnit_C __iomem *reg = acb->pmuC;
3610 uint32_t flag_ccb;
3611 struct ARCMSR_CDB *arcmsr_cdb;
3612 bool error;
3613 struct CommandControlBlock *pCCB;
3614 uint32_t poll_ccb_done = 0, poll_count = 0;
3615 int rtn;
3616 unsigned long ccb_cdb_phy;
3617
3618polling_hbc_ccb_retry:
3619 poll_count++;
3620 while (1) {
3621 if ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
3622 if (poll_ccb_done) {
3623 rtn = SUCCESS;
3624 break;
3625 } else {
3626 msleep(25);
3627 if (poll_count > 100) {
3628 rtn = FAILED;
3629 break;
3630 }
3631 goto polling_hbc_ccb_retry;
3632 }
3633 }
3634 flag_ccb = readl(®->outbound_queueport_low);
3635 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
3636 if (acb->cdb_phyadd_hipart)
3637 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
3638 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
3639 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
3640 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3641
3642 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3643 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3644 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3645 " poll command abort successfully \n"
3646 , acb->host->host_no
3647 , pCCB->pcmd->device->id
3648 , (u32)pCCB->pcmd->device->lun
3649 , pCCB);
3650 pCCB->pcmd->result = DID_ABORT << 16;
3651 arcmsr_ccb_complete(pCCB);
3652 continue;
3653 }
3654 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3655 " command done ccb = '0x%p'"
3656 "ccboutstandingcount = %d \n"
3657 , acb->host->host_no
3658 , pCCB
3659 , atomic_read(&acb->ccboutstandingcount));
3660 continue;
3661 }
3662 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3663 arcmsr_report_ccb_state(acb, pCCB, error);
3664 }
3665 return rtn;
3666}
3667
3668static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
3669 struct CommandControlBlock *poll_ccb)
3670{
3671 bool error;
3672 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb;
3673 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
3674 unsigned long flags, ccb_cdb_phy;
3675 struct ARCMSR_CDB *arcmsr_cdb;
3676 struct CommandControlBlock *pCCB;
3677 struct MessageUnit_D *pmu = acb->pmuD;
3678
3679polling_hbaD_ccb_retry:
3680 poll_count++;
3681 while (1) {
3682 spin_lock_irqsave(&acb->doneq_lock, flags);
3683 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
3684 doneq_index = pmu->doneq_index;
3685 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
3686 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3687 if (poll_ccb_done) {
3688 rtn = SUCCESS;
3689 break;
3690 } else {
3691 msleep(25);
3692 if (poll_count > 40) {
3693 rtn = FAILED;
3694 break;
3695 }
3696 goto polling_hbaD_ccb_retry;
3697 }
3698 }
3699 toggle = doneq_index & 0x4000;
3700 index_stripped = (doneq_index & 0xFFF) + 1;
3701 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
3702 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
3703 ((toggle ^ 0x4000) + 1);
3704 doneq_index = pmu->doneq_index;
3705 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3706 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
3707 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
3708 if (acb->cdb_phyadd_hipart)
3709 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
3710 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
3711 ccb_cdb_phy);
3712 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
3713 arcmsr_cdb);
3714 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3715 if ((pCCB->acb != acb) ||
3716 (pCCB->startdone != ARCMSR_CCB_START)) {
3717 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3718 pr_notice("arcmsr%d: scsi id = %d "
3719 "lun = %d ccb = '0x%p' poll command "
3720 "abort successfully\n"
3721 , acb->host->host_no
3722 , pCCB->pcmd->device->id
3723 , (u32)pCCB->pcmd->device->lun
3724 , pCCB);
3725 pCCB->pcmd->result = DID_ABORT << 16;
3726 arcmsr_ccb_complete(pCCB);
3727 continue;
3728 }
3729 pr_notice("arcmsr%d: polling an illegal "
3730 "ccb command done ccb = '0x%p' "
3731 "ccboutstandingcount = %d\n"
3732 , acb->host->host_no
3733 , pCCB
3734 , atomic_read(&acb->ccboutstandingcount));
3735 continue;
3736 }
3737 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
3738 ? true : false;
3739 arcmsr_report_ccb_state(acb, pCCB, error);
3740 }
3741 return rtn;
3742}
3743
3744static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb,
3745 struct CommandControlBlock *poll_ccb)
3746{
3747 bool error;
3748 uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index;
3749 uint16_t cmdSMID;
3750 unsigned long flags;
3751 int rtn;
3752 struct CommandControlBlock *pCCB;
3753 struct MessageUnit_E __iomem *reg = acb->pmuE;
3754
3755 polling_hbaC_ccb_retry:
3756 poll_count++;
3757 while (1) {
3758 spin_lock_irqsave(&acb->doneq_lock, flags);
3759 doneq_index = acb->doneq_index;
3760 if ((readl(®->reply_post_producer_index) & 0xFFFF) ==
3761 doneq_index) {
3762 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3763 if (poll_ccb_done) {
3764 rtn = SUCCESS;
3765 break;
3766 } else {
3767 msleep(25);
3768 if (poll_count > 40) {
3769 rtn = FAILED;
3770 break;
3771 }
3772 goto polling_hbaC_ccb_retry;
3773 }
3774 }
3775 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3776 doneq_index++;
3777 if (doneq_index >= acb->completionQ_entry)
3778 doneq_index = 0;
3779 acb->doneq_index = doneq_index;
3780 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3781 pCCB = acb->pccb_pool[cmdSMID];
3782 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3783
3784 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3785 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3786 pr_notice("arcmsr%d: scsi id = %d "
3787 "lun = %d ccb = '0x%p' poll command "
3788 "abort successfully\n"
3789 , acb->host->host_no
3790 , pCCB->pcmd->device->id
3791 , (u32)pCCB->pcmd->device->lun
3792 , pCCB);
3793 pCCB->pcmd->result = DID_ABORT << 16;
3794 arcmsr_ccb_complete(pCCB);
3795 continue;
3796 }
3797 pr_notice("arcmsr%d: polling an illegal "
3798 "ccb command done ccb = '0x%p' "
3799 "ccboutstandingcount = %d\n"
3800 , acb->host->host_no
3801 , pCCB
3802 , atomic_read(&acb->ccboutstandingcount));
3803 continue;
3804 }
3805 error = (acb->pCompletionQ[doneq_index].cmdFlag &
3806 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3807 arcmsr_report_ccb_state(acb, pCCB, error);
3808 }
3809 writel(doneq_index, ®->reply_post_consumer_index);
3810 return rtn;
3811}
3812
3813static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
3814 struct CommandControlBlock *poll_ccb)
3815{
3816 int rtn = 0;
3817 switch (acb->adapter_type) {
3818
3819 case ACB_ADAPTER_TYPE_A:
3820 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
3821 break;
3822 case ACB_ADAPTER_TYPE_B:
3823 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
3824 break;
3825 case ACB_ADAPTER_TYPE_C:
3826 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
3827 break;
3828 case ACB_ADAPTER_TYPE_D:
3829 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
3830 break;
3831 case ACB_ADAPTER_TYPE_E:
3832 case ACB_ADAPTER_TYPE_F:
3833 rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb);
3834 break;
3835 }
3836 return rtn;
3837}
3838
3839static void arcmsr_set_iop_datetime(struct timer_list *t)
3840{
3841 struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer);
3842 unsigned int next_time;
3843 struct tm tm;
3844
3845 union {
3846 struct {
3847 uint16_t signature;
3848 uint8_t year;
3849 uint8_t month;
3850 uint8_t date;
3851 uint8_t hour;
3852 uint8_t minute;
3853 uint8_t second;
3854 } a;
3855 struct {
3856 uint32_t msg_time[2];
3857 } b;
3858 } datetime;
3859
3860 time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm);
3861
3862 datetime.a.signature = 0x55AA;
3863 datetime.a.year = tm.tm_year - 100;
3864 datetime.a.month = tm.tm_mon;
3865 datetime.a.date = tm.tm_mday;
3866 datetime.a.hour = tm.tm_hour;
3867 datetime.a.minute = tm.tm_min;
3868 datetime.a.second = tm.tm_sec;
3869
3870 switch (pacb->adapter_type) {
3871 case ACB_ADAPTER_TYPE_A: {
3872 struct MessageUnit_A __iomem *reg = pacb->pmuA;
3873 writel(datetime.b.msg_time[0], ®->message_rwbuffer[0]);
3874 writel(datetime.b.msg_time[1], ®->message_rwbuffer[1]);
3875 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
3876 break;
3877 }
3878 case ACB_ADAPTER_TYPE_B: {
3879 uint32_t __iomem *rwbuffer;
3880 struct MessageUnit_B *reg = pacb->pmuB;
3881 rwbuffer = reg->message_rwbuffer;
3882 writel(datetime.b.msg_time[0], rwbuffer++);
3883 writel(datetime.b.msg_time[1], rwbuffer++);
3884 writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell);
3885 break;
3886 }
3887 case ACB_ADAPTER_TYPE_C: {
3888 struct MessageUnit_C __iomem *reg = pacb->pmuC;
3889 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]);
3890 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]);
3891 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
3892 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
3893 break;
3894 }
3895 case ACB_ADAPTER_TYPE_D: {
3896 uint32_t __iomem *rwbuffer;
3897 struct MessageUnit_D *reg = pacb->pmuD;
3898 rwbuffer = reg->msgcode_rwbuffer;
3899 writel(datetime.b.msg_time[0], rwbuffer++);
3900 writel(datetime.b.msg_time[1], rwbuffer++);
3901 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0);
3902 break;
3903 }
3904 case ACB_ADAPTER_TYPE_E: {
3905 struct MessageUnit_E __iomem *reg = pacb->pmuE;
3906 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]);
3907 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]);
3908 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
3909 pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3910 writel(pacb->out_doorbell, ®->iobound_doorbell);
3911 break;
3912 }
3913 case ACB_ADAPTER_TYPE_F: {
3914 struct MessageUnit_F __iomem *reg = pacb->pmuF;
3915
3916 pacb->msgcode_rwbuffer[0] = datetime.b.msg_time[0];
3917 pacb->msgcode_rwbuffer[1] = datetime.b.msg_time[1];
3918 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
3919 pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3920 writel(pacb->out_doorbell, ®->iobound_doorbell);
3921 break;
3922 }
3923 }
3924 if (sys_tz.tz_minuteswest)
3925 next_time = ARCMSR_HOURS;
3926 else
3927 next_time = ARCMSR_MINUTES;
3928 mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time));
3929}
3930
3931static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3932{
3933 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
3934 dma_addr_t dma_coherent_handle;
3935
3936
3937
3938
3939
3940
3941
3942 switch (acb->adapter_type) {
3943 case ACB_ADAPTER_TYPE_B:
3944 case ACB_ADAPTER_TYPE_D:
3945 dma_coherent_handle = acb->dma_coherent_handle2;
3946 break;
3947 case ACB_ADAPTER_TYPE_E:
3948 case ACB_ADAPTER_TYPE_F:
3949 dma_coherent_handle = acb->dma_coherent_handle +
3950 offsetof(struct CommandControlBlock, arcmsr_cdb);
3951 break;
3952 default:
3953 dma_coherent_handle = acb->dma_coherent_handle;
3954 break;
3955 }
3956 cdb_phyaddr = lower_32_bits(dma_coherent_handle);
3957 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
3958 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
3959 acb->cdb_phyadd_hipart = ((uint64_t)cdb_phyaddr_hi32) << 32;
3960
3961
3962
3963
3964
3965 switch (acb->adapter_type) {
3966
3967 case ACB_ADAPTER_TYPE_A: {
3968 if (cdb_phyaddr_hi32 != 0) {
3969 struct MessageUnit_A __iomem *reg = acb->pmuA;
3970 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
3971 ®->message_rwbuffer[0]);
3972 writel(cdb_phyaddr_hi32, ®->message_rwbuffer[1]);
3973 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
3974 ®->inbound_msgaddr0);
3975 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3976 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
3977 part physical address timeout\n",
3978 acb->host->host_no);
3979 return 1;
3980 }
3981 }
3982 }
3983 break;
3984
3985 case ACB_ADAPTER_TYPE_B: {
3986 uint32_t __iomem *rwbuffer;
3987
3988 struct MessageUnit_B *reg = acb->pmuB;
3989 reg->postq_index = 0;
3990 reg->doneq_index = 0;
3991 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
3992 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3993 printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \
3994 acb->host->host_no);
3995 return 1;
3996 }
3997 rwbuffer = reg->message_rwbuffer;
3998
3999 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
4000
4001 writel(cdb_phyaddr_hi32, rwbuffer++);
4002
4003 writel(cdb_phyaddr, rwbuffer++);
4004
4005 writel(cdb_phyaddr + 1056, rwbuffer++);
4006
4007 writel(1056, rwbuffer);
4008
4009 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
4010 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
4011 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
4012 timeout \n",acb->host->host_no);
4013 return 1;
4014 }
4015 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
4016 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
4017 pr_err("arcmsr%d: can't set driver mode.\n",
4018 acb->host->host_no);
4019 return 1;
4020 }
4021 }
4022 break;
4023 case ACB_ADAPTER_TYPE_C: {
4024 struct MessageUnit_C __iomem *reg = acb->pmuC;
4025
4026 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
4027 acb->adapter_index, cdb_phyaddr_hi32);
4028 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]);
4029 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[1]);
4030 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
4031 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
4032 if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
4033 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
4034 timeout \n", acb->host->host_no);
4035 return 1;
4036 }
4037 }
4038 break;
4039 case ACB_ADAPTER_TYPE_D: {
4040 uint32_t __iomem *rwbuffer;
4041 struct MessageUnit_D *reg = acb->pmuD;
4042 reg->postq_index = 0;
4043 reg->doneq_index = 0;
4044 rwbuffer = reg->msgcode_rwbuffer;
4045 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
4046 writel(cdb_phyaddr_hi32, rwbuffer++);
4047 writel(cdb_phyaddr, rwbuffer++);
4048 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
4049 sizeof(struct InBound_SRB)), rwbuffer++);
4050 writel(0x100, rwbuffer);
4051 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
4052 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
4053 pr_notice("arcmsr%d: 'set command Q window' timeout\n",
4054 acb->host->host_no);
4055 return 1;
4056 }
4057 }
4058 break;
4059 case ACB_ADAPTER_TYPE_E: {
4060 struct MessageUnit_E __iomem *reg = acb->pmuE;
4061 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]);
4062 writel(ARCMSR_SIGNATURE_1884, ®->msgcode_rwbuffer[1]);
4063 writel(cdb_phyaddr, ®->msgcode_rwbuffer[2]);
4064 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[3]);
4065 writel(acb->ccbsize, ®->msgcode_rwbuffer[4]);
4066 writel(lower_32_bits(acb->dma_coherent_handle2), ®->msgcode_rwbuffer[5]);
4067 writel(upper_32_bits(acb->dma_coherent_handle2), ®->msgcode_rwbuffer[6]);
4068 writel(acb->ioqueue_size, ®->msgcode_rwbuffer[7]);
4069 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
4070 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4071 writel(acb->out_doorbell, ®->iobound_doorbell);
4072 if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
4073 pr_notice("arcmsr%d: 'set command Q window' timeout \n",
4074 acb->host->host_no);
4075 return 1;
4076 }
4077 }
4078 break;
4079 case ACB_ADAPTER_TYPE_F: {
4080 struct MessageUnit_F __iomem *reg = acb->pmuF;
4081
4082 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG;
4083 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886;
4084 acb->msgcode_rwbuffer[2] = cdb_phyaddr;
4085 acb->msgcode_rwbuffer[3] = cdb_phyaddr_hi32;
4086 acb->msgcode_rwbuffer[4] = acb->ccbsize;
4087 acb->msgcode_rwbuffer[5] = lower_32_bits(acb->dma_coherent_handle2);
4088 acb->msgcode_rwbuffer[6] = upper_32_bits(acb->dma_coherent_handle2);
4089 acb->msgcode_rwbuffer[7] = acb->completeQ_size;
4090 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
4091 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4092 writel(acb->out_doorbell, ®->iobound_doorbell);
4093 if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
4094 pr_notice("arcmsr%d: 'set command Q window' timeout\n",
4095 acb->host->host_no);
4096 return 1;
4097 }
4098 }
4099 break;
4100 }
4101 return 0;
4102}
4103
4104static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
4105{
4106 uint32_t firmware_state = 0;
4107 switch (acb->adapter_type) {
4108
4109 case ACB_ADAPTER_TYPE_A: {
4110 struct MessageUnit_A __iomem *reg = acb->pmuA;
4111 do {
4112 if (!(acb->acb_flags & ACB_F_IOP_INITED))
4113 msleep(20);
4114 firmware_state = readl(®->outbound_msgaddr1);
4115 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
4116 }
4117 break;
4118
4119 case ACB_ADAPTER_TYPE_B: {
4120 struct MessageUnit_B *reg = acb->pmuB;
4121 do {
4122 if (!(acb->acb_flags & ACB_F_IOP_INITED))
4123 msleep(20);
4124 firmware_state = readl(reg->iop2drv_doorbell);
4125 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
4126 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
4127 }
4128 break;
4129 case ACB_ADAPTER_TYPE_C: {
4130 struct MessageUnit_C __iomem *reg = acb->pmuC;
4131 do {
4132 if (!(acb->acb_flags & ACB_F_IOP_INITED))
4133 msleep(20);
4134 firmware_state = readl(®->outbound_msgaddr1);
4135 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
4136 }
4137 break;
4138 case ACB_ADAPTER_TYPE_D: {
4139 struct MessageUnit_D *reg = acb->pmuD;
4140 do {
4141 if (!(acb->acb_flags & ACB_F_IOP_INITED))
4142 msleep(20);
4143 firmware_state = readl(reg->outbound_msgaddr1);
4144 } while ((firmware_state &
4145 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
4146 }
4147 break;
4148 case ACB_ADAPTER_TYPE_E:
4149 case ACB_ADAPTER_TYPE_F: {
4150 struct MessageUnit_E __iomem *reg = acb->pmuE;
4151 do {
4152 if (!(acb->acb_flags & ACB_F_IOP_INITED))
4153 msleep(20);
4154 firmware_state = readl(®->outbound_msgaddr1);
4155 } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0);
4156 }
4157 break;
4158 }
4159}
4160
4161static void arcmsr_request_device_map(struct timer_list *t)
4162{
4163 struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer);
4164 if (acb->acb_flags & (ACB_F_MSG_GET_CONFIG | ACB_F_BUS_RESET | ACB_F_ABORT)) {
4165 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
4166 } else {
4167 acb->fw_flag = FW_NORMAL;
4168 switch (acb->adapter_type) {
4169 case ACB_ADAPTER_TYPE_A: {
4170 struct MessageUnit_A __iomem *reg = acb->pmuA;
4171 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
4172 break;
4173 }
4174 case ACB_ADAPTER_TYPE_B: {
4175 struct MessageUnit_B *reg = acb->pmuB;
4176 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
4177 break;
4178 }
4179 case ACB_ADAPTER_TYPE_C: {
4180 struct MessageUnit_C __iomem *reg = acb->pmuC;
4181 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
4182 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
4183 break;
4184 }
4185 case ACB_ADAPTER_TYPE_D: {
4186 struct MessageUnit_D *reg = acb->pmuD;
4187 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
4188 break;
4189 }
4190 case ACB_ADAPTER_TYPE_E: {
4191 struct MessageUnit_E __iomem *reg = acb->pmuE;
4192 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
4193 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4194 writel(acb->out_doorbell, ®->iobound_doorbell);
4195 break;
4196 }
4197 case ACB_ADAPTER_TYPE_F: {
4198 struct MessageUnit_F __iomem *reg = acb->pmuF;
4199 uint32_t outMsg1 = readl(®->outbound_msgaddr1);
4200
4201 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) ||
4202 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE))
4203 goto nxt6s;
4204 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
4205 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4206 writel(acb->out_doorbell, ®->iobound_doorbell);
4207 break;
4208 }
4209 default:
4210 return;
4211 }
4212 acb->acb_flags |= ACB_F_MSG_GET_CONFIG;
4213nxt6s:
4214 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
4215 }
4216}
4217
4218static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
4219{
4220 struct MessageUnit_A __iomem *reg = acb->pmuA;
4221 acb->acb_flags |= ACB_F_MSG_START_BGRB;
4222 writel(ARCMSR_INBOUND_MESG0_START_BGRB, ®->inbound_msgaddr0);
4223 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
4224 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
4225 rebuild' timeout \n", acb->host->host_no);
4226 }
4227}
4228
4229static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
4230{
4231 struct MessageUnit_B *reg = acb->pmuB;
4232 acb->acb_flags |= ACB_F_MSG_START_BGRB;
4233 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
4234 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
4235 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
4236 rebuild' timeout \n",acb->host->host_no);
4237 }
4238}
4239
4240static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
4241{
4242 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
4243 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
4244 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
4245 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
4246 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
4247 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
4248 rebuild' timeout \n", pACB->host->host_no);
4249 }
4250 return;
4251}
4252
4253static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
4254{
4255 struct MessageUnit_D *pmu = pACB->pmuD;
4256
4257 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
4258 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
4259 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
4260 pr_notice("arcmsr%d: wait 'start adapter "
4261 "background rebuild' timeout\n", pACB->host->host_no);
4262 }
4263}
4264
4265static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB)
4266{
4267 struct MessageUnit_E __iomem *pmu = pACB->pmuE;
4268
4269 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
4270 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0);
4271 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4272 writel(pACB->out_doorbell, &pmu->iobound_doorbell);
4273 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
4274 pr_notice("arcmsr%d: wait 'start adapter "
4275 "background rebuild' timeout \n", pACB->host->host_no);
4276 }
4277}
4278
4279static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
4280{
4281 switch (acb->adapter_type) {
4282 case ACB_ADAPTER_TYPE_A:
4283 arcmsr_hbaA_start_bgrb(acb);
4284 break;
4285 case ACB_ADAPTER_TYPE_B:
4286 arcmsr_hbaB_start_bgrb(acb);
4287 break;
4288 case ACB_ADAPTER_TYPE_C:
4289 arcmsr_hbaC_start_bgrb(acb);
4290 break;
4291 case ACB_ADAPTER_TYPE_D:
4292 arcmsr_hbaD_start_bgrb(acb);
4293 break;
4294 case ACB_ADAPTER_TYPE_E:
4295 case ACB_ADAPTER_TYPE_F:
4296 arcmsr_hbaE_start_bgrb(acb);
4297 break;
4298 }
4299}
4300
4301static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
4302{
4303 switch (acb->adapter_type) {
4304 case ACB_ADAPTER_TYPE_A: {
4305 struct MessageUnit_A __iomem *reg = acb->pmuA;
4306 uint32_t outbound_doorbell;
4307
4308 outbound_doorbell = readl(®->outbound_doorbell);
4309
4310 writel(outbound_doorbell, ®->outbound_doorbell);
4311 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell);
4312 }
4313 break;
4314
4315 case ACB_ADAPTER_TYPE_B: {
4316 struct MessageUnit_B *reg = acb->pmuB;
4317 uint32_t outbound_doorbell, i;
4318 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
4319 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
4320
4321 for(i=0; i < 200; i++) {
4322 msleep(20);
4323 outbound_doorbell = readl(reg->iop2drv_doorbell);
4324 if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
4325 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
4326 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
4327 } else
4328 break;
4329 }
4330 }
4331 break;
4332 case ACB_ADAPTER_TYPE_C: {
4333 struct MessageUnit_C __iomem *reg = acb->pmuC;
4334 uint32_t outbound_doorbell, i;
4335
4336 outbound_doorbell = readl(®->outbound_doorbell);
4337 writel(outbound_doorbell, ®->outbound_doorbell_clear);
4338 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell);
4339 for (i = 0; i < 200; i++) {
4340 msleep(20);
4341 outbound_doorbell = readl(®->outbound_doorbell);
4342 if (outbound_doorbell &
4343 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
4344 writel(outbound_doorbell,
4345 ®->outbound_doorbell_clear);
4346 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
4347 ®->inbound_doorbell);
4348 } else
4349 break;
4350 }
4351 }
4352 break;
4353 case ACB_ADAPTER_TYPE_D: {
4354 struct MessageUnit_D *reg = acb->pmuD;
4355 uint32_t outbound_doorbell, i;
4356
4357 outbound_doorbell = readl(reg->outbound_doorbell);
4358 writel(outbound_doorbell, reg->outbound_doorbell);
4359 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
4360 reg->inbound_doorbell);
4361 for (i = 0; i < 200; i++) {
4362 msleep(20);
4363 outbound_doorbell = readl(reg->outbound_doorbell);
4364 if (outbound_doorbell &
4365 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
4366 writel(outbound_doorbell,
4367 reg->outbound_doorbell);
4368 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
4369 reg->inbound_doorbell);
4370 } else
4371 break;
4372 }
4373 }
4374 break;
4375 case ACB_ADAPTER_TYPE_E:
4376 case ACB_ADAPTER_TYPE_F: {
4377 struct MessageUnit_E __iomem *reg = acb->pmuE;
4378 uint32_t i, tmp;
4379
4380 acb->in_doorbell = readl(®->iobound_doorbell);
4381 writel(0, ®->host_int_status);
4382 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4383 writel(acb->out_doorbell, ®->iobound_doorbell);
4384 for(i=0; i < 200; i++) {
4385 msleep(20);
4386 tmp = acb->in_doorbell;
4387 acb->in_doorbell = readl(®->iobound_doorbell);
4388 if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
4389 writel(0, ®->host_int_status);
4390 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4391 writel(acb->out_doorbell, ®->iobound_doorbell);
4392 } else
4393 break;
4394 }
4395 }
4396 break;
4397 }
4398}
4399
4400static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
4401{
4402 switch (acb->adapter_type) {
4403 case ACB_ADAPTER_TYPE_A:
4404 return;
4405 case ACB_ADAPTER_TYPE_B:
4406 {
4407 struct MessageUnit_B *reg = acb->pmuB;
4408 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
4409 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
4410 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
4411 return;
4412 }
4413 }
4414 break;
4415 case ACB_ADAPTER_TYPE_C:
4416 return;
4417 }
4418 return;
4419}
4420
4421static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
4422{
4423 uint8_t value[64];
4424 int i, count = 0;
4425 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
4426 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
4427 struct MessageUnit_D *pmuD = acb->pmuD;
4428
4429
4430 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
4431 for (i = 0; i < 64; i++) {
4432 pci_read_config_byte(acb->pdev, i, &value[i]);
4433 }
4434
4435 if (acb->dev_id == 0x1680) {
4436 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
4437 } else if (acb->dev_id == 0x1880) {
4438 do {
4439 count++;
4440 writel(0xF, &pmuC->write_sequence);
4441 writel(0x4, &pmuC->write_sequence);
4442 writel(0xB, &pmuC->write_sequence);
4443 writel(0x2, &pmuC->write_sequence);
4444 writel(0x7, &pmuC->write_sequence);
4445 writel(0xD, &pmuC->write_sequence);
4446 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
4447 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
4448 } else if (acb->dev_id == 0x1884) {
4449 struct MessageUnit_E __iomem *pmuE = acb->pmuE;
4450 do {
4451 count++;
4452 writel(0x4, &pmuE->write_sequence_3xxx);
4453 writel(0xB, &pmuE->write_sequence_3xxx);
4454 writel(0x2, &pmuE->write_sequence_3xxx);
4455 writel(0x7, &pmuE->write_sequence_3xxx);
4456 writel(0xD, &pmuE->write_sequence_3xxx);
4457 mdelay(10);
4458 } while (((readl(&pmuE->host_diagnostic_3xxx) &
4459 ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5));
4460 writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx);
4461 } else if (acb->dev_id == 0x1214) {
4462 writel(0x20, pmuD->reset_request);
4463 } else {
4464 pci_write_config_byte(acb->pdev, 0x84, 0x20);
4465 }
4466 msleep(2000);
4467
4468 for (i = 0; i < 64; i++) {
4469 pci_write_config_byte(acb->pdev, i, value[i]);
4470 }
4471 msleep(1000);
4472 return;
4473}
4474
4475static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb)
4476{
4477 bool rtn = true;
4478
4479 switch(acb->adapter_type) {
4480 case ACB_ADAPTER_TYPE_A:{
4481 struct MessageUnit_A __iomem *reg = acb->pmuA;
4482 rtn = ((readl(®->outbound_msgaddr1) &
4483 ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false;
4484 }
4485 break;
4486 case ACB_ADAPTER_TYPE_B:{
4487 struct MessageUnit_B *reg = acb->pmuB;
4488 rtn = ((readl(reg->iop2drv_doorbell) &
4489 ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false;
4490 }
4491 break;
4492 case ACB_ADAPTER_TYPE_C:{
4493 struct MessageUnit_C __iomem *reg = acb->pmuC;
4494 rtn = (readl(®->host_diagnostic) & 0x04) ? true : false;
4495 }
4496 break;
4497 case ACB_ADAPTER_TYPE_D:{
4498 struct MessageUnit_D *reg = acb->pmuD;
4499 rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ?
4500 true : false;
4501 }
4502 break;
4503 case ACB_ADAPTER_TYPE_E:
4504 case ACB_ADAPTER_TYPE_F:{
4505 struct MessageUnit_E __iomem *reg = acb->pmuE;
4506 rtn = (readl(®->host_diagnostic_3xxx) &
4507 ARCMSR_ARC188X_RESET_ADAPTER) ? true : false;
4508 }
4509 break;
4510 }
4511 return rtn;
4512}
4513
4514static void arcmsr_iop_init(struct AdapterControlBlock *acb)
4515{
4516 uint32_t intmask_org;
4517
4518 intmask_org = arcmsr_disable_outbound_ints(acb);
4519 arcmsr_wait_firmware_ready(acb);
4520 arcmsr_iop_confirm(acb);
4521
4522 arcmsr_start_adapter_bgrb(acb);
4523
4524 arcmsr_clear_doorbell_queue_buffer(acb);
4525 arcmsr_enable_eoi_mode(acb);
4526
4527 arcmsr_enable_outbound_ints(acb, intmask_org);
4528 acb->acb_flags |= ACB_F_IOP_INITED;
4529}
4530
4531static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
4532{
4533 struct CommandControlBlock *ccb;
4534 uint32_t intmask_org;
4535 uint8_t rtnval = 0x00;
4536 int i = 0;
4537 unsigned long flags;
4538
4539 if (atomic_read(&acb->ccboutstandingcount) != 0) {
4540
4541 intmask_org = arcmsr_disable_outbound_ints(acb);
4542
4543 rtnval = arcmsr_abort_allcmd(acb);
4544
4545 arcmsr_done4abort_postqueue(acb);
4546 for (i = 0; i < acb->maxFreeCCB; i++) {
4547 ccb = acb->pccb_pool[i];
4548 if (ccb->startdone == ARCMSR_CCB_START) {
4549 scsi_dma_unmap(ccb->pcmd);
4550 ccb->startdone = ARCMSR_CCB_DONE;
4551 ccb->ccb_flags = 0;
4552 spin_lock_irqsave(&acb->ccblist_lock, flags);
4553 list_add_tail(&ccb->list, &acb->ccb_free_list);
4554 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
4555 }
4556 }
4557 atomic_set(&acb->ccboutstandingcount, 0);
4558
4559 arcmsr_enable_outbound_ints(acb, intmask_org);
4560 return rtnval;
4561 }
4562 return rtnval;
4563}
4564
4565static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
4566{
4567 struct AdapterControlBlock *acb;
4568 int retry_count = 0;
4569 int rtn = FAILED;
4570 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
4571 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
4572 return SUCCESS;
4573 pr_notice("arcmsr: executing bus reset eh.....num_resets = %d,"
4574 " num_aborts = %d \n", acb->num_resets, acb->num_aborts);
4575 acb->num_resets++;
4576
4577 if (acb->acb_flags & ACB_F_BUS_RESET) {
4578 long timeout;
4579 pr_notice("arcmsr: there is a bus reset eh proceeding...\n");
4580 timeout = wait_event_timeout(wait_q, (acb->acb_flags
4581 & ACB_F_BUS_RESET) == 0, 220 * HZ);
4582 if (timeout)
4583 return SUCCESS;
4584 }
4585 acb->acb_flags |= ACB_F_BUS_RESET;
4586 if (!arcmsr_iop_reset(acb)) {
4587 arcmsr_hardware_reset(acb);
4588 acb->acb_flags &= ~ACB_F_IOP_INITED;
4589wait_reset_done:
4590 ssleep(ARCMSR_SLEEPTIME);
4591 if (arcmsr_reset_in_progress(acb)) {
4592 if (retry_count > ARCMSR_RETRYCOUNT) {
4593 acb->fw_flag = FW_DEADLOCK;
4594 pr_notice("arcmsr%d: waiting for hw bus reset"
4595 " return, RETRY TERMINATED!!\n",
4596 acb->host->host_no);
4597 return FAILED;
4598 }
4599 retry_count++;
4600 goto wait_reset_done;
4601 }
4602 arcmsr_iop_init(acb);
4603 acb->fw_flag = FW_NORMAL;
4604 mod_timer(&acb->eternal_timer, jiffies +
4605 msecs_to_jiffies(6 * HZ));
4606 acb->acb_flags &= ~ACB_F_BUS_RESET;
4607 rtn = SUCCESS;
4608 pr_notice("arcmsr: scsi bus reset eh returns with success\n");
4609 } else {
4610 acb->acb_flags &= ~ACB_F_BUS_RESET;
4611 acb->fw_flag = FW_NORMAL;
4612 mod_timer(&acb->eternal_timer, jiffies +
4613 msecs_to_jiffies(6 * HZ));
4614 rtn = SUCCESS;
4615 }
4616 return rtn;
4617}
4618
4619static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
4620 struct CommandControlBlock *ccb)
4621{
4622 int rtn;
4623 rtn = arcmsr_polling_ccbdone(acb, ccb);
4624 return rtn;
4625}
4626
4627static int arcmsr_abort(struct scsi_cmnd *cmd)
4628{
4629 struct AdapterControlBlock *acb =
4630 (struct AdapterControlBlock *)cmd->device->host->hostdata;
4631 int i = 0;
4632 int rtn = FAILED;
4633 uint32_t intmask_org;
4634
4635 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
4636 return SUCCESS;
4637 printk(KERN_NOTICE
4638 "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
4639 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
4640 acb->acb_flags |= ACB_F_ABORT;
4641 acb->num_aborts++;
4642
4643
4644
4645
4646
4647
4648 if (!atomic_read(&acb->ccboutstandingcount)) {
4649 acb->acb_flags &= ~ACB_F_ABORT;
4650 return rtn;
4651 }
4652
4653 intmask_org = arcmsr_disable_outbound_ints(acb);
4654 for (i = 0; i < acb->maxFreeCCB; i++) {
4655 struct CommandControlBlock *ccb = acb->pccb_pool[i];
4656 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
4657 ccb->startdone = ARCMSR_CCB_ABORTED;
4658 rtn = arcmsr_abort_one_cmd(acb, ccb);
4659 break;
4660 }
4661 }
4662 acb->acb_flags &= ~ACB_F_ABORT;
4663 arcmsr_enable_outbound_ints(acb, intmask_org);
4664 return rtn;
4665}
4666
4667static const char *arcmsr_info(struct Scsi_Host *host)
4668{
4669 struct AdapterControlBlock *acb =
4670 (struct AdapterControlBlock *) host->hostdata;
4671 static char buf[256];
4672 char *type;
4673 int raid6 = 1;
4674 switch (acb->pdev->device) {
4675 case PCI_DEVICE_ID_ARECA_1110:
4676 case PCI_DEVICE_ID_ARECA_1200:
4677 case PCI_DEVICE_ID_ARECA_1202:
4678 case PCI_DEVICE_ID_ARECA_1210:
4679 raid6 = 0;
4680 fallthrough;
4681 case PCI_DEVICE_ID_ARECA_1120:
4682 case PCI_DEVICE_ID_ARECA_1130:
4683 case PCI_DEVICE_ID_ARECA_1160:
4684 case PCI_DEVICE_ID_ARECA_1170:
4685 case PCI_DEVICE_ID_ARECA_1201:
4686 case PCI_DEVICE_ID_ARECA_1203:
4687 case PCI_DEVICE_ID_ARECA_1220:
4688 case PCI_DEVICE_ID_ARECA_1230:
4689 case PCI_DEVICE_ID_ARECA_1260:
4690 case PCI_DEVICE_ID_ARECA_1270:
4691 case PCI_DEVICE_ID_ARECA_1280:
4692 type = "SATA";
4693 break;
4694 case PCI_DEVICE_ID_ARECA_1214:
4695 case PCI_DEVICE_ID_ARECA_1380:
4696 case PCI_DEVICE_ID_ARECA_1381:
4697 case PCI_DEVICE_ID_ARECA_1680:
4698 case PCI_DEVICE_ID_ARECA_1681:
4699 case PCI_DEVICE_ID_ARECA_1880:
4700 case PCI_DEVICE_ID_ARECA_1884:
4701 type = "SAS/SATA";
4702 break;
4703 case PCI_DEVICE_ID_ARECA_1886:
4704 type = "NVMe/SAS/SATA";
4705 break;
4706 default:
4707 type = "unknown";
4708 raid6 = 0;
4709 break;
4710 }
4711 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
4712 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
4713 return buf;
4714}
4715
