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23#define FDMI_DID 0xfffffaU
24#define NameServer_DID 0xfffffcU
25#define Fabric_Cntl_DID 0xfffffdU
26#define Fabric_DID 0xfffffeU
27#define Bcast_DID 0xffffffU
28#define Mask_DID 0xffffffU
29#define CT_DID_MASK 0xffff00U
30#define Fabric_DID_MASK 0xfff000U
31#define WELL_KNOWN_DID_MASK 0xfffff0U
32
33#define PT2PT_LocalID 1
34#define PT2PT_RemoteID 2
35
36#define FF_DEF_EDTOV 2000
37#define FF_DEF_ALTOV 15
38#define FF_DEF_RATOV 10
39#define FF_DEF_ARBTOV 1900
40
41#define LPFC_BUF_RING0 64
42
43
44#define FCELSSIZE 1024
45
46#define LPFC_FCP_RING 0
47#define LPFC_EXTRA_RING 1
48#define LPFC_ELS_RING 2
49
50#define SLI2_IOCB_CMD_R0_ENTRIES 172
51#define SLI2_IOCB_RSP_R0_ENTRIES 134
52#define SLI2_IOCB_CMD_R1_ENTRIES 4
53#define SLI2_IOCB_RSP_R1_ENTRIES 4
54#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36
55#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52
56#define SLI2_IOCB_CMD_R2_ENTRIES 20
57#define SLI2_IOCB_RSP_R2_ENTRIES 20
58#define SLI2_IOCB_CMD_R3_ENTRIES 0
59#define SLI2_IOCB_RSP_R3_ENTRIES 0
60#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63#define SLI2_IOCB_CMD_SIZE 32
64#define SLI2_IOCB_RSP_SIZE 32
65#define SLI3_IOCB_CMD_SIZE 128
66#define SLI3_IOCB_RSP_SIZE 64
67
68#define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69#define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71
72#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74#define FW_REV_STR_SIZE 32
75
76
77union CtRevisionId {
78
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84};
85
86union CtCommandResponse {
87
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93};
94
95
96#define FC4_FEATURE_TARGET 0x1
97#define FC4_FEATURE_INIT 0x2
98#define FC4_FEATURE_NVME_DISC 0x4
99
100struct lpfc_sli_ct_request {
101
102 union CtRevisionId RevisionId;
103 uint8_t FsType;
104 uint8_t FsSubType;
105 uint8_t Options;
106 uint8_t Rsrvd1;
107 union CtCommandResponse CommandResponse;
108 uint8_t Rsrvd2;
109 uint8_t ReasonCode;
110 uint8_t Explanation;
111 uint8_t VendorUnique;
112#define LPFC_CT_PREAMBLE 20
113
114 union {
115 uint32_t PortID;
116 struct gid {
117 uint8_t PortType;
118#define GID_PT_N_PORT 1
119 uint8_t DomainScope;
120 uint8_t AreaScope;
121 uint8_t Fc4Type;
122 } gid;
123 struct gid_ff {
124 uint8_t Flags;
125 uint8_t DomainScope;
126 uint8_t AreaScope;
127 uint8_t rsvd1;
128 uint8_t rsvd2;
129 uint8_t rsvd3;
130 uint8_t Fc4FBits;
131 uint8_t Fc4Type;
132 } gid_ff;
133 struct rft {
134 uint32_t PortId;
135
136#ifdef __BIG_ENDIAN_BITFIELD
137 uint32_t rsvd0:16;
138 uint32_t rsvd1:7;
139 uint32_t fcpReg:1;
140 uint32_t rsvd2:2;
141 uint32_t ipReg:1;
142 uint32_t rsvd3:5;
143#else
144 uint32_t rsvd0:16;
145 uint32_t fcpReg:1;
146 uint32_t rsvd1:7;
147 uint32_t rsvd3:5;
148 uint32_t ipReg:1;
149 uint32_t rsvd2:2;
150#endif
151
152 uint32_t rsvd[7];
153 } rft;
154 struct rnn {
155 uint32_t PortId;
156 uint8_t wwnn[8];
157 } rnn;
158 struct rsnn {
159 uint8_t wwnn[8];
160 uint8_t len;
161 uint8_t symbname[255];
162 } rsnn;
163 struct da_id {
164 uint32_t port_id;
165 } da_id;
166 struct rspn {
167 uint32_t PortId;
168 uint8_t len;
169 uint8_t symbname[255];
170 } rspn;
171 struct gff {
172 uint32_t PortId;
173 } gff;
174 struct gff_acc {
175 uint8_t fbits[128];
176 } gff_acc;
177 struct gft {
178 uint32_t PortId;
179 } gft;
180 struct gft_acc {
181 uint32_t fc4_types[8];
182 } gft_acc;
183#define FCP_TYPE_FEATURE_OFFSET 7
184 struct rff {
185 uint32_t PortId;
186 uint8_t reserved[2];
187 uint8_t fbits;
188 uint8_t type_code;
189 } rff;
190 } un;
191};
192
193#define LPFC_MAX_CT_SIZE (60 * 4096)
194
195#define SLI_CT_REVISION 1
196#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
197 sizeof(struct gid))
198#define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
199 sizeof(struct gid_ff))
200#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
201 sizeof(struct gff))
202#define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
203 sizeof(struct gft))
204#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
205 sizeof(struct rft))
206#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
207 sizeof(struct rff))
208#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
209 sizeof(struct rnn))
210#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
211 sizeof(struct rsnn))
212#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
213 sizeof(struct da_id))
214#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
215 sizeof(struct rspn))
216
217
218
219
220
221#define SLI_CT_MANAGEMENT_SERVICE 0xFA
222#define SLI_CT_TIME_SERVICE 0xFB
223#define SLI_CT_DIRECTORY_SERVICE 0xFC
224#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
225
226
227
228
229
230#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
231
232
233
234
235
236#define SLI_CT_RESPONSE_FS_RJT 0x8001
237#define SLI_CT_RESPONSE_FS_ACC 0x8002
238
239
240
241
242
243#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
244#define SLI_CT_INVALID_COMMAND 0x01
245#define SLI_CT_INVALID_VERSION 0x02
246#define SLI_CT_LOGICAL_ERROR 0x03
247#define SLI_CT_INVALID_IU_SIZE 0x04
248#define SLI_CT_LOGICAL_BUSY 0x05
249#define SLI_CT_PROTOCOL_ERROR 0x07
250#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
251#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
252#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
253#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
254#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
255#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
256#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
257#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
258#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
259#define SLI_CT_VENDOR_UNIQUE 0xff
260
261
262
263
264
265#define SLI_CT_NO_PORT_ID 0x01
266#define SLI_CT_NO_PORT_NAME 0x02
267#define SLI_CT_NO_NODE_NAME 0x03
268#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
269#define SLI_CT_NO_IP_ADDRESS 0x05
270#define SLI_CT_NO_IPA 0x06
271#define SLI_CT_NO_FC4_TYPES 0x07
272#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
273#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
274#define SLI_CT_NO_PORT_TYPE 0x0A
275#define SLI_CT_ACCESS_DENIED 0x10
276#define SLI_CT_INVALID_PORT_ID 0x11
277#define SLI_CT_DATABASE_EMPTY 0x12
278
279
280
281
282
283#define SLI_CTNS_GA_NXT 0x0100
284#define SLI_CTNS_GPN_ID 0x0112
285#define SLI_CTNS_GNN_ID 0x0113
286#define SLI_CTNS_GCS_ID 0x0114
287#define SLI_CTNS_GFT_ID 0x0117
288#define SLI_CTNS_GSPN_ID 0x0118
289#define SLI_CTNS_GPT_ID 0x011A
290#define SLI_CTNS_GFF_ID 0x011F
291#define SLI_CTNS_GID_PN 0x0121
292#define SLI_CTNS_GID_NN 0x0131
293#define SLI_CTNS_GIP_NN 0x0135
294#define SLI_CTNS_GIPA_NN 0x0136
295#define SLI_CTNS_GSNN_NN 0x0139
296#define SLI_CTNS_GNN_IP 0x0153
297#define SLI_CTNS_GIPA_IP 0x0156
298#define SLI_CTNS_GID_FT 0x0171
299#define SLI_CTNS_GID_FF 0x01F1
300#define SLI_CTNS_GID_PT 0x01A1
301#define SLI_CTNS_RPN_ID 0x0212
302#define SLI_CTNS_RNN_ID 0x0213
303#define SLI_CTNS_RCS_ID 0x0214
304#define SLI_CTNS_RFT_ID 0x0217
305#define SLI_CTNS_RSPN_ID 0x0218
306#define SLI_CTNS_RPT_ID 0x021A
307#define SLI_CTNS_RFF_ID 0x021F
308#define SLI_CTNS_RIP_NN 0x0235
309#define SLI_CTNS_RIPA_NN 0x0236
310#define SLI_CTNS_RSNN_NN 0x0239
311#define SLI_CTNS_DA_ID 0x0300
312
313
314
315
316
317#define SLI_CTPT_N_PORT 0x01
318#define SLI_CTPT_NL_PORT 0x02
319#define SLI_CTPT_FNL_PORT 0x03
320#define SLI_CTPT_IP 0x04
321#define SLI_CTPT_FCP 0x08
322#define SLI_CTPT_NVME 0x28
323#define SLI_CTPT_NX_PORT 0x7F
324#define SLI_CTPT_F_PORT 0x81
325#define SLI_CTPT_FL_PORT 0x82
326#define SLI_CTPT_E_PORT 0x84
327
328#define SLI_CT_LAST_ENTRY 0x80000000
329
330
331
332#define FC_PH_4_0 6
333#define FC_PH_4_1 7
334#define FC_PH_4_2 8
335#define FC_PH_4_3 9
336
337#define FC_PH_LOW 8
338#define FC_PH_HIGH 9
339#define FC_PH3 0x20
340
341#define FF_FRAME_SIZE 2048
342
343struct lpfc_name {
344 union {
345 struct {
346#ifdef __BIG_ENDIAN_BITFIELD
347 uint8_t nameType:4;
348 uint8_t IEEEextMsn:4;
349
350#else
351 uint8_t IEEEextMsn:4;
352
353 uint8_t nameType:4;
354#endif
355
356#define NAME_IEEE 0x1
357#define NAME_IEEE_EXT 0x2
358#define NAME_FC_TYPE 0x3
359#define NAME_IP_TYPE 0x4
360#define NAME_CCITT_TYPE 0xC
361#define NAME_CCITT_GR_TYPE 0xE
362 uint8_t IEEEextLsb;
363
364 uint8_t IEEE[6];
365 } s;
366 uint8_t wwn[8];
367 uint64_t name;
368 } u;
369};
370
371struct csp {
372 uint8_t fcphHigh;
373 uint8_t fcphLow;
374 uint8_t bbCreditMsb;
375 uint8_t bbCreditLsb;
376
377
378
379
380
381
382#define clean_address_bit request_multiple_Nport
383
384
385
386
387
388#define virtual_fabric_support randomOffset
389
390
391
392
393
394#define valid_vendor_ver_level response_multiple_NPort
395#ifdef __BIG_ENDIAN_BITFIELD
396 uint16_t request_multiple_Nport:1;
397 uint16_t randomOffset:1;
398 uint16_t response_multiple_NPort:1;
399 uint16_t fPort:1;
400 uint16_t altBbCredit:1;
401 uint16_t edtovResolution:1;
402 uint16_t multicast:1;
403 uint16_t broadcast:1;
404
405 uint16_t huntgroup:1;
406 uint16_t simplex:1;
407 uint16_t word1Reserved1:3;
408 uint16_t dhd:1;
409 uint16_t contIncSeqCnt:1;
410 uint16_t payloadlength:1;
411#else
412 uint16_t broadcast:1;
413 uint16_t multicast:1;
414 uint16_t edtovResolution:1;
415 uint16_t altBbCredit:1;
416 uint16_t fPort:1;
417 uint16_t response_multiple_NPort:1;
418 uint16_t randomOffset:1;
419 uint16_t request_multiple_Nport:1;
420
421 uint16_t payloadlength:1;
422 uint16_t contIncSeqCnt:1;
423 uint16_t dhd:1;
424 uint16_t word1Reserved1:3;
425 uint16_t simplex:1;
426 uint16_t huntgroup:1;
427#endif
428
429 uint8_t bbRcvSizeMsb;
430 uint8_t bbRcvSizeLsb;
431 union {
432 struct {
433 uint8_t word2Reserved1;
434
435 uint8_t totalConcurrSeq;
436 uint8_t roByCategoryMsb;
437
438 uint8_t roByCategoryLsb;
439 } nPort;
440 uint32_t r_a_tov;
441 } w2;
442
443 uint32_t e_d_tov;
444};
445
446struct class_parms {
447#ifdef __BIG_ENDIAN_BITFIELD
448 uint8_t classValid:1;
449 uint8_t intermix:1;
450 uint8_t stackedXparent:1;
451 uint8_t stackedLockDown:1;
452 uint8_t seqDelivery:1;
453 uint8_t word0Reserved1:3;
454#else
455 uint8_t word0Reserved1:3;
456 uint8_t seqDelivery:1;
457 uint8_t stackedLockDown:1;
458 uint8_t stackedXparent:1;
459 uint8_t intermix:1;
460 uint8_t classValid:1;
461
462#endif
463
464 uint8_t word0Reserved2;
465
466#ifdef __BIG_ENDIAN_BITFIELD
467 uint8_t iCtlXidReAssgn:2;
468 uint8_t iCtlInitialPa:2;
469 uint8_t iCtlAck0capable:1;
470 uint8_t iCtlAckNcapable:1;
471 uint8_t word0Reserved3:2;
472#else
473 uint8_t word0Reserved3:2;
474 uint8_t iCtlAckNcapable:1;
475 uint8_t iCtlAck0capable:1;
476 uint8_t iCtlInitialPa:2;
477 uint8_t iCtlXidReAssgn:2;
478#endif
479
480 uint8_t word0Reserved4;
481
482#ifdef __BIG_ENDIAN_BITFIELD
483 uint8_t rCtlAck0capable:1;
484 uint8_t rCtlAckNcapable:1;
485 uint8_t rCtlXidInterlck:1;
486 uint8_t rCtlErrorPolicy:2;
487 uint8_t word1Reserved1:1;
488 uint8_t rCtlCatPerSeq:2;
489#else
490 uint8_t rCtlCatPerSeq:2;
491 uint8_t word1Reserved1:1;
492 uint8_t rCtlErrorPolicy:2;
493 uint8_t rCtlXidInterlck:1;
494 uint8_t rCtlAckNcapable:1;
495 uint8_t rCtlAck0capable:1;
496#endif
497
498 uint8_t word1Reserved2;
499 uint8_t rcvDataSizeMsb;
500 uint8_t rcvDataSizeLsb;
501
502 uint8_t concurrentSeqMsb;
503 uint8_t concurrentSeqLsb;
504 uint8_t EeCreditSeqMsb;
505 uint8_t EeCreditSeqLsb;
506
507 uint8_t openSeqPerXchgMsb;
508 uint8_t openSeqPerXchgLsb;
509 uint8_t word3Reserved1;
510 uint8_t word3Reserved2;
511};
512
513#define FAPWWN_KEY_VENDOR 0x42524344
514
515struct serv_parm {
516 struct csp cmn;
517 struct lpfc_name portName;
518 struct lpfc_name nodeName;
519 struct class_parms cls1;
520 struct class_parms cls2;
521 struct class_parms cls3;
522 struct class_parms cls4;
523 union {
524 uint8_t vendorVersion[16];
525 struct {
526 uint32_t vid;
527#define LPFC_VV_EMLX_ID 0x454d4c58
528 uint32_t flags;
529#define LPFC_VV_SUPPRESS_RSP 1
530 } vv;
531 } un;
532};
533
534
535
536
537struct fc_vft_header {
538 uint32_t word0;
539#define fc_vft_hdr_r_ctl_SHIFT 24
540#define fc_vft_hdr_r_ctl_MASK 0xFF
541#define fc_vft_hdr_r_ctl_WORD word0
542#define fc_vft_hdr_ver_SHIFT 22
543#define fc_vft_hdr_ver_MASK 0x3
544#define fc_vft_hdr_ver_WORD word0
545#define fc_vft_hdr_type_SHIFT 18
546#define fc_vft_hdr_type_MASK 0xF
547#define fc_vft_hdr_type_WORD word0
548#define fc_vft_hdr_e_SHIFT 16
549#define fc_vft_hdr_e_MASK 0x1
550#define fc_vft_hdr_e_WORD word0
551#define fc_vft_hdr_priority_SHIFT 13
552#define fc_vft_hdr_priority_MASK 0x7
553#define fc_vft_hdr_priority_WORD word0
554#define fc_vft_hdr_vf_id_SHIFT 1
555#define fc_vft_hdr_vf_id_MASK 0xFFF
556#define fc_vft_hdr_vf_id_WORD word0
557 uint32_t word1;
558#define fc_vft_hdr_hopct_SHIFT 24
559#define fc_vft_hdr_hopct_MASK 0xFF
560#define fc_vft_hdr_hopct_WORD word1
561};
562
563#include <uapi/scsi/fc/fc_els.h>
564
565
566
567
568#ifdef __BIG_ENDIAN_BITFIELD
569#define ELS_CMD_MASK 0xffff0000
570#define ELS_RSP_MASK 0xff000000
571#define ELS_CMD_LS_RJT 0x01000000
572#define ELS_CMD_ACC 0x02000000
573#define ELS_CMD_PLOGI 0x03000000
574#define ELS_CMD_FLOGI 0x04000000
575#define ELS_CMD_LOGO 0x05000000
576#define ELS_CMD_ABTX 0x06000000
577#define ELS_CMD_RCS 0x07000000
578#define ELS_CMD_RES 0x08000000
579#define ELS_CMD_RSS 0x09000000
580#define ELS_CMD_RSI 0x0A000000
581#define ELS_CMD_ESTS 0x0B000000
582#define ELS_CMD_ESTC 0x0C000000
583#define ELS_CMD_ADVC 0x0D000000
584#define ELS_CMD_RTV 0x0E000000
585#define ELS_CMD_RLS 0x0F000000
586#define ELS_CMD_ECHO 0x10000000
587#define ELS_CMD_TEST 0x11000000
588#define ELS_CMD_RRQ 0x12000000
589#define ELS_CMD_REC 0x13000000
590#define ELS_CMD_RDP 0x18000000
591#define ELS_CMD_RDF 0x19000000
592#define ELS_CMD_PRLI 0x20100014
593#define ELS_CMD_NVMEPRLI 0x20140018
594#define ELS_CMD_PRLO 0x21100014
595#define ELS_CMD_PRLO_ACC 0x02100014
596#define ELS_CMD_PDISC 0x50000000
597#define ELS_CMD_FDISC 0x51000000
598#define ELS_CMD_ADISC 0x52000000
599#define ELS_CMD_FARP 0x54000000
600#define ELS_CMD_FARPR 0x55000000
601#define ELS_CMD_RPL 0x57000000
602#define ELS_CMD_FAN 0x60000000
603#define ELS_CMD_RSCN 0x61040000
604#define ELS_CMD_RSCN_XMT 0x61040008
605#define ELS_CMD_SCR 0x62000000
606#define ELS_CMD_RNID 0x78000000
607#define ELS_CMD_LIRR 0x7A000000
608#define ELS_CMD_LCB 0x81000000
609#define ELS_CMD_FPIN 0x16000000
610#else
611#define ELS_CMD_MASK 0xffff
612#define ELS_RSP_MASK 0xff
613#define ELS_CMD_LS_RJT 0x01
614#define ELS_CMD_ACC 0x02
615#define ELS_CMD_PLOGI 0x03
616#define ELS_CMD_FLOGI 0x04
617#define ELS_CMD_LOGO 0x05
618#define ELS_CMD_ABTX 0x06
619#define ELS_CMD_RCS 0x07
620#define ELS_CMD_RES 0x08
621#define ELS_CMD_RSS 0x09
622#define ELS_CMD_RSI 0x0A
623#define ELS_CMD_ESTS 0x0B
624#define ELS_CMD_ESTC 0x0C
625#define ELS_CMD_ADVC 0x0D
626#define ELS_CMD_RTV 0x0E
627#define ELS_CMD_RLS 0x0F
628#define ELS_CMD_ECHO 0x10
629#define ELS_CMD_TEST 0x11
630#define ELS_CMD_RRQ 0x12
631#define ELS_CMD_REC 0x13
632#define ELS_CMD_RDP 0x18
633#define ELS_CMD_RDF 0x19
634#define ELS_CMD_PRLI 0x14001020
635#define ELS_CMD_NVMEPRLI 0x18001420
636#define ELS_CMD_PRLO 0x14001021
637#define ELS_CMD_PRLO_ACC 0x14001002
638#define ELS_CMD_PDISC 0x50
639#define ELS_CMD_FDISC 0x51
640#define ELS_CMD_ADISC 0x52
641#define ELS_CMD_FARP 0x54
642#define ELS_CMD_FARPR 0x55
643#define ELS_CMD_RPL 0x57
644#define ELS_CMD_FAN 0x60
645#define ELS_CMD_RSCN 0x0461
646#define ELS_CMD_RSCN_XMT 0x08000461
647#define ELS_CMD_SCR 0x62
648#define ELS_CMD_RNID 0x78
649#define ELS_CMD_LIRR 0x7A
650#define ELS_CMD_LCB 0x81
651#define ELS_CMD_FPIN ELS_FPIN
652#endif
653
654
655
656
657
658struct ls_rjt {
659 union {
660 uint32_t lsRjtError;
661 struct {
662 uint8_t lsRjtRsvd0;
663
664 uint8_t lsRjtRsnCode;
665
666#define LSRJT_INVALID_CMD 0x01
667#define LSRJT_LOGICAL_ERR 0x03
668#define LSRJT_LOGICAL_BSY 0x05
669#define LSRJT_PROTOCOL_ERR 0x07
670#define LSRJT_UNABLE_TPC 0x09
671#define LSRJT_CMD_UNSUPPORTED 0x0B
672#define LSRJT_VENDOR_UNIQUE 0xFF
673
674 uint8_t lsRjtRsnCodeExp;
675
676#define LSEXP_NOTHING_MORE 0x00
677#define LSEXP_SPARM_OPTIONS 0x01
678#define LSEXP_SPARM_ICTL 0x03
679#define LSEXP_SPARM_RCTL 0x05
680#define LSEXP_SPARM_RCV_SIZE 0x07
681#define LSEXP_SPARM_CONCUR_SEQ 0x09
682#define LSEXP_SPARM_CREDIT 0x0B
683#define LSEXP_INVALID_PNAME 0x0D
684#define LSEXP_INVALID_NNAME 0x0E
685#define LSEXP_INVALID_CSP 0x0F
686#define LSEXP_INVALID_ASSOC_HDR 0x11
687#define LSEXP_ASSOC_HDR_REQ 0x13
688#define LSEXP_INVALID_O_SID 0x15
689#define LSEXP_INVALID_OX_RX 0x17
690#define LSEXP_CMD_IN_PROGRESS 0x19
691#define LSEXP_PORT_LOGIN_REQ 0x1E
692#define LSEXP_INVALID_NPORT_ID 0x1F
693#define LSEXP_INVALID_SEQ_ID 0x21
694#define LSEXP_INVALID_XCHG 0x23
695#define LSEXP_INACTIVE_XCHG 0x25
696#define LSEXP_RQ_REQUIRED 0x27
697#define LSEXP_OUT_OF_RESOURCE 0x29
698#define LSEXP_CANT_GIVE_DATA 0x2A
699#define LSEXP_REQ_UNSUPPORTED 0x2C
700 uint8_t vendorUnique;
701 } b;
702 } un;
703};
704
705
706
707
708
709typedef struct _LOGO {
710 union {
711 uint32_t nPortId32;
712 struct {
713 uint8_t word1Reserved1;
714 uint8_t nPortIdByte0;
715 uint8_t nPortIdByte1;
716 uint8_t nPortIdByte2;
717 } b;
718 } un;
719 struct lpfc_name portName;
720} LOGO;
721
722
723
724
725
726#define PRLX_PAGE_LEN 0x10
727#define TPRLO_PAGE_LEN 0x14
728
729typedef struct _PRLI {
730 uint8_t prliType;
731
732#define PRLI_FCP_TYPE 0x08
733#define PRLI_NVME_TYPE 0x28
734 uint8_t word0Reserved1;
735
736#ifdef __BIG_ENDIAN_BITFIELD
737 uint8_t origProcAssocV:1;
738 uint8_t respProcAssocV:1;
739 uint8_t estabImagePair:1;
740
741
742 uint8_t word0Reserved2:1;
743 uint8_t acceptRspCode:4;
744#else
745 uint8_t acceptRspCode:4;
746 uint8_t word0Reserved2:1;
747 uint8_t estabImagePair:1;
748 uint8_t respProcAssocV:1;
749 uint8_t origProcAssocV:1;
750
751#endif
752
753#define PRLI_REQ_EXECUTED 0x1
754#define PRLI_NO_RESOURCES 0x2
755#define PRLI_INIT_INCOMPLETE 0x3
756#define PRLI_NO_SUCH_PA 0x4
757#define PRLI_PREDEF_CONFIG 0x5
758#define PRLI_PARTIAL_SUCCESS 0x6
759#define PRLI_INVALID_PAGE_CNT 0x7
760 uint8_t word0Reserved3;
761
762 uint32_t origProcAssoc;
763
764 uint32_t respProcAssoc;
765
766 uint8_t word3Reserved1;
767 uint8_t word3Reserved2;
768
769#ifdef __BIG_ENDIAN_BITFIELD
770 uint16_t Word3bit15Resved:1;
771 uint16_t Word3bit14Resved:1;
772 uint16_t Word3bit13Resved:1;
773 uint16_t Word3bit12Resved:1;
774 uint16_t Word3bit11Resved:1;
775 uint16_t Word3bit10Resved:1;
776 uint16_t TaskRetryIdReq:1;
777 uint16_t Retry:1;
778 uint16_t ConfmComplAllowed:1;
779 uint16_t dataOverLay:1;
780 uint16_t initiatorFunc:1;
781 uint16_t targetFunc:1;
782 uint16_t cmdDataMixEna:1;
783 uint16_t dataRspMixEna:1;
784 uint16_t readXferRdyDis:1;
785 uint16_t writeXferRdyDis:1;
786#else
787 uint16_t Retry:1;
788 uint16_t TaskRetryIdReq:1;
789 uint16_t Word3bit10Resved:1;
790 uint16_t Word3bit11Resved:1;
791 uint16_t Word3bit12Resved:1;
792 uint16_t Word3bit13Resved:1;
793 uint16_t Word3bit14Resved:1;
794 uint16_t Word3bit15Resved:1;
795 uint16_t writeXferRdyDis:1;
796 uint16_t readXferRdyDis:1;
797 uint16_t dataRspMixEna:1;
798 uint16_t cmdDataMixEna:1;
799 uint16_t targetFunc:1;
800 uint16_t initiatorFunc:1;
801 uint16_t dataOverLay:1;
802 uint16_t ConfmComplAllowed:1;
803#endif
804} PRLI;
805
806
807
808
809
810typedef struct _PRLO {
811 uint8_t prloType;
812
813#define PRLO_FCP_TYPE 0x08
814 uint8_t word0Reserved1;
815
816#ifdef __BIG_ENDIAN_BITFIELD
817 uint8_t origProcAssocV:1;
818 uint8_t respProcAssocV:1;
819 uint8_t word0Reserved2:2;
820 uint8_t acceptRspCode:4;
821#else
822 uint8_t acceptRspCode:4;
823 uint8_t word0Reserved2:2;
824 uint8_t respProcAssocV:1;
825 uint8_t origProcAssocV:1;
826#endif
827
828#define PRLO_REQ_EXECUTED 0x1
829#define PRLO_NO_SUCH_IMAGE 0x4
830#define PRLO_INVALID_PAGE_CNT 0x7
831
832 uint8_t word0Reserved3;
833
834 uint32_t origProcAssoc;
835
836 uint32_t respProcAssoc;
837
838 uint32_t word3Reserved1;
839} PRLO;
840
841typedef struct _ADISC {
842 uint32_t hardAL_PA;
843 struct lpfc_name portName;
844 struct lpfc_name nodeName;
845 uint32_t DID;
846} __packed ADISC;
847
848typedef struct _FARP {
849 uint32_t Mflags:8;
850 uint32_t Odid:24;
851#define FARP_NO_ACTION 0
852
853#define FARP_MATCH_PORT 0x1
854#define FARP_MATCH_NODE 0x2
855#define FARP_MATCH_IP 0x4
856#define FARP_MATCH_IPV4 0x5
857
858#define FARP_MATCH_IPV6 0x6
859
860 uint32_t Rflags:8;
861 uint32_t Rdid:24;
862#define FARP_REQUEST_PLOGI 0x1
863#define FARP_REQUEST_FARPR 0x2
864 struct lpfc_name OportName;
865 struct lpfc_name OnodeName;
866 struct lpfc_name RportName;
867 struct lpfc_name RnodeName;
868 uint8_t Oipaddr[16];
869 uint8_t Ripaddr[16];
870} FARP;
871
872typedef struct _FAN {
873 uint32_t Fdid;
874 struct lpfc_name FportName;
875 struct lpfc_name FnodeName;
876} __packed FAN;
877
878typedef struct _SCR {
879 uint8_t resvd1;
880 uint8_t resvd2;
881 uint8_t resvd3;
882 uint8_t Function;
883#define SCR_FUNC_FABRIC 0x01
884#define SCR_FUNC_NPORT 0x02
885#define SCR_FUNC_FULL 0x03
886#define SCR_CLEAR 0xff
887} SCR;
888
889typedef struct _RNID_TOP_DISC {
890 struct lpfc_name portName;
891 uint8_t resvd[8];
892 uint32_t unitType;
893#define RNID_HBA 0x7
894#define RNID_HOST 0xa
895#define RNID_DRIVER 0xd
896 uint32_t physPort;
897 uint32_t attachedNodes;
898 uint16_t ipVersion;
899#define RNID_IPV4 0x1
900#define RNID_IPV6 0x2
901 uint16_t UDPport;
902 uint8_t ipAddr[16];
903 uint16_t resvd1;
904 uint16_t flags;
905#define RNID_TD_SUPPORT 0x1
906#define RNID_LP_VALID 0x2
907} RNID_TOP_DISC;
908
909typedef struct _RNID {
910 uint8_t Format;
911#define RNID_TOPOLOGY_DISC 0xdf
912 uint8_t CommonLen;
913 uint8_t resvd1;
914 uint8_t SpecificLen;
915 struct lpfc_name portName;
916 struct lpfc_name nodeName;
917 union {
918 RNID_TOP_DISC topologyDisc;
919 } un;
920} __packed RNID;
921
922struct RLS {
923 uint32_t rls;
924#define rls_rsvd_SHIFT 24
925#define rls_rsvd_MASK 0x000000ff
926#define rls_rsvd_WORD rls
927#define rls_did_SHIFT 0
928#define rls_did_MASK 0x00ffffff
929#define rls_did_WORD rls
930};
931
932struct RLS_RSP {
933 uint32_t linkFailureCnt;
934 uint32_t lossSyncCnt;
935 uint32_t lossSignalCnt;
936 uint32_t primSeqErrCnt;
937 uint32_t invalidXmitWord;
938 uint32_t crcCnt;
939};
940
941struct RRQ {
942 uint32_t rrq;
943#define rrq_rsvd_SHIFT 24
944#define rrq_rsvd_MASK 0x000000ff
945#define rrq_rsvd_WORD rrq
946#define rrq_did_SHIFT 0
947#define rrq_did_MASK 0x00ffffff
948#define rrq_did_WORD rrq
949 uint32_t rrq_exchg;
950#define rrq_oxid_SHIFT 16
951#define rrq_oxid_MASK 0xffff
952#define rrq_oxid_WORD rrq_exchg
953#define rrq_rxid_SHIFT 0
954#define rrq_rxid_MASK 0xffff
955#define rrq_rxid_WORD rrq_exchg
956};
957
958#define LPFC_MAX_VFN_PER_PFN 255
959#define LPFC_DEF_VFN_PER_PFN 0
960
961struct RTV_RSP {
962 uint32_t ratov;
963 uint32_t edtov;
964 uint32_t qtov;
965#define qtov_rsvd0_SHIFT 28
966#define qtov_rsvd0_MASK 0x0000000f
967#define qtov_rsvd0_WORD qtov
968#define qtov_edtovres_SHIFT 27
969#define qtov_edtovres_MASK 0x00000001
970#define qtov_edtovres_WORD qtov
971#define qtov__rsvd1_SHIFT 19
972#define qtov_rsvd1_MASK 0x0000003f
973#define qtov_rsvd1_WORD qtov
974#define qtov_rttov_SHIFT 18
975#define qtov_rttov_MASK 0x00000001
976#define qtov_rttov_WORD qtov
977#define qtov_rsvd2_SHIFT 0
978#define qtov_rsvd2_MASK 0x0003ffff
979#define qtov_rsvd2_WORD qtov
980};
981
982
983typedef struct _RPL {
984 uint32_t maxsize;
985 uint32_t index;
986} RPL;
987
988typedef struct _PORT_NUM_BLK {
989 uint32_t portNum;
990 uint32_t portID;
991 struct lpfc_name portName;
992} PORT_NUM_BLK;
993
994typedef struct _RPL_RSP {
995 uint32_t listLen;
996 uint32_t index;
997 PORT_NUM_BLK port_num_blk;
998} RPL_RSP;
999
1000
1001typedef struct _D_ID {
1002 union {
1003 uint32_t word;
1004 struct {
1005#ifdef __BIG_ENDIAN_BITFIELD
1006 uint8_t resv;
1007 uint8_t domain;
1008 uint8_t area;
1009 uint8_t id;
1010#else
1011 uint8_t id;
1012 uint8_t area;
1013 uint8_t domain;
1014 uint8_t resv;
1015#endif
1016 } b;
1017 } un;
1018} D_ID;
1019
1020#define RSCN_ADDRESS_FORMAT_PORT 0x0
1021#define RSCN_ADDRESS_FORMAT_AREA 0x1
1022#define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
1023#define RSCN_ADDRESS_FORMAT_FABRIC 0x3
1024#define RSCN_ADDRESS_FORMAT_MASK 0x3
1025
1026
1027
1028
1029
1030typedef struct _ELS_PKT {
1031 uint8_t elsCode;
1032 uint8_t elsByte1;
1033 uint8_t elsByte2;
1034 uint8_t elsByte3;
1035 union {
1036 struct ls_rjt lsRjt;
1037 struct serv_parm logi;
1038 LOGO logo;
1039 PRLI prli;
1040 PRLO prlo;
1041 ADISC adisc;
1042 FARP farp;
1043 FAN fan;
1044 SCR scr;
1045 RNID rnid;
1046 uint8_t pad[128 - 4];
1047 } un;
1048} ELS_PKT;
1049
1050
1051
1052
1053
1054struct fc_lcb_request_frame {
1055 uint32_t lcb_command;
1056 uint8_t lcb_sub_command;
1057#define LPFC_LCB_ON 0x1
1058#define LPFC_LCB_OFF 0x2
1059 uint8_t reserved[2];
1060 uint8_t capability;
1061 uint8_t lcb_type;
1062#define LPFC_LCB_GREEN 0x1
1063#define LPFC_LCB_AMBER 0x2
1064 uint8_t lcb_frequency;
1065#define LCB_CAPABILITY_DURATION 1
1066#define BEACON_VERSION_V1 1
1067#define BEACON_VERSION_V0 0
1068 uint16_t lcb_duration;
1069};
1070
1071
1072
1073
1074struct fc_lcb_res_frame {
1075 uint32_t lcb_ls_acc;
1076 uint8_t lcb_sub_command;
1077 uint8_t reserved[2];
1078 uint8_t capability;
1079 uint8_t lcb_type;
1080 uint8_t lcb_frequency;
1081 uint16_t lcb_duration;
1082};
1083
1084
1085
1086
1087#define SFF_PG0_IDENT_SFP 0x3
1088
1089#define SFP_FLAG_PT_OPTICAL 0x0
1090#define SFP_FLAG_PT_SWLASER 0x01
1091#define SFP_FLAG_PT_LWLASER_LC1310 0x02
1092#define SFP_FLAG_PT_LWLASER_LL1550 0x03
1093#define SFP_FLAG_PT_MASK 0x0F
1094#define SFP_FLAG_PT_SHIFT 0
1095
1096#define SFP_FLAG_IS_OPTICAL_PORT 0x01
1097#define SFP_FLAG_IS_OPTICAL_MASK 0x010
1098#define SFP_FLAG_IS_OPTICAL_SHIFT 4
1099
1100#define SFP_FLAG_IS_DESC_VALID 0x01
1101#define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1102#define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1103
1104#define SFP_FLAG_CT_UNKNOWN 0x0
1105#define SFP_FLAG_CT_SFP_PLUS 0x01
1106#define SFP_FLAG_CT_MASK 0x3C
1107#define SFP_FLAG_CT_SHIFT 6
1108
1109struct fc_rdp_port_name_info {
1110 uint8_t wwnn[8];
1111 uint8_t wwpn[8];
1112};
1113
1114
1115
1116
1117
1118
1119struct fc_link_status {
1120 uint32_t link_failure_cnt;
1121 uint32_t loss_of_synch_cnt;
1122 uint32_t loss_of_signal_cnt;
1123 uint32_t primitive_seq_proto_err;
1124 uint32_t invalid_trans_word;
1125 uint32_t invalid_crc_cnt;
1126
1127};
1128
1129#define RDP_PORT_NAMES_DESC_TAG 0x00010003
1130struct fc_rdp_port_name_desc {
1131 uint32_t tag;
1132 uint32_t length;
1133 struct fc_rdp_port_name_info port_names;
1134};
1135
1136
1137struct fc_rdp_fec_info {
1138 uint32_t CorrectedBlocks;
1139 uint32_t UncorrectableBlocks;
1140};
1141
1142#define RDP_FEC_DESC_TAG 0x00010005
1143struct fc_fec_rdp_desc {
1144 uint32_t tag;
1145 uint32_t length;
1146 struct fc_rdp_fec_info info;
1147};
1148
1149struct fc_rdp_link_error_status_payload_info {
1150 struct fc_link_status link_status;
1151 uint32_t port_type;
1152};
1153
1154#define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1155struct fc_rdp_link_error_status_desc {
1156 uint32_t tag;
1157 uint32_t length;
1158 struct fc_rdp_link_error_status_payload_info info;
1159};
1160
1161#define VN_PT_PHY_UNKNOWN 0x00
1162#define VN_PT_PHY_PF_PORT 0x01
1163#define VN_PT_PHY_ETH_MAC 0x10
1164#define VN_PT_PHY_SHIFT 30
1165
1166#define RDP_PS_1GB 0x8000
1167#define RDP_PS_2GB 0x4000
1168#define RDP_PS_4GB 0x2000
1169#define RDP_PS_10GB 0x1000
1170#define RDP_PS_8GB 0x0800
1171#define RDP_PS_16GB 0x0400
1172#define RDP_PS_32GB 0x0200
1173#define RDP_PS_64GB 0x0100
1174#define RDP_PS_128GB 0x0080
1175#define RDP_PS_256GB 0x0040
1176
1177#define RDP_CAP_USER_CONFIGURED 0x0002
1178#define RDP_CAP_UNKNOWN 0x0001
1179#define RDP_PS_UNKNOWN 0x0002
1180#define RDP_PS_NOT_ESTABLISHED 0x0001
1181
1182struct fc_rdp_port_speed {
1183 uint16_t capabilities;
1184 uint16_t speed;
1185};
1186
1187struct fc_rdp_port_speed_info {
1188 struct fc_rdp_port_speed port_speed;
1189};
1190
1191#define RDP_PORT_SPEED_DESC_TAG 0x00010001
1192struct fc_rdp_port_speed_desc {
1193 uint32_t tag;
1194 uint32_t length;
1195 struct fc_rdp_port_speed_info info;
1196};
1197
1198#define RDP_NPORT_ID_SIZE 4
1199#define RDP_N_PORT_DESC_TAG 0x00000003
1200struct fc_rdp_nport_desc {
1201 uint32_t tag;
1202 uint32_t length;
1203 uint32_t nport_id : 12;
1204 uint32_t reserved : 8;
1205};
1206
1207
1208struct fc_rdp_link_service_info {
1209 uint32_t els_req;
1210};
1211
1212#define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1213struct fc_rdp_link_service_desc {
1214 uint32_t tag;
1215 uint32_t length;
1216 struct fc_rdp_link_service_info payload;
1217
1218};
1219
1220struct fc_rdp_sfp_info {
1221 uint16_t temperature;
1222 uint16_t vcc;
1223 uint16_t tx_bias;
1224 uint16_t tx_power;
1225 uint16_t rx_power;
1226 uint16_t flags;
1227};
1228
1229#define RDP_SFP_DESC_TAG 0x00010000
1230struct fc_rdp_sfp_desc {
1231 uint32_t tag;
1232 uint32_t length;
1233 struct fc_rdp_sfp_info sfp_info;
1234};
1235
1236
1237struct fc_rdp_bbc_info {
1238 uint32_t port_bbc;
1239 uint32_t attached_port_bbc;
1240 uint32_t rtt;
1241};
1242#define RDP_BBC_DESC_TAG 0x00010006
1243struct fc_rdp_bbc_desc {
1244 uint32_t tag;
1245 uint32_t length;
1246 struct fc_rdp_bbc_info bbc_info;
1247};
1248
1249
1250#define RDP_OET_LOW_WARNING 0x1
1251#define RDP_OET_HIGH_WARNING 0x2
1252#define RDP_OET_LOW_ALARM 0x4
1253#define RDP_OET_HIGH_ALARM 0x8
1254
1255#define RDP_OED_TEMPERATURE 0x1
1256#define RDP_OED_VOLTAGE 0x2
1257#define RDP_OED_TXBIAS 0x3
1258#define RDP_OED_TXPOWER 0x4
1259#define RDP_OED_RXPOWER 0x5
1260
1261#define RDP_OED_TYPE_SHIFT 28
1262
1263struct fc_rdp_oed_info {
1264 uint16_t hi_alarm;
1265 uint16_t lo_alarm;
1266 uint16_t hi_warning;
1267 uint16_t lo_warning;
1268 uint32_t function_flags;
1269};
1270#define RDP_OED_DESC_TAG 0x00010007
1271struct fc_rdp_oed_sfp_desc {
1272 uint32_t tag;
1273 uint32_t length;
1274 struct fc_rdp_oed_info oed_info;
1275};
1276
1277
1278struct fc_rdp_opd_sfp_info {
1279 uint8_t vendor_name[16];
1280 uint8_t model_number[16];
1281 uint8_t serial_number[16];
1282 uint8_t revision[4];
1283 uint8_t date[8];
1284};
1285
1286#define RDP_OPD_DESC_TAG 0x00010008
1287struct fc_rdp_opd_sfp_desc {
1288 uint32_t tag;
1289 uint32_t length;
1290 struct fc_rdp_opd_sfp_info opd_info;
1291};
1292
1293struct fc_rdp_req_frame {
1294 uint32_t rdp_command;
1295 uint32_t rdp_des_length;
1296 struct fc_rdp_nport_desc nport_id_desc;
1297};
1298
1299
1300struct fc_rdp_res_frame {
1301 uint32_t reply_sequence;
1302 uint32_t length;
1303 struct fc_rdp_link_service_desc link_service_desc;
1304 struct fc_rdp_sfp_desc sfp_desc;
1305 struct fc_rdp_port_speed_desc portspeed_desc;
1306 struct fc_rdp_link_error_status_desc link_error_desc;
1307 struct fc_rdp_port_name_desc diag_port_names_desc;
1308 struct fc_rdp_port_name_desc attached_port_names_desc;
1309 struct fc_fec_rdp_desc fec_desc;
1310 struct fc_rdp_bbc_desc bbc_desc;
1311 struct fc_rdp_oed_sfp_desc oed_temp_desc;
1312 struct fc_rdp_oed_sfp_desc oed_voltage_desc;
1313 struct fc_rdp_oed_sfp_desc oed_txbias_desc;
1314 struct fc_rdp_oed_sfp_desc oed_txpower_desc;
1315 struct fc_rdp_oed_sfp_desc oed_rxpower_desc;
1316 struct fc_rdp_opd_sfp_desc opd_desc;
1317};
1318
1319
1320
1321
1322
1323#define SLI_CT_FDMI_Subtypes 0x10
1324
1325
1326
1327
1328struct lpfc_fdmi_attr_entry {
1329 union {
1330 uint32_t AttrInt;
1331 uint8_t AttrTypes[32];
1332 uint8_t AttrString[256];
1333 struct lpfc_name AttrWWN;
1334 } un;
1335};
1336
1337struct lpfc_fdmi_attr_def {
1338
1339 uint32_t AttrType:16;
1340 uint32_t AttrLen:16;
1341
1342 struct lpfc_fdmi_attr_entry AttrValue;
1343} __packed;
1344
1345
1346
1347
1348struct lpfc_fdmi_attr_block {
1349 uint32_t EntryCnt;
1350 struct lpfc_fdmi_attr_entry Entry;
1351};
1352
1353
1354
1355
1356struct lpfc_fdmi_port_entry {
1357 struct lpfc_name PortName;
1358};
1359
1360
1361
1362
1363struct lpfc_fdmi_hba_ident {
1364 struct lpfc_name PortName;
1365};
1366
1367
1368
1369
1370struct lpfc_fdmi_reg_port_list {
1371 uint32_t EntryCnt;
1372 struct lpfc_fdmi_port_entry pe;
1373} __packed;
1374
1375
1376
1377
1378struct lpfc_fdmi_reg_hba {
1379 struct lpfc_fdmi_hba_ident hi;
1380 struct lpfc_fdmi_reg_port_list rpl;
1381};
1382
1383
1384#define SLI_CT_MIB_Subtypes 0x11
1385
1386
1387
1388
1389struct lpfc_fdmi_reg_hbaattr {
1390 struct lpfc_name HBA_PortName;
1391 struct lpfc_fdmi_attr_block ab;
1392};
1393
1394
1395
1396
1397struct lpfc_fdmi_reg_portattr {
1398 struct lpfc_name PortName;
1399 struct lpfc_fdmi_attr_block ab;
1400};
1401
1402
1403
1404
1405#define SLI_MGMT_GRHL 0x100
1406#define SLI_MGMT_GHAT 0x101
1407#define SLI_MGMT_GRPL 0x102
1408#define SLI_MGMT_GPAT 0x110
1409#define SLI_MGMT_GPAS 0x120
1410#define SLI_MGMT_RHBA 0x200
1411#define SLI_MGMT_RHAT 0x201
1412#define SLI_MGMT_RPRT 0x210
1413#define SLI_MGMT_RPA 0x211
1414#define SLI_MGMT_DHBA 0x300
1415#define SLI_MGMT_DHAT 0x301
1416#define SLI_MGMT_DPRT 0x310
1417#define SLI_MGMT_DPA 0x311
1418
1419#define LPFC_FDMI_MAX_RETRY 3
1420
1421
1422
1423
1424#define RHBA_NODENAME 0x1
1425#define RHBA_MANUFACTURER 0x2
1426#define RHBA_SERIAL_NUMBER 0x3
1427#define RHBA_MODEL 0x4
1428#define RHBA_MODEL_DESCRIPTION 0x5
1429#define RHBA_HARDWARE_VERSION 0x6
1430#define RHBA_DRIVER_VERSION 0x7
1431#define RHBA_OPTION_ROM_VERSION 0x8
1432#define RHBA_FIRMWARE_VERSION 0x9
1433#define RHBA_OS_NAME_VERSION 0xa
1434#define RHBA_MAX_CT_PAYLOAD_LEN 0xb
1435#define RHBA_SYM_NODENAME 0xc
1436#define RHBA_VENDOR_INFO 0xd
1437#define RHBA_NUM_PORTS 0xe
1438#define RHBA_FABRIC_WWNN 0xf
1439#define RHBA_BIOS_VERSION 0x10
1440#define RHBA_BIOS_STATE 0x11
1441#define RHBA_VENDOR_ID 0xe0
1442
1443
1444#define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1445#define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1446#define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1447#define LPFC_FDMI_HBA_ATTR_model 0x00000008
1448#define LPFC_FDMI_HBA_ATTR_description 0x00000010
1449#define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1450#define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1451#define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1452#define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1453#define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1454#define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1455#define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1456#define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000
1457#define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1458#define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1459#define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1460#define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000
1461#define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1462
1463
1464#define LPFC_FDMI1_HBA_ATTR 0x000007ff
1465
1466
1467
1468#define LPFC_FDMI2_HBA_ATTR 0x0002efff
1469
1470
1471
1472
1473#define RPRT_SUPPORTED_FC4_TYPES 0x1
1474#define RPRT_SUPPORTED_SPEED 0x2
1475#define RPRT_PORT_SPEED 0x3
1476#define RPRT_MAX_FRAME_SIZE 0x4
1477#define RPRT_OS_DEVICE_NAME 0x5
1478#define RPRT_HOST_NAME 0x6
1479#define RPRT_NODENAME 0x7
1480#define RPRT_PORTNAME 0x8
1481#define RPRT_SYM_PORTNAME 0x9
1482#define RPRT_PORT_TYPE 0xa
1483#define RPRT_SUPPORTED_CLASS 0xb
1484#define RPRT_FABRICNAME 0xc
1485#define RPRT_ACTIVE_FC4_TYPES 0xd
1486#define RPRT_PORT_STATE 0x101
1487#define RPRT_DISC_PORT 0x102
1488#define RPRT_PORT_ID 0x103
1489#define RPRT_VENDOR_MI 0xf047
1490#define RPRT_SMART_SERVICE 0xf100
1491#define RPRT_SMART_GUID 0xf101
1492#define RPRT_SMART_VERSION 0xf102
1493#define RPRT_SMART_MODEL 0xf103
1494#define RPRT_SMART_PORT_INFO 0xf104
1495#define RPRT_SMART_QOS 0xf105
1496#define RPRT_SMART_SECURITY 0xf106
1497
1498
1499#define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1500#define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1501#define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1502#define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1503#define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1504#define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1505#define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1506#define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1507#define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1508#define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1509#define LPFC_FDMI_PORT_ATTR_class 0x00000400
1510#define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1511#define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1512#define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1513#define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1514#define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1515#define LPFC_FDMI_SMART_ATTR_service 0x00010000
1516#define LPFC_FDMI_SMART_ATTR_guid 0x00020000
1517#define LPFC_FDMI_SMART_ATTR_version 0x00040000
1518#define LPFC_FDMI_SMART_ATTR_model 0x00080000
1519#define LPFC_FDMI_SMART_ATTR_port_info 0x00100000
1520#define LPFC_FDMI_SMART_ATTR_qos 0x00200000
1521#define LPFC_FDMI_SMART_ATTR_security 0x00400000
1522#define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000
1523
1524
1525#define LPFC_FDMI1_PORT_ATTR 0x0000003f
1526
1527
1528#define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1529
1530
1531#define LPFC_FDMI2_SMART_ATTR 0x007fffff
1532
1533
1534#define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1535#define LPFC_FDMI_PORTSTATE_ONLINE 2
1536
1537
1538#define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1539#define LPFC_FDMI_PORTTYPE_NPORT 1
1540#define LPFC_FDMI_PORTTYPE_NLPORT 2
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554#define MAX_SLI3_CONFIGURED_RINGS 3
1555#define MAX_SLI3_RINGS 4
1556
1557
1558#define OWN_CHIP 1
1559
1560
1561#define OWN_HOST 0
1562
1563
1564#define IOCB_WORD_SZ 8
1565
1566
1567#define FC_NET_HDR 0x20
1568
1569
1570#define PCI_VENDOR_ID_EMULEX 0x10df
1571#define PCI_DEVICE_ID_FIREFLY 0x1ae5
1572#define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1573#define PCI_DEVICE_ID_BALIUS 0xe131
1574#define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1575#define PCI_DEVICE_ID_LANCER_FC 0xe200
1576#define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1577#define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1578#define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1579#define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1580#define PCI_DEVICE_ID_LANCER_G7_FC 0xf400
1581#define PCI_DEVICE_ID_SAT_SMB 0xf011
1582#define PCI_DEVICE_ID_SAT_MID 0xf015
1583#define PCI_DEVICE_ID_RFLY 0xf095
1584#define PCI_DEVICE_ID_PFLY 0xf098
1585#define PCI_DEVICE_ID_LP101 0xf0a1
1586#define PCI_DEVICE_ID_TFLY 0xf0a5
1587#define PCI_DEVICE_ID_BSMB 0xf0d1
1588#define PCI_DEVICE_ID_BMID 0xf0d5
1589#define PCI_DEVICE_ID_ZSMB 0xf0e1
1590#define PCI_DEVICE_ID_ZMID 0xf0e5
1591#define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1592#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1593#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1594#define PCI_DEVICE_ID_SAT 0xf100
1595#define PCI_DEVICE_ID_SAT_SCSP 0xf111
1596#define PCI_DEVICE_ID_SAT_DCSP 0xf112
1597#define PCI_DEVICE_ID_FALCON 0xf180
1598#define PCI_DEVICE_ID_SUPERFLY 0xf700
1599#define PCI_DEVICE_ID_DRAGONFLY 0xf800
1600#define PCI_DEVICE_ID_CENTAUR 0xf900
1601#define PCI_DEVICE_ID_PEGASUS 0xf980
1602#define PCI_DEVICE_ID_THOR 0xfa00
1603#define PCI_DEVICE_ID_VIPER 0xfb00
1604#define PCI_DEVICE_ID_LP10000S 0xfc00
1605#define PCI_DEVICE_ID_LP11000S 0xfc10
1606#define PCI_DEVICE_ID_LPE11000S 0xfc20
1607#define PCI_DEVICE_ID_SAT_S 0xfc40
1608#define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1609#define PCI_DEVICE_ID_HELIOS 0xfd00
1610#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1611#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1612#define PCI_DEVICE_ID_ZEPHYR 0xfe00
1613#define PCI_DEVICE_ID_HORNET 0xfe05
1614#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1615#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1616#define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1617#define PCI_DEVICE_ID_TIGERSHARK 0x0704
1618#define PCI_DEVICE_ID_TOMCAT 0x0714
1619#define PCI_DEVICE_ID_SKYHAWK 0x0724
1620#define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1621
1622#define JEDEC_ID_ADDRESS 0x0080001c
1623#define FIREFLY_JEDEC_ID 0x1ACC
1624#define SUPERFLY_JEDEC_ID 0x0020
1625#define DRAGONFLY_JEDEC_ID 0x0021
1626#define DRAGONFLY_V2_JEDEC_ID 0x0025
1627#define CENTAUR_2G_JEDEC_ID 0x0026
1628#define CENTAUR_1G_JEDEC_ID 0x0028
1629#define PEGASUS_ORION_JEDEC_ID 0x0036
1630#define PEGASUS_JEDEC_ID 0x0038
1631#define THOR_JEDEC_ID 0x0012
1632#define HELIOS_JEDEC_ID 0x0364
1633#define ZEPHYR_JEDEC_ID 0x0577
1634#define VIPER_JEDEC_ID 0x4838
1635#define SATURN_JEDEC_ID 0x1004
1636#define HORNET_JDEC_ID 0x2057706D
1637
1638#define JEDEC_ID_MASK 0x0FFFF000
1639#define JEDEC_ID_SHIFT 12
1640#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1641
1642typedef struct {
1643 uint32_t hostAtt;
1644
1645 uint32_t chipAtt;
1646
1647 uint32_t hostStatus;
1648 uint32_t hostControl;
1649 uint32_t buiConfig;
1650
1651} FF_REGS;
1652
1653
1654#define FF_REG_AREA_SIZE 256
1655
1656
1657
1658#define HA_REG_OFFSET 0
1659
1660#define HA_R0RE_REQ 0x00000001
1661#define HA_R0CE_RSP 0x00000002
1662#define HA_R0ATT 0x00000008
1663#define HA_R1RE_REQ 0x00000010
1664#define HA_R1CE_RSP 0x00000020
1665#define HA_R1ATT 0x00000080
1666#define HA_R2RE_REQ 0x00000100
1667#define HA_R2CE_RSP 0x00000200
1668#define HA_R2ATT 0x00000800
1669#define HA_R3RE_REQ 0x00001000
1670#define HA_R3CE_RSP 0x00002000
1671#define HA_R3ATT 0x00008000
1672#define HA_LATT 0x20000000
1673#define HA_MBATT 0x40000000
1674#define HA_ERATT 0x80000000
1675
1676#define HA_RXRE_REQ 0x00000001
1677#define HA_RXCE_RSP 0x00000002
1678#define HA_RXATT 0x00000008
1679#define HA_RXMASK 0x0000000f
1680
1681#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1682#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1683#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1684#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1685
1686#define HA_R0_POS 3
1687#define HA_R1_POS 7
1688#define HA_R2_POS 11
1689#define HA_R3_POS 15
1690#define HA_LE_POS 29
1691#define HA_MB_POS 30
1692#define HA_ER_POS 31
1693
1694
1695#define CA_REG_OFFSET 4
1696
1697#define CA_R0CE_REQ 0x00000001
1698#define CA_R0RE_RSP 0x00000002
1699#define CA_R0ATT 0x00000008
1700#define CA_R1CE_REQ 0x00000010
1701#define CA_R1RE_RSP 0x00000020
1702#define CA_R1ATT 0x00000080
1703#define CA_R2CE_REQ 0x00000100
1704#define CA_R2RE_RSP 0x00000200
1705#define CA_R2ATT 0x00000800
1706#define CA_R3CE_REQ 0x00001000
1707#define CA_R3RE_RSP 0x00002000
1708#define CA_R3ATT 0x00008000
1709#define CA_MBATT 0x40000000
1710
1711
1712
1713#define HS_REG_OFFSET 8
1714
1715#define HS_MBRDY 0x00400000
1716#define HS_FFRDY 0x00800000
1717#define HS_FFER8 0x01000000
1718#define HS_FFER7 0x02000000
1719#define HS_FFER6 0x04000000
1720#define HS_FFER5 0x08000000
1721#define HS_FFER4 0x10000000
1722#define HS_FFER3 0x20000000
1723#define HS_FFER2 0x40000000
1724#define HS_FFER1 0x80000000
1725#define HS_CRIT_TEMP 0x00000100
1726#define HS_FFERM 0xFF000100
1727#define UNPLUG_ERR 0x00000001
1728
1729
1730#define HC_REG_OFFSET 12
1731
1732#define HC_MBINT_ENA 0x00000001
1733#define HC_R0INT_ENA 0x00000002
1734#define HC_R1INT_ENA 0x00000004
1735#define HC_R2INT_ENA 0x00000008
1736#define HC_R3INT_ENA 0x00000010
1737#define HC_INITHBI 0x02000000
1738#define HC_INITMB 0x04000000
1739#define HC_INITFF 0x08000000
1740#define HC_LAINT_ENA 0x20000000
1741#define HC_ERINT_ENA 0x80000000
1742
1743
1744#define MSIX_DFLT_ID 0
1745#define MSIX_RNG0_ID 0
1746#define MSIX_RNG1_ID 1
1747#define MSIX_RNG2_ID 2
1748#define MSIX_RNG3_ID 3
1749
1750#define MSIX_LINK_ID 4
1751#define MSIX_MBOX_ID 5
1752
1753#define MSIX_SPARE0_ID 6
1754#define MSIX_SPARE1_ID 7
1755
1756
1757#define MBX_SHUTDOWN 0x00
1758#define MBX_LOAD_SM 0x01
1759#define MBX_READ_NV 0x02
1760#define MBX_WRITE_NV 0x03
1761#define MBX_RUN_BIU_DIAG 0x04
1762#define MBX_INIT_LINK 0x05
1763#define MBX_DOWN_LINK 0x06
1764#define MBX_CONFIG_LINK 0x07
1765#define MBX_CONFIG_RING 0x09
1766#define MBX_RESET_RING 0x0A
1767#define MBX_READ_CONFIG 0x0B
1768#define MBX_READ_RCONFIG 0x0C
1769#define MBX_READ_SPARM 0x0D
1770#define MBX_READ_STATUS 0x0E
1771#define MBX_READ_RPI 0x0F
1772#define MBX_READ_XRI 0x10
1773#define MBX_READ_REV 0x11
1774#define MBX_READ_LNK_STAT 0x12
1775#define MBX_REG_LOGIN 0x13
1776#define MBX_UNREG_LOGIN 0x14
1777#define MBX_CLEAR_LA 0x16
1778#define MBX_DUMP_MEMORY 0x17
1779#define MBX_DUMP_CONTEXT 0x18
1780#define MBX_RUN_DIAGS 0x19
1781#define MBX_RESTART 0x1A
1782#define MBX_UPDATE_CFG 0x1B
1783#define MBX_DOWN_LOAD 0x1C
1784#define MBX_DEL_LD_ENTRY 0x1D
1785#define MBX_RUN_PROGRAM 0x1E
1786#define MBX_SET_MASK 0x20
1787#define MBX_SET_VARIABLE 0x21
1788#define MBX_UNREG_D_ID 0x23
1789#define MBX_KILL_BOARD 0x24
1790#define MBX_CONFIG_FARP 0x25
1791#define MBX_BEACON 0x2A
1792#define MBX_CONFIG_MSI 0x30
1793#define MBX_HEARTBEAT 0x31
1794#define MBX_WRITE_VPARMS 0x32
1795#define MBX_ASYNCEVT_ENABLE 0x33
1796#define MBX_READ_EVENT_LOG_STATUS 0x37
1797#define MBX_READ_EVENT_LOG 0x38
1798#define MBX_WRITE_EVENT_LOG 0x39
1799
1800#define MBX_PORT_CAPABILITIES 0x3B
1801#define MBX_PORT_IOV_CONTROL 0x3C
1802
1803#define MBX_CONFIG_HBQ 0x7C
1804#define MBX_LOAD_AREA 0x81
1805#define MBX_RUN_BIU_DIAG64 0x84
1806#define MBX_CONFIG_PORT 0x88
1807#define MBX_READ_SPARM64 0x8D
1808#define MBX_READ_RPI64 0x8F
1809#define MBX_REG_LOGIN64 0x93
1810#define MBX_READ_TOPOLOGY 0x95
1811#define MBX_REG_VPI 0x96
1812#define MBX_UNREG_VPI 0x97
1813
1814#define MBX_WRITE_WWN 0x98
1815#define MBX_SET_DEBUG 0x99
1816#define MBX_LOAD_EXP_ROM 0x9C
1817#define MBX_SLI4_CONFIG 0x9B
1818#define MBX_SLI4_REQ_FTRS 0x9D
1819#define MBX_MAX_CMDS 0x9E
1820#define MBX_RESUME_RPI 0x9E
1821#define MBX_SLI2_CMD_MASK 0x80
1822#define MBX_REG_VFI 0x9F
1823#define MBX_REG_FCFI 0xA0
1824#define MBX_UNREG_VFI 0xA1
1825#define MBX_UNREG_FCFI 0xA2
1826#define MBX_INIT_VFI 0xA3
1827#define MBX_INIT_VPI 0xA4
1828#define MBX_ACCESS_VDATA 0xA5
1829#define MBX_REG_FCFI_MRQ 0xAF
1830
1831#define MBX_AUTH_PORT 0xF8
1832#define MBX_SECURITY_MGMT 0xF9
1833
1834
1835
1836#define CMD_RCV_SEQUENCE_CX 0x01
1837#define CMD_XMIT_SEQUENCE_CR 0x02
1838#define CMD_XMIT_SEQUENCE_CX 0x03
1839#define CMD_XMIT_BCAST_CN 0x04
1840#define CMD_XMIT_BCAST_CX 0x05
1841#define CMD_QUE_RING_BUF_CN 0x06
1842#define CMD_QUE_XRI_BUF_CX 0x07
1843#define CMD_IOCB_CONTINUE_CN 0x08
1844#define CMD_RET_XRI_BUF_CX 0x09
1845#define CMD_ELS_REQUEST_CR 0x0A
1846#define CMD_ELS_REQUEST_CX 0x0B
1847#define CMD_RCV_ELS_REQ_CX 0x0D
1848#define CMD_ABORT_XRI_CN 0x0E
1849#define CMD_ABORT_XRI_CX 0x0F
1850#define CMD_CLOSE_XRI_CN 0x10
1851#define CMD_CLOSE_XRI_CX 0x11
1852#define CMD_CREATE_XRI_CR 0x12
1853#define CMD_CREATE_XRI_CX 0x13
1854#define CMD_GET_RPI_CN 0x14
1855#define CMD_XMIT_ELS_RSP_CX 0x15
1856#define CMD_GET_RPI_CR 0x16
1857#define CMD_XRI_ABORTED_CX 0x17
1858#define CMD_FCP_IWRITE_CR 0x18
1859#define CMD_FCP_IWRITE_CX 0x19
1860#define CMD_FCP_IREAD_CR 0x1A
1861#define CMD_FCP_IREAD_CX 0x1B
1862#define CMD_FCP_ICMND_CR 0x1C
1863#define CMD_FCP_ICMND_CX 0x1D
1864#define CMD_FCP_TSEND_CX 0x1F
1865#define CMD_FCP_TRECEIVE_CX 0x21
1866#define CMD_FCP_TRSP_CX 0x23
1867#define CMD_FCP_AUTO_TRSP_CX 0x29
1868
1869#define CMD_ADAPTER_MSG 0x20
1870#define CMD_ADAPTER_DUMP 0x22
1871
1872
1873
1874#define CMD_ASYNC_STATUS 0x7C
1875#define CMD_RCV_SEQUENCE64_CX 0x81
1876#define CMD_XMIT_SEQUENCE64_CR 0x82
1877#define CMD_XMIT_SEQUENCE64_CX 0x83
1878#define CMD_XMIT_BCAST64_CN 0x84
1879#define CMD_XMIT_BCAST64_CX 0x85
1880#define CMD_QUE_RING_BUF64_CN 0x86
1881#define CMD_QUE_XRI_BUF64_CX 0x87
1882#define CMD_IOCB_CONTINUE64_CN 0x88
1883#define CMD_RET_XRI_BUF64_CX 0x89
1884#define CMD_ELS_REQUEST64_CR 0x8A
1885#define CMD_ELS_REQUEST64_CX 0x8B
1886#define CMD_ABORT_MXRI64_CN 0x8C
1887#define CMD_RCV_ELS_REQ64_CX 0x8D
1888#define CMD_XMIT_ELS_RSP64_CX 0x95
1889#define CMD_XMIT_BLS_RSP64_CX 0x97
1890#define CMD_FCP_IWRITE64_CR 0x98
1891#define CMD_FCP_IWRITE64_CX 0x99
1892#define CMD_FCP_IREAD64_CR 0x9A
1893#define CMD_FCP_IREAD64_CX 0x9B
1894#define CMD_FCP_ICMND64_CR 0x9C
1895#define CMD_FCP_ICMND64_CX 0x9D
1896#define CMD_FCP_TSEND64_CX 0x9F
1897#define CMD_FCP_TRECEIVE64_CX 0xA1
1898#define CMD_FCP_TRSP64_CX 0xA3
1899
1900#define CMD_QUE_XRI64_CX 0xB3
1901#define CMD_IOCB_RCV_SEQ64_CX 0xB5
1902#define CMD_IOCB_RCV_ELS64_CX 0xB7
1903#define CMD_IOCB_RET_XRI64_CX 0xB9
1904#define CMD_IOCB_RCV_CONT64_CX 0xBB
1905
1906#define CMD_GEN_REQUEST64_CR 0xC2
1907#define CMD_GEN_REQUEST64_CX 0xC3
1908
1909
1910#define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1911#define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1912#define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1913#define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1914#define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1915#define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1916#define CMD_IOCB_RET_HBQE64_CN 0xCA
1917#define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1918#define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1919#define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1920#define CMD_IOCB_LOGENTRY_CN 0x94
1921#define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1922
1923
1924#define DSSCMD_IWRITE64_CR 0xF8
1925#define DSSCMD_IWRITE64_CX 0xF9
1926#define DSSCMD_IREAD64_CR 0xFA
1927#define DSSCMD_IREAD64_CX 0xFB
1928
1929#define CMD_MAX_IOCB_CMD 0xFB
1930#define CMD_IOCB_MASK 0xff
1931
1932#define MAX_MSG_DATA 28
1933
1934#define LPFC_MAX_ADPTMSG 32
1935
1936
1937
1938#define MBX_SUCCESS 0
1939#define MBXERR_NUM_RINGS 1
1940#define MBXERR_NUM_IOCBS 2
1941#define MBXERR_IOCBS_EXCEEDED 3
1942#define MBXERR_BAD_RING_NUMBER 4
1943#define MBXERR_MASK_ENTRIES_RANGE 5
1944#define MBXERR_MASKS_EXCEEDED 6
1945#define MBXERR_BAD_PROFILE 7
1946#define MBXERR_BAD_DEF_CLASS 8
1947#define MBXERR_BAD_MAX_RESPONDER 9
1948#define MBXERR_BAD_MAX_ORIGINATOR 10
1949#define MBXERR_RPI_REGISTERED 11
1950#define MBXERR_RPI_FULL 12
1951#define MBXERR_NO_RESOURCES 13
1952#define MBXERR_BAD_RCV_LENGTH 14
1953#define MBXERR_DMA_ERROR 15
1954#define MBXERR_ERROR 16
1955#define MBXERR_LINK_DOWN 0x33
1956#define MBXERR_SEC_NO_PERMISSION 0xF02
1957#define MBX_NOT_FINISHED 255
1958
1959#define MBX_BUSY 0xffffff
1960#define MBX_TIMEOUT 0xfffffe
1961
1962#define TEMPERATURE_OFFSET 0xB0
1963
1964
1965
1966
1967#define FAILURE 1
1968
1969
1970
1971
1972
1973typedef struct {
1974#ifdef __BIG_ENDIAN_BITFIELD
1975 uint8_t tval;
1976 uint8_t tmask;
1977 uint8_t rval;
1978 uint8_t rmask;
1979#else
1980 uint8_t rmask;
1981 uint8_t rval;
1982 uint8_t tmask;
1983 uint8_t tval;
1984#endif
1985} RR_REG;
1986
1987struct ulp_bde {
1988 uint32_t bdeAddress;
1989#ifdef __BIG_ENDIAN_BITFIELD
1990 uint32_t bdeReserved:4;
1991 uint32_t bdeAddrHigh:4;
1992 uint32_t bdeSize:24;
1993#else
1994 uint32_t bdeSize:24;
1995 uint32_t bdeAddrHigh:4;
1996 uint32_t bdeReserved:4;
1997#endif
1998};
1999
2000typedef struct ULP_BDL {
2001#ifdef __BIG_ENDIAN_BITFIELD
2002 uint32_t bdeFlags:8;
2003 uint32_t bdeSize:24;
2004#else
2005 uint32_t bdeSize:24;
2006 uint32_t bdeFlags:8;
2007#endif
2008
2009 uint32_t addrLow;
2010 uint32_t addrHigh;
2011 uint32_t ulpIoTag32;
2012} ULP_BDL;
2013
2014
2015
2016
2017
2018enum lpfc_protgrp_type {
2019 LPFC_PG_TYPE_INVALID = 0,
2020 LPFC_PG_TYPE_NO_DIF,
2021 LPFC_PG_TYPE_EMBD_DIF,
2022 LPFC_PG_TYPE_DIF_BUF
2023};
2024
2025
2026#define LPFC_PDE5_DESCRIPTOR 0x85
2027#define LPFC_PDE6_DESCRIPTOR 0x86
2028#define LPFC_PDE7_DESCRIPTOR 0x87
2029
2030
2031#define BG_OP_IN_NODIF_OUT_CRC 0x0
2032#define BG_OP_IN_CRC_OUT_NODIF 0x1
2033#define BG_OP_IN_NODIF_OUT_CSUM 0x2
2034#define BG_OP_IN_CSUM_OUT_NODIF 0x3
2035#define BG_OP_IN_CRC_OUT_CRC 0x4
2036#define BG_OP_IN_CSUM_OUT_CSUM 0x5
2037#define BG_OP_IN_CRC_OUT_CSUM 0x6
2038#define BG_OP_IN_CSUM_OUT_CRC 0x7
2039#define BG_OP_RAW_MODE 0x8
2040
2041struct lpfc_pde5 {
2042 uint32_t word0;
2043#define pde5_type_SHIFT 24
2044#define pde5_type_MASK 0x000000ff
2045#define pde5_type_WORD word0
2046#define pde5_rsvd0_SHIFT 0
2047#define pde5_rsvd0_MASK 0x00ffffff
2048#define pde5_rsvd0_WORD word0
2049 uint32_t reftag;
2050 uint32_t reftagtr;
2051};
2052
2053struct lpfc_pde6 {
2054 uint32_t word0;
2055#define pde6_type_SHIFT 24
2056#define pde6_type_MASK 0x000000ff
2057#define pde6_type_WORD word0
2058#define pde6_rsvd0_SHIFT 0
2059#define pde6_rsvd0_MASK 0x00ffffff
2060#define pde6_rsvd0_WORD word0
2061 uint32_t word1;
2062#define pde6_rsvd1_SHIFT 26
2063#define pde6_rsvd1_MASK 0x0000003f
2064#define pde6_rsvd1_WORD word1
2065#define pde6_na_SHIFT 25
2066#define pde6_na_MASK 0x00000001
2067#define pde6_na_WORD word1
2068#define pde6_rsvd2_SHIFT 16
2069#define pde6_rsvd2_MASK 0x000001FF
2070#define pde6_rsvd2_WORD word1
2071#define pde6_apptagtr_SHIFT 0
2072#define pde6_apptagtr_MASK 0x0000ffff
2073#define pde6_apptagtr_WORD word1
2074 uint32_t word2;
2075#define pde6_optx_SHIFT 28
2076#define pde6_optx_MASK 0x0000000f
2077#define pde6_optx_WORD word2
2078#define pde6_oprx_SHIFT 24
2079#define pde6_oprx_MASK 0x0000000f
2080#define pde6_oprx_WORD word2
2081#define pde6_nr_SHIFT 23
2082#define pde6_nr_MASK 0x00000001
2083#define pde6_nr_WORD word2
2084#define pde6_ce_SHIFT 22
2085#define pde6_ce_MASK 0x00000001
2086#define pde6_ce_WORD word2
2087#define pde6_re_SHIFT 21
2088#define pde6_re_MASK 0x00000001
2089#define pde6_re_WORD word2
2090#define pde6_ae_SHIFT 20
2091#define pde6_ae_MASK 0x00000001
2092#define pde6_ae_WORD word2
2093#define pde6_ai_SHIFT 19
2094#define pde6_ai_MASK 0x00000001
2095#define pde6_ai_WORD word2
2096#define pde6_bs_SHIFT 16
2097#define pde6_bs_MASK 0x00000007
2098#define pde6_bs_WORD word2
2099#define pde6_apptagval_SHIFT 0
2100#define pde6_apptagval_MASK 0x0000ffff
2101#define pde6_apptagval_WORD word2
2102};
2103
2104struct lpfc_pde7 {
2105 uint32_t word0;
2106#define pde7_type_SHIFT 24
2107#define pde7_type_MASK 0x000000ff
2108#define pde7_type_WORD word0
2109#define pde7_rsvd0_SHIFT 0
2110#define pde7_rsvd0_MASK 0x00ffffff
2111#define pde7_rsvd0_WORD word0
2112 uint32_t addrHigh;
2113 uint32_t addrLow;
2114};
2115
2116
2117
2118typedef struct {
2119#ifdef __BIG_ENDIAN_BITFIELD
2120 uint32_t rsvd2:25;
2121 uint32_t acknowledgment:1;
2122 uint32_t version:1;
2123 uint32_t erase_or_prog:1;
2124 uint32_t update_flash:1;
2125 uint32_t update_ram:1;
2126 uint32_t method:1;
2127 uint32_t load_cmplt:1;
2128#else
2129 uint32_t load_cmplt:1;
2130 uint32_t method:1;
2131 uint32_t update_ram:1;
2132 uint32_t update_flash:1;
2133 uint32_t erase_or_prog:1;
2134 uint32_t version:1;
2135 uint32_t acknowledgment:1;
2136 uint32_t rsvd2:25;
2137#endif
2138
2139 uint32_t dl_to_adr_low;
2140 uint32_t dl_to_adr_high;
2141 uint32_t dl_len;
2142 union {
2143 uint32_t dl_from_mbx_offset;
2144 struct ulp_bde dl_from_bde;
2145 struct ulp_bde64 dl_from_bde64;
2146 } un;
2147
2148} LOAD_SM_VAR;
2149
2150
2151
2152typedef struct {
2153 uint32_t rsvd1[3];
2154 uint32_t rsvd2;
2155 uint32_t portname[2];
2156 uint32_t nodename[2];
2157
2158#ifdef __BIG_ENDIAN_BITFIELD
2159 uint32_t pref_DID:24;
2160 uint32_t hardAL_PA:8;
2161#else
2162 uint32_t hardAL_PA:8;
2163 uint32_t pref_DID:24;
2164#endif
2165
2166 uint32_t rsvd3[21];
2167} READ_NV_VAR;
2168
2169
2170
2171typedef struct {
2172 uint32_t rsvd1[3];
2173 uint32_t rsvd2;
2174 uint32_t portname[2];
2175 uint32_t nodename[2];
2176
2177#ifdef __BIG_ENDIAN_BITFIELD
2178 uint32_t pref_DID:24;
2179 uint32_t hardAL_PA:8;
2180#else
2181 uint32_t hardAL_PA:8;
2182 uint32_t pref_DID:24;
2183#endif
2184
2185 uint32_t rsvd3[21];
2186} WRITE_NV_VAR;
2187
2188
2189
2190
2191typedef struct {
2192 uint32_t rsvd1;
2193 union {
2194 struct {
2195 struct ulp_bde xmit_bde;
2196 struct ulp_bde rcv_bde;
2197 } s1;
2198 struct {
2199 struct ulp_bde64 xmit_bde64;
2200 struct ulp_bde64 rcv_bde64;
2201 } s2;
2202 } un;
2203} BIU_DIAG_VAR;
2204
2205
2206struct READ_EVENT_LOG_VAR {
2207 uint32_t word1;
2208#define lpfc_event_log_SHIFT 29
2209#define lpfc_event_log_MASK 0x00000001
2210#define lpfc_event_log_WORD word1
2211#define USE_MAILBOX_RESPONSE 1
2212 uint32_t offset;
2213 struct ulp_bde64 rcv_bde64;
2214};
2215
2216
2217
2218typedef struct {
2219#ifdef __BIG_ENDIAN_BITFIELD
2220 uint32_t rsvd1:24;
2221 uint32_t lipsr_AL_PA:8;
2222#else
2223 uint32_t lipsr_AL_PA:8;
2224 uint32_t rsvd1:24;
2225#endif
2226
2227#ifdef __BIG_ENDIAN_BITFIELD
2228 uint8_t fabric_AL_PA;
2229 uint8_t rsvd2;
2230 uint16_t link_flags;
2231#else
2232 uint16_t link_flags;
2233 uint8_t rsvd2;
2234 uint8_t fabric_AL_PA;
2235#endif
2236
2237#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00
2238#define FLAGS_LOCAL_LB 0x01
2239#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02
2240#define FLAGS_TOPOLOGY_MODE_LOOP 0x04
2241#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06
2242#define FLAGS_UNREG_LOGIN_ALL 0x08
2243#define FLAGS_LIRP_LILP 0x80
2244
2245#define FLAGS_TOPOLOGY_FAILOVER 0x0400
2246#define FLAGS_LINK_SPEED 0x0800
2247#define FLAGS_IMED_ABORT 0x04000
2248
2249 uint32_t link_speed;
2250#define LINK_SPEED_AUTO 0x0
2251#define LINK_SPEED_1G 0x1
2252#define LINK_SPEED_2G 0x2
2253#define LINK_SPEED_4G 0x4
2254#define LINK_SPEED_8G 0x8
2255#define LINK_SPEED_10G 0x10
2256#define LINK_SPEED_16G 0x11
2257#define LINK_SPEED_32G 0x14
2258#define LINK_SPEED_64G 0x17
2259#define LINK_SPEED_128G 0x1A
2260#define LINK_SPEED_256G 0x1D
2261
2262} INIT_LINK_VAR;
2263
2264
2265
2266typedef struct {
2267 uint32_t rsvd1;
2268} DOWN_LINK_VAR;
2269
2270
2271
2272typedef struct {
2273#ifdef __BIG_ENDIAN_BITFIELD
2274 uint32_t cr:1;
2275 uint32_t ci:1;
2276 uint32_t cr_delay:6;
2277 uint32_t cr_count:8;
2278 uint32_t rsvd1:8;
2279 uint32_t MaxBBC:8;
2280#else
2281 uint32_t MaxBBC:8;
2282 uint32_t rsvd1:8;
2283 uint32_t cr_count:8;
2284 uint32_t cr_delay:6;
2285 uint32_t ci:1;
2286 uint32_t cr:1;
2287#endif
2288
2289 uint32_t myId;
2290 uint32_t rsvd2;
2291 uint32_t edtov;
2292 uint32_t arbtov;
2293 uint32_t ratov;
2294 uint32_t rttov;
2295 uint32_t altov;
2296 uint32_t crtov;
2297
2298#ifdef __BIG_ENDIAN_BITFIELD
2299 uint32_t rsvd4:19;
2300 uint32_t cscn:1;
2301 uint32_t bbscn:4;
2302 uint32_t rsvd3:8;
2303#else
2304 uint32_t rsvd3:8;
2305 uint32_t bbscn:4;
2306 uint32_t cscn:1;
2307 uint32_t rsvd4:19;
2308#endif
2309
2310#ifdef __BIG_ENDIAN_BITFIELD
2311 uint32_t rrq_enable:1;
2312 uint32_t rrq_immed:1;
2313 uint32_t rsvd5:29;
2314 uint32_t ack0_enable:1;
2315#else
2316 uint32_t ack0_enable:1;
2317 uint32_t rsvd5:29;
2318 uint32_t rrq_immed:1;
2319 uint32_t rrq_enable:1;
2320#endif
2321} CONFIG_LINK;
2322
2323
2324
2325
2326typedef struct {
2327#ifdef __BIG_ENDIAN_BITFIELD
2328 uint16_t offCiocb;
2329 uint16_t numCiocb;
2330 uint16_t offRiocb;
2331 uint16_t numRiocb;
2332#else
2333 uint16_t numCiocb;
2334 uint16_t offCiocb;
2335 uint16_t numRiocb;
2336 uint16_t offRiocb;
2337#endif
2338} RING_DEF;
2339
2340typedef struct {
2341#ifdef __BIG_ENDIAN_BITFIELD
2342 uint32_t unused1:24;
2343 uint32_t numRing:8;
2344#else
2345 uint32_t numRing:8;
2346 uint32_t unused1:24;
2347#endif
2348
2349 RING_DEF ringdef[4];
2350 uint32_t hbainit;
2351} PART_SLIM_VAR;
2352
2353
2354
2355typedef struct {
2356#ifdef __BIG_ENDIAN_BITFIELD
2357 uint32_t unused2:6;
2358 uint32_t recvSeq:1;
2359 uint32_t recvNotify:1;
2360 uint32_t numMask:8;
2361 uint32_t profile:8;
2362 uint32_t unused1:4;
2363 uint32_t ring:4;
2364#else
2365 uint32_t ring:4;
2366 uint32_t unused1:4;
2367 uint32_t profile:8;
2368 uint32_t numMask:8;
2369 uint32_t recvNotify:1;
2370 uint32_t recvSeq:1;
2371 uint32_t unused2:6;
2372#endif
2373
2374#ifdef __BIG_ENDIAN_BITFIELD
2375 uint16_t maxRespXchg;
2376 uint16_t maxOrigXchg;
2377#else
2378 uint16_t maxOrigXchg;
2379 uint16_t maxRespXchg;
2380#endif
2381
2382 RR_REG rrRegs[6];
2383} CONFIG_RING_VAR;
2384
2385
2386
2387typedef struct {
2388 uint32_t ring_no;
2389} RESET_RING_VAR;
2390
2391
2392
2393typedef struct {
2394#ifdef __BIG_ENDIAN_BITFIELD
2395 uint32_t cr:1;
2396 uint32_t ci:1;
2397 uint32_t cr_delay:6;
2398 uint32_t cr_count:8;
2399 uint32_t InitBBC:8;
2400 uint32_t MaxBBC:8;
2401#else
2402 uint32_t MaxBBC:8;
2403 uint32_t InitBBC:8;
2404 uint32_t cr_count:8;
2405 uint32_t cr_delay:6;
2406 uint32_t ci:1;
2407 uint32_t cr:1;
2408#endif
2409
2410#ifdef __BIG_ENDIAN_BITFIELD
2411 uint32_t topology:8;
2412 uint32_t myDid:24;
2413#else
2414 uint32_t myDid:24;
2415 uint32_t topology:8;
2416#endif
2417
2418
2419#ifdef __BIG_ENDIAN_BITFIELD
2420 uint32_t AR:1;
2421 uint32_t IR:1;
2422 uint32_t rsvd1:29;
2423 uint32_t ack0:1;
2424#else
2425 uint32_t ack0:1;
2426 uint32_t rsvd1:29;
2427 uint32_t IR:1;
2428 uint32_t AR:1;
2429#endif
2430
2431 uint32_t edtov;
2432 uint32_t arbtov;
2433 uint32_t ratov;
2434 uint32_t rttov;
2435 uint32_t altov;
2436 uint32_t lmt;
2437#define LMT_RESERVED 0x000
2438#define LMT_1Gb 0x004
2439#define LMT_2Gb 0x008
2440#define LMT_4Gb 0x040
2441#define LMT_8Gb 0x080
2442#define LMT_10Gb 0x100
2443#define LMT_16Gb 0x200
2444#define LMT_32Gb 0x400
2445#define LMT_64Gb 0x800
2446#define LMT_128Gb 0x1000
2447#define LMT_256Gb 0x2000
2448 uint32_t rsvd2;
2449 uint32_t rsvd3;
2450 uint32_t max_xri;
2451 uint32_t max_iocb;
2452 uint32_t max_rpi;
2453 uint32_t avail_xri;
2454 uint32_t avail_iocb;
2455 uint32_t avail_rpi;
2456 uint32_t max_vpi;
2457 uint32_t rsvd4;
2458 uint32_t rsvd5;
2459 uint32_t avail_vpi;
2460} READ_CONFIG_VAR;
2461
2462
2463
2464typedef struct {
2465#ifdef __BIG_ENDIAN_BITFIELD
2466 uint32_t rsvd2:7;
2467 uint32_t recvNotify:1;
2468 uint32_t numMask:8;
2469 uint32_t profile:8;
2470 uint32_t rsvd1:4;
2471 uint32_t ring:4;
2472#else
2473 uint32_t ring:4;
2474 uint32_t rsvd1:4;
2475 uint32_t profile:8;
2476 uint32_t numMask:8;
2477 uint32_t recvNotify:1;
2478 uint32_t rsvd2:7;
2479#endif
2480
2481#ifdef __BIG_ENDIAN_BITFIELD
2482 uint16_t maxResp;
2483 uint16_t maxOrig;
2484#else
2485 uint16_t maxOrig;
2486 uint16_t maxResp;
2487#endif
2488
2489 RR_REG rrRegs[6];
2490
2491#ifdef __BIG_ENDIAN_BITFIELD
2492 uint16_t cmdRingOffset;
2493 uint16_t cmdEntryCnt;
2494 uint16_t rspRingOffset;
2495 uint16_t rspEntryCnt;
2496 uint16_t nextCmdOffset;
2497 uint16_t rsvd3;
2498 uint16_t nextRspOffset;
2499 uint16_t rsvd4;
2500#else
2501 uint16_t cmdEntryCnt;
2502 uint16_t cmdRingOffset;
2503 uint16_t rspEntryCnt;
2504 uint16_t rspRingOffset;
2505 uint16_t rsvd3;
2506 uint16_t nextCmdOffset;
2507 uint16_t rsvd4;
2508 uint16_t nextRspOffset;
2509#endif
2510} READ_RCONF_VAR;
2511
2512
2513
2514
2515typedef struct {
2516 uint32_t rsvd1;
2517 uint32_t rsvd2;
2518 union {
2519 struct ulp_bde sp;
2520
2521 struct ulp_bde64 sp64;
2522 } un;
2523#ifdef __BIG_ENDIAN_BITFIELD
2524 uint16_t rsvd3;
2525 uint16_t vpi;
2526#else
2527 uint16_t vpi;
2528 uint16_t rsvd3;
2529#endif
2530} READ_SPARM_VAR;
2531
2532
2533
2534typedef struct {
2535#ifdef __BIG_ENDIAN_BITFIELD
2536 uint32_t rsvd1:31;
2537 uint32_t clrCounters:1;
2538 uint16_t activeXriCnt;
2539 uint16_t activeRpiCnt;
2540#else
2541 uint32_t clrCounters:1;
2542 uint32_t rsvd1:31;
2543 uint16_t activeRpiCnt;
2544 uint16_t activeXriCnt;
2545#endif
2546
2547 uint32_t xmitByteCnt;
2548 uint32_t rcvByteCnt;
2549 uint32_t xmitFrameCnt;
2550 uint32_t rcvFrameCnt;
2551 uint32_t xmitSeqCnt;
2552 uint32_t rcvSeqCnt;
2553 uint32_t totalOrigExchanges;
2554 uint32_t totalRespExchanges;
2555 uint32_t rcvPbsyCnt;
2556 uint32_t rcvFbsyCnt;
2557} READ_STATUS_VAR;
2558
2559
2560
2561
2562typedef struct {
2563#ifdef __BIG_ENDIAN_BITFIELD
2564 uint16_t nextRpi;
2565 uint16_t reqRpi;
2566 uint32_t rsvd2:8;
2567 uint32_t DID:24;
2568#else
2569 uint16_t reqRpi;
2570 uint16_t nextRpi;
2571 uint32_t DID:24;
2572 uint32_t rsvd2:8;
2573#endif
2574
2575 union {
2576 struct ulp_bde sp;
2577 struct ulp_bde64 sp64;
2578 } un;
2579
2580} READ_RPI_VAR;
2581
2582
2583
2584typedef struct {
2585#ifdef __BIG_ENDIAN_BITFIELD
2586 uint16_t nextXri;
2587 uint16_t reqXri;
2588 uint16_t rsvd1;
2589 uint16_t rpi;
2590 uint32_t rsvd2:8;
2591 uint32_t DID:24;
2592 uint32_t rsvd3:8;
2593 uint32_t SID:24;
2594 uint32_t rsvd4;
2595 uint8_t seqId;
2596 uint8_t rsvd5;
2597 uint16_t seqCount;
2598 uint16_t oxId;
2599 uint16_t rxId;
2600 uint32_t rsvd6:30;
2601 uint32_t si:1;
2602 uint32_t exchOrig:1;
2603#else
2604 uint16_t reqXri;
2605 uint16_t nextXri;
2606 uint16_t rpi;
2607 uint16_t rsvd1;
2608 uint32_t DID:24;
2609 uint32_t rsvd2:8;
2610 uint32_t SID:24;
2611 uint32_t rsvd3:8;
2612 uint32_t rsvd4;
2613 uint16_t seqCount;
2614 uint8_t rsvd5;
2615 uint8_t seqId;
2616 uint16_t rxId;
2617 uint16_t oxId;
2618 uint32_t exchOrig:1;
2619 uint32_t si:1;
2620 uint32_t rsvd6:30;
2621#endif
2622} READ_XRI_VAR;
2623
2624
2625
2626typedef struct {
2627#ifdef __BIG_ENDIAN_BITFIELD
2628 uint32_t cv:1;
2629 uint32_t rr:1;
2630 uint32_t rsvd2:2;
2631 uint32_t v3req:1;
2632 uint32_t v3rsp:1;
2633 uint32_t rsvd1:25;
2634 uint32_t rv:1;
2635#else
2636 uint32_t rv:1;
2637 uint32_t rsvd1:25;
2638 uint32_t v3rsp:1;
2639 uint32_t v3req:1;
2640 uint32_t rsvd2:2;
2641 uint32_t rr:1;
2642 uint32_t cv:1;
2643#endif
2644
2645 uint32_t biuRev;
2646 uint32_t smRev;
2647 union {
2648 uint32_t smFwRev;
2649 struct {
2650#ifdef __BIG_ENDIAN_BITFIELD
2651 uint8_t ProgType;
2652 uint8_t ProgId;
2653 uint16_t ProgVer:4;
2654 uint16_t ProgRev:4;
2655 uint16_t ProgFixLvl:2;
2656 uint16_t ProgDistType:2;
2657 uint16_t DistCnt:4;
2658#else
2659 uint16_t DistCnt:4;
2660 uint16_t ProgDistType:2;
2661 uint16_t ProgFixLvl:2;
2662 uint16_t ProgRev:4;
2663 uint16_t ProgVer:4;
2664 uint8_t ProgId;
2665 uint8_t ProgType;
2666#endif
2667
2668 } b;
2669 } un;
2670 uint32_t endecRev;
2671#ifdef __BIG_ENDIAN_BITFIELD
2672 uint8_t feaLevelHigh;
2673 uint8_t feaLevelLow;
2674 uint8_t fcphHigh;
2675 uint8_t fcphLow;
2676#else
2677 uint8_t fcphLow;
2678 uint8_t fcphHigh;
2679 uint8_t feaLevelLow;
2680 uint8_t feaLevelHigh;
2681#endif
2682
2683 uint32_t postKernRev;
2684 uint32_t opFwRev;
2685 uint8_t opFwName[16];
2686 uint32_t sli1FwRev;
2687 uint8_t sli1FwName[16];
2688 uint32_t sli2FwRev;
2689 uint8_t sli2FwName[16];
2690 uint32_t sli3Feat;
2691 uint32_t RandomData[6];
2692} READ_REV_VAR;
2693
2694
2695
2696typedef struct {
2697 uint32_t word0;
2698
2699#define lpfc_read_link_stat_rec_SHIFT 0
2700#define lpfc_read_link_stat_rec_MASK 0x1
2701#define lpfc_read_link_stat_rec_WORD word0
2702
2703#define lpfc_read_link_stat_gec_SHIFT 1
2704#define lpfc_read_link_stat_gec_MASK 0x1
2705#define lpfc_read_link_stat_gec_WORD word0
2706
2707#define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2708#define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2709#define lpfc_read_link_stat_w02oftow23of_WORD word0
2710
2711#define lpfc_read_link_stat_rsvd_SHIFT 24
2712#define lpfc_read_link_stat_rsvd_MASK 0x1F
2713#define lpfc_read_link_stat_rsvd_WORD word0
2714
2715#define lpfc_read_link_stat_gec2_SHIFT 29
2716#define lpfc_read_link_stat_gec2_MASK 0x1
2717#define lpfc_read_link_stat_gec2_WORD word0
2718
2719#define lpfc_read_link_stat_clrc_SHIFT 30
2720#define lpfc_read_link_stat_clrc_MASK 0x1
2721#define lpfc_read_link_stat_clrc_WORD word0
2722
2723#define lpfc_read_link_stat_clof_SHIFT 31
2724#define lpfc_read_link_stat_clof_MASK 0x1
2725#define lpfc_read_link_stat_clof_WORD word0
2726
2727 uint32_t linkFailureCnt;
2728 uint32_t lossSyncCnt;
2729 uint32_t lossSignalCnt;
2730 uint32_t primSeqErrCnt;
2731 uint32_t invalidXmitWord;
2732 uint32_t crcCnt;
2733 uint32_t primSeqTimeout;
2734 uint32_t elasticOverrun;
2735 uint32_t arbTimeout;
2736 uint32_t advRecBufCredit;
2737 uint32_t curRecBufCredit;
2738 uint32_t advTransBufCredit;
2739 uint32_t curTransBufCredit;
2740 uint32_t recEofCount;
2741 uint32_t recEofdtiCount;
2742 uint32_t recEofniCount;
2743 uint32_t recSofcount;
2744 uint32_t rsvd1;
2745 uint32_t rsvd2;
2746 uint32_t recDrpXriCount;
2747 uint32_t fecCorrBlkCount;
2748 uint32_t fecUncorrBlkCount;
2749} READ_LNK_VAR;
2750
2751
2752
2753
2754typedef struct {
2755#ifdef __BIG_ENDIAN_BITFIELD
2756 uint16_t rsvd1;
2757 uint16_t rpi;
2758 uint32_t rsvd2:8;
2759 uint32_t did:24;
2760#else
2761 uint16_t rpi;
2762 uint16_t rsvd1;
2763 uint32_t did:24;
2764 uint32_t rsvd2:8;
2765#endif
2766
2767 union {
2768 struct ulp_bde sp;
2769 struct ulp_bde64 sp64;
2770 } un;
2771
2772#ifdef __BIG_ENDIAN_BITFIELD
2773 uint16_t rsvd6;
2774 uint16_t vpi;
2775#else
2776 uint16_t vpi;
2777 uint16_t rsvd6;
2778#endif
2779
2780} REG_LOGIN_VAR;
2781
2782
2783typedef union {
2784 struct {
2785#ifdef __BIG_ENDIAN_BITFIELD
2786 uint16_t rsvd1:12;
2787 uint16_t wd30_class:4;
2788 uint16_t xri;
2789#else
2790 uint16_t xri;
2791 uint16_t wd30_class:4;
2792 uint16_t rsvd1:12;
2793#endif
2794 } f;
2795 uint32_t word;
2796} REG_WD30;
2797
2798
2799
2800typedef struct {
2801#ifdef __BIG_ENDIAN_BITFIELD
2802 uint16_t rsvd1;
2803 uint16_t rpi;
2804 uint32_t rsvd2;
2805 uint32_t rsvd3;
2806 uint32_t rsvd4;
2807 uint32_t rsvd5;
2808 uint16_t rsvd6;
2809 uint16_t vpi;
2810#else
2811 uint16_t rpi;
2812 uint16_t rsvd1;
2813 uint32_t rsvd2;
2814 uint32_t rsvd3;
2815 uint32_t rsvd4;
2816 uint32_t rsvd5;
2817 uint16_t vpi;
2818 uint16_t rsvd6;
2819#endif
2820} UNREG_LOGIN_VAR;
2821
2822
2823typedef struct {
2824#ifdef __BIG_ENDIAN_BITFIELD
2825 uint32_t rsvd1;
2826 uint32_t rsvd2:7;
2827 uint32_t upd:1;
2828 uint32_t sid:24;
2829 uint32_t wwn[2];
2830 uint32_t rsvd5;
2831 uint16_t vfi;
2832 uint16_t vpi;
2833#else
2834 uint32_t rsvd1;
2835 uint32_t sid:24;
2836 uint32_t upd:1;
2837 uint32_t rsvd2:7;
2838 uint32_t wwn[2];
2839 uint32_t rsvd5;
2840 uint16_t vpi;
2841 uint16_t vfi;
2842#endif
2843} REG_VPI_VAR;
2844
2845
2846typedef struct {
2847 uint32_t rsvd1;
2848#ifdef __BIG_ENDIAN_BITFIELD
2849 uint16_t rsvd2;
2850 uint16_t sli4_vpi;
2851#else
2852 uint16_t sli4_vpi;
2853 uint16_t rsvd2;
2854#endif
2855 uint32_t rsvd3;
2856 uint32_t rsvd4;
2857 uint32_t rsvd5;
2858#ifdef __BIG_ENDIAN_BITFIELD
2859 uint16_t rsvd6;
2860 uint16_t vpi;
2861#else
2862 uint16_t vpi;
2863 uint16_t rsvd6;
2864#endif
2865} UNREG_VPI_VAR;
2866
2867
2868
2869typedef struct {
2870 uint32_t did;
2871 uint32_t rsvd2;
2872 uint32_t rsvd3;
2873 uint32_t rsvd4;
2874 uint32_t rsvd5;
2875#ifdef __BIG_ENDIAN_BITFIELD
2876 uint16_t rsvd6;
2877 uint16_t vpi;
2878#else
2879 uint16_t vpi;
2880 uint16_t rsvd6;
2881#endif
2882} UNREG_D_ID_VAR;
2883
2884
2885struct lpfc_mbx_read_top {
2886 uint32_t eventTag;
2887 uint32_t word2;
2888#define lpfc_mbx_read_top_fa_SHIFT 12
2889#define lpfc_mbx_read_top_fa_MASK 0x00000001
2890#define lpfc_mbx_read_top_fa_WORD word2
2891#define lpfc_mbx_read_top_mm_SHIFT 11
2892#define lpfc_mbx_read_top_mm_MASK 0x00000001
2893#define lpfc_mbx_read_top_mm_WORD word2
2894#define lpfc_mbx_read_top_pb_SHIFT 9
2895#define lpfc_mbx_read_top_pb_MASK 0X00000001
2896#define lpfc_mbx_read_top_pb_WORD word2
2897#define lpfc_mbx_read_top_il_SHIFT 8
2898#define lpfc_mbx_read_top_il_MASK 0x00000001
2899#define lpfc_mbx_read_top_il_WORD word2
2900#define lpfc_mbx_read_top_att_type_SHIFT 0
2901#define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2902#define lpfc_mbx_read_top_att_type_WORD word2
2903#define LPFC_ATT_RESERVED 0x00
2904#define LPFC_ATT_LINK_UP 0x01
2905#define LPFC_ATT_LINK_DOWN 0x02
2906#define LPFC_ATT_UNEXP_WWPN 0x06
2907 uint32_t word3;
2908#define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2909#define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2910#define lpfc_mbx_read_top_alpa_granted_WORD word3
2911#define lpfc_mbx_read_top_lip_alps_SHIFT 16
2912#define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2913#define lpfc_mbx_read_top_lip_alps_WORD word3
2914#define lpfc_mbx_read_top_lip_type_SHIFT 8
2915#define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2916#define lpfc_mbx_read_top_lip_type_WORD word3
2917#define lpfc_mbx_read_top_topology_SHIFT 0
2918#define lpfc_mbx_read_top_topology_MASK 0x000000FF
2919#define lpfc_mbx_read_top_topology_WORD word3
2920#define LPFC_TOPOLOGY_PT_PT 0x01
2921#define LPFC_TOPOLOGY_LOOP 0x02
2922#define LPFC_TOPOLOGY_MM 0x05
2923
2924 struct ulp_bde64 lilpBde64;
2925#define LPFC_ALPA_MAP_SIZE 128
2926 uint32_t word7;
2927#define lpfc_mbx_read_top_ld_lu_SHIFT 31
2928#define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2929#define lpfc_mbx_read_top_ld_lu_WORD word7
2930#define lpfc_mbx_read_top_ld_tf_SHIFT 30
2931#define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2932#define lpfc_mbx_read_top_ld_tf_WORD word7
2933#define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2934#define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2935#define lpfc_mbx_read_top_ld_link_spd_WORD word7
2936#define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2937#define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2938#define lpfc_mbx_read_top_ld_nl_port_WORD word7
2939#define lpfc_mbx_read_top_ld_tx_SHIFT 2
2940#define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2941#define lpfc_mbx_read_top_ld_tx_WORD word7
2942#define lpfc_mbx_read_top_ld_rx_SHIFT 0
2943#define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2944#define lpfc_mbx_read_top_ld_rx_WORD word7
2945 uint32_t word8;
2946#define lpfc_mbx_read_top_lu_SHIFT 31
2947#define lpfc_mbx_read_top_lu_MASK 0x00000001
2948#define lpfc_mbx_read_top_lu_WORD word8
2949#define lpfc_mbx_read_top_tf_SHIFT 30
2950#define lpfc_mbx_read_top_tf_MASK 0x00000001
2951#define lpfc_mbx_read_top_tf_WORD word8
2952#define lpfc_mbx_read_top_link_spd_SHIFT 8
2953#define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2954#define lpfc_mbx_read_top_link_spd_WORD word8
2955#define lpfc_mbx_read_top_nl_port_SHIFT 4
2956#define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2957#define lpfc_mbx_read_top_nl_port_WORD word8
2958#define lpfc_mbx_read_top_tx_SHIFT 2
2959#define lpfc_mbx_read_top_tx_MASK 0x00000003
2960#define lpfc_mbx_read_top_tx_WORD word8
2961#define lpfc_mbx_read_top_rx_SHIFT 0
2962#define lpfc_mbx_read_top_rx_MASK 0x00000003
2963#define lpfc_mbx_read_top_rx_WORD word8
2964#define LPFC_LINK_SPEED_UNKNOWN 0x0
2965#define LPFC_LINK_SPEED_1GHZ 0x04
2966#define LPFC_LINK_SPEED_2GHZ 0x08
2967#define LPFC_LINK_SPEED_4GHZ 0x10
2968#define LPFC_LINK_SPEED_8GHZ 0x20
2969#define LPFC_LINK_SPEED_10GHZ 0x40
2970#define LPFC_LINK_SPEED_16GHZ 0x80
2971#define LPFC_LINK_SPEED_32GHZ 0x90
2972#define LPFC_LINK_SPEED_64GHZ 0xA0
2973#define LPFC_LINK_SPEED_128GHZ 0xB0
2974#define LPFC_LINK_SPEED_256GHZ 0xC0
2975};
2976
2977
2978
2979typedef struct {
2980 uint32_t eventTag;
2981 uint32_t rsvd1;
2982} CLEAR_LA_VAR;
2983
2984
2985
2986typedef struct {
2987#ifdef __BIG_ENDIAN_BITFIELD
2988 uint32_t rsvd:25;
2989 uint32_t ra:1;
2990 uint32_t co:1;
2991 uint32_t cv:1;
2992 uint32_t type:4;
2993 uint32_t entry_index:16;
2994 uint32_t region_id:16;
2995#else
2996 uint32_t type:4;
2997 uint32_t cv:1;
2998 uint32_t co:1;
2999 uint32_t ra:1;
3000 uint32_t rsvd:25;
3001 uint32_t region_id:16;
3002 uint32_t entry_index:16;
3003#endif
3004
3005 uint32_t sli4_length;
3006 uint32_t word_cnt;
3007 uint32_t resp_offset;
3008} DUMP_VAR;
3009
3010#define DMP_MEM_REG 0x1
3011#define DMP_NV_PARAMS 0x2
3012#define DMP_LMSD 0x3
3013#define DMP_WELL_KNOWN 0x4
3014
3015#define DMP_REGION_VPD 0xe
3016#define DMP_VPD_SIZE 0x400
3017#define DMP_RSP_OFFSET 0x14
3018#define DMP_RSP_SIZE 0x6C
3019
3020#define DMP_REGION_VPORT 0x16
3021#define DMP_VPORT_REGION_SIZE 0x200
3022#define DMP_MBOX_OFFSET_WORD 0x5
3023
3024#define DMP_REGION_23 0x17
3025#define DMP_RGN23_SIZE 0x400
3026
3027#define WAKE_UP_PARMS_REGION_ID 4
3028#define WAKE_UP_PARMS_WORD_SIZE 15
3029
3030struct vport_rec {
3031 uint8_t wwpn[8];
3032 uint8_t wwnn[8];
3033};
3034
3035#define VPORT_INFO_SIG 0x32324752
3036#define VPORT_INFO_REV_MASK 0xff
3037#define VPORT_INFO_REV 0x1
3038#define MAX_STATIC_VPORT_COUNT 16
3039struct static_vport_info {
3040 uint32_t signature;
3041 uint32_t rev;
3042 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
3043 uint32_t resvd[66];
3044};
3045
3046
3047struct prog_id {
3048#ifdef __BIG_ENDIAN_BITFIELD
3049 uint8_t type;
3050 uint8_t id;
3051 uint32_t ver:4;
3052 uint32_t rev:4;
3053 uint32_t lev:2;
3054 uint32_t dist:2;
3055 uint32_t num:4;
3056#else
3057 uint32_t num:4;
3058 uint32_t dist:2;
3059 uint32_t lev:2;
3060 uint32_t rev:4;
3061 uint32_t ver:4;
3062 uint8_t id;
3063 uint8_t type;
3064#endif
3065};
3066
3067
3068
3069struct update_cfg_var {
3070#ifdef __BIG_ENDIAN_BITFIELD
3071 uint32_t rsvd2:16;
3072 uint32_t type:8;
3073 uint32_t rsvd:1;
3074 uint32_t ra:1;
3075 uint32_t co:1;
3076 uint32_t cv:1;
3077 uint32_t req:4;
3078 uint32_t entry_length:16;
3079 uint32_t region_id:16;
3080#else
3081 uint32_t req:4;
3082 uint32_t cv:1;
3083 uint32_t co:1;
3084 uint32_t ra:1;
3085 uint32_t rsvd:1;
3086 uint32_t type:8;
3087 uint32_t rsvd2:16;
3088 uint32_t region_id:16;
3089 uint32_t entry_length:16;
3090#endif
3091
3092 uint32_t resp_info;
3093 uint32_t byte_cnt;
3094 uint32_t data_offset;
3095};
3096
3097struct hbq_mask {
3098#ifdef __BIG_ENDIAN_BITFIELD
3099 uint8_t tmatch;
3100 uint8_t tmask;
3101 uint8_t rctlmatch;
3102 uint8_t rctlmask;
3103#else
3104 uint8_t rctlmask;
3105 uint8_t rctlmatch;
3106 uint8_t tmask;
3107 uint8_t tmatch;
3108#endif
3109};
3110
3111
3112
3113
3114struct config_hbq_var {
3115#ifdef __BIG_ENDIAN_BITFIELD
3116 uint32_t rsvd1 :7;
3117 uint32_t recvNotify :1;
3118 uint32_t numMask :8;
3119 uint32_t profile :8;
3120 uint32_t rsvd2 :8;
3121#else
3122 uint32_t rsvd2 :8;
3123 uint32_t profile :8;
3124 uint32_t numMask :8;
3125 uint32_t recvNotify :1;
3126 uint32_t rsvd1 :7;
3127#endif
3128
3129#ifdef __BIG_ENDIAN_BITFIELD
3130 uint32_t hbqId :16;
3131 uint32_t rsvd3 :12;
3132 uint32_t ringMask :4;
3133#else
3134 uint32_t ringMask :4;
3135 uint32_t rsvd3 :12;
3136 uint32_t hbqId :16;
3137#endif
3138
3139#ifdef __BIG_ENDIAN_BITFIELD
3140 uint32_t entry_count :16;
3141 uint32_t rsvd4 :8;
3142 uint32_t headerLen :8;
3143#else
3144 uint32_t headerLen :8;
3145 uint32_t rsvd4 :8;
3146 uint32_t entry_count :16;
3147#endif
3148
3149 uint32_t hbqaddrLow;
3150 uint32_t hbqaddrHigh;
3151
3152#ifdef __BIG_ENDIAN_BITFIELD
3153 uint32_t rsvd5 :31;
3154 uint32_t logEntry :1;
3155#else
3156 uint32_t logEntry :1;
3157 uint32_t rsvd5 :31;
3158#endif
3159
3160 uint32_t rsvd6;
3161 uint32_t rsvd7;
3162 uint32_t rsvd8;
3163
3164 struct hbq_mask hbqMasks[6];
3165
3166
3167 union {
3168 uint32_t allprofiles[12];
3169
3170 struct {
3171 #ifdef __BIG_ENDIAN_BITFIELD
3172 uint32_t seqlenoff :16;
3173 uint32_t maxlen :16;
3174 #else
3175 uint32_t maxlen :16;
3176 uint32_t seqlenoff :16;
3177 #endif
3178 #ifdef __BIG_ENDIAN_BITFIELD
3179 uint32_t rsvd1 :28;
3180 uint32_t seqlenbcnt :4;
3181 #else
3182 uint32_t seqlenbcnt :4;
3183 uint32_t rsvd1 :28;
3184 #endif
3185 uint32_t rsvd[10];
3186 } profile2;
3187
3188 struct {
3189 #ifdef __BIG_ENDIAN_BITFIELD
3190 uint32_t seqlenoff :16;
3191 uint32_t maxlen :16;
3192 #else
3193 uint32_t maxlen :16;
3194 uint32_t seqlenoff :16;
3195 #endif
3196 #ifdef __BIG_ENDIAN_BITFIELD
3197 uint32_t cmdcodeoff :28;
3198 uint32_t rsvd1 :12;
3199 uint32_t seqlenbcnt :4;
3200 #else
3201 uint32_t seqlenbcnt :4;
3202 uint32_t rsvd1 :12;
3203 uint32_t cmdcodeoff :28;
3204 #endif
3205 uint32_t cmdmatch[8];
3206
3207 uint32_t rsvd[2];
3208 } profile3;
3209
3210 struct {
3211 #ifdef __BIG_ENDIAN_BITFIELD
3212 uint32_t seqlenoff :16;
3213 uint32_t maxlen :16;
3214 #else
3215 uint32_t maxlen :16;
3216 uint32_t seqlenoff :16;
3217 #endif
3218 #ifdef __BIG_ENDIAN_BITFIELD
3219 uint32_t cmdcodeoff :28;
3220 uint32_t rsvd1 :12;
3221 uint32_t seqlenbcnt :4;
3222 #else
3223 uint32_t seqlenbcnt :4;
3224 uint32_t rsvd1 :12;
3225 uint32_t cmdcodeoff :28;
3226 #endif
3227 uint32_t cmdmatch[8];
3228
3229 uint32_t rsvd[2];
3230 } profile5;
3231
3232 } profiles;
3233
3234};
3235
3236
3237
3238
3239typedef struct {
3240#ifdef __BIG_ENDIAN_BITFIELD
3241 uint32_t cBE : 1;
3242 uint32_t cET : 1;
3243 uint32_t cHpcb : 1;
3244 uint32_t cMA : 1;
3245 uint32_t sli_mode : 4;
3246 uint32_t pcbLen : 24;
3247
3248#else
3249 uint32_t pcbLen : 24;
3250
3251 uint32_t sli_mode : 4;
3252 uint32_t cMA : 1;
3253 uint32_t cHpcb : 1;
3254 uint32_t cET : 1;
3255 uint32_t cBE : 1;
3256#endif
3257
3258 uint32_t pcbLow;
3259 uint32_t pcbHigh;
3260 uint32_t hbainit[5];
3261#ifdef __BIG_ENDIAN_BITFIELD
3262 uint32_t hps : 1;
3263 uint32_t rsvd : 31;
3264#else
3265 uint32_t rsvd : 31;
3266 uint32_t hps : 1;
3267#endif
3268
3269#ifdef __BIG_ENDIAN_BITFIELD
3270 uint32_t rsvd1 : 20;
3271 uint32_t casabt : 1;
3272 uint32_t rsvd2 : 2;
3273 uint32_t cbg : 1;
3274 uint32_t cmv : 1;
3275 uint32_t ccrp : 1;
3276 uint32_t csah : 1;
3277 uint32_t chbs : 1;
3278 uint32_t cinb : 1;
3279 uint32_t cerbm : 1;
3280 uint32_t cmx : 1;
3281 uint32_t cmr : 1;
3282#else
3283 uint32_t cmr : 1;
3284 uint32_t cmx : 1;
3285 uint32_t cerbm : 1;
3286 uint32_t cinb : 1;
3287 uint32_t chbs : 1;
3288 uint32_t csah : 1;
3289 uint32_t ccrp : 1;
3290 uint32_t cmv : 1;
3291 uint32_t cbg : 1;
3292 uint32_t rsvd2 : 2;
3293 uint32_t casabt : 1;
3294 uint32_t rsvd1 : 20;
3295#endif
3296#ifdef __BIG_ENDIAN_BITFIELD
3297 uint32_t rsvd3 : 20;
3298 uint32_t gasabt : 1;
3299 uint32_t rsvd4 : 2;
3300 uint32_t gbg : 1;
3301 uint32_t gmv : 1;
3302 uint32_t gcrp : 1;
3303 uint32_t gsah : 1;
3304 uint32_t ghbs : 1;
3305 uint32_t ginb : 1;
3306 uint32_t gerbm : 1;
3307 uint32_t gmx : 1;
3308 uint32_t gmr : 1;
3309#else
3310 uint32_t gmr : 1;
3311 uint32_t gmx : 1;
3312 uint32_t gerbm : 1;
3313 uint32_t ginb : 1;
3314 uint32_t ghbs : 1;
3315 uint32_t gsah : 1;
3316 uint32_t gcrp : 1;
3317 uint32_t gmv : 1;
3318 uint32_t gbg : 1;
3319 uint32_t rsvd4 : 2;
3320 uint32_t gasabt : 1;
3321 uint32_t rsvd3 : 20;
3322#endif
3323
3324#ifdef __BIG_ENDIAN_BITFIELD
3325 uint32_t max_rpi : 16;
3326 uint32_t max_xri : 16;
3327#else
3328 uint32_t max_xri : 16;
3329 uint32_t max_rpi : 16;
3330#endif
3331
3332#ifdef __BIG_ENDIAN_BITFIELD
3333 uint32_t max_hbq : 16;
3334 uint32_t rsvd5 : 16;
3335#else
3336 uint32_t rsvd5 : 16;
3337 uint32_t max_hbq : 16;
3338#endif
3339
3340 uint32_t rsvd6;
3341
3342#ifdef __BIG_ENDIAN_BITFIELD
3343 uint32_t rsvd7 : 16;
3344 uint32_t max_vpi : 16;
3345#else
3346 uint32_t max_vpi : 16;
3347 uint32_t rsvd7 : 16;
3348#endif
3349
3350} CONFIG_PORT_VAR;
3351
3352
3353struct config_msi_var {
3354#ifdef __BIG_ENDIAN_BITFIELD
3355 uint32_t dfltMsgNum:8;
3356 uint32_t rsvd1:11;
3357 uint32_t NID:5;
3358 uint32_t rsvd2:5;
3359 uint32_t dfltPresent:1;
3360 uint32_t addFlag:1;
3361 uint32_t reportFlag:1;
3362#else
3363 uint32_t reportFlag:1;
3364 uint32_t addFlag:1;
3365 uint32_t dfltPresent:1;
3366 uint32_t rsvd2:5;
3367 uint32_t NID:5;
3368 uint32_t rsvd1:11;
3369 uint32_t dfltMsgNum:8;
3370#endif
3371 uint32_t attentionConditions[2];
3372 uint8_t attentionId[16];
3373 uint8_t messageNumberByHA[64];
3374 uint8_t messageNumberByID[16];
3375 uint32_t autoClearHA[2];
3376#ifdef __BIG_ENDIAN_BITFIELD
3377 uint32_t rsvd3:16;
3378 uint32_t autoClearID:16;
3379#else
3380 uint32_t autoClearID:16;
3381 uint32_t rsvd3:16;
3382#endif
3383 uint32_t rsvd4;
3384};
3385
3386
3387
3388
3389#define SLIMOFF 0x30
3390
3391typedef struct _SLI2_RDSC {
3392 uint32_t cmdEntries;
3393 uint32_t cmdAddrLow;
3394 uint32_t cmdAddrHigh;
3395
3396 uint32_t rspEntries;
3397 uint32_t rspAddrLow;
3398 uint32_t rspAddrHigh;
3399} SLI2_RDSC;
3400
3401typedef struct _PCB {
3402#ifdef __BIG_ENDIAN_BITFIELD
3403 uint32_t type:8;
3404#define TYPE_NATIVE_SLI2 0x01
3405 uint32_t feature:8;
3406#define FEATURE_INITIAL_SLI2 0x01
3407 uint32_t rsvd:12;
3408 uint32_t maxRing:4;
3409#else
3410 uint32_t maxRing:4;
3411 uint32_t rsvd:12;
3412 uint32_t feature:8;
3413#define FEATURE_INITIAL_SLI2 0x01
3414 uint32_t type:8;
3415#define TYPE_NATIVE_SLI2 0x01
3416#endif
3417
3418 uint32_t mailBoxSize;
3419 uint32_t mbAddrLow;
3420 uint32_t mbAddrHigh;
3421
3422 uint32_t hgpAddrLow;
3423 uint32_t hgpAddrHigh;
3424
3425 uint32_t pgpAddrLow;
3426 uint32_t pgpAddrHigh;
3427 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3428} PCB_t;
3429
3430
3431typedef struct {
3432#ifdef __BIG_ENDIAN_BITFIELD
3433 uint32_t rsvd0:27;
3434 uint32_t discardFarp:1;
3435 uint32_t IPEnable:1;
3436 uint32_t nodeName:1;
3437 uint32_t portName:1;
3438 uint32_t filterEnable:1;
3439#else
3440 uint32_t filterEnable:1;
3441 uint32_t portName:1;
3442 uint32_t nodeName:1;
3443 uint32_t IPEnable:1;
3444 uint32_t discardFarp:1;
3445 uint32_t rsvd:27;
3446#endif
3447
3448 uint8_t portname[8];
3449 uint8_t nodename[8];
3450 uint32_t rsvd1;
3451 uint32_t rsvd2;
3452 uint32_t rsvd3;
3453 uint32_t IPAddress;
3454} CONFIG_FARP_VAR;
3455
3456
3457
3458typedef struct {
3459#ifdef __BIG_ENDIAN_BITFIELD
3460 uint32_t rsvd:30;
3461 uint32_t ring:2;
3462#else
3463 uint32_t ring:2;
3464 uint32_t rsvd:30;
3465#endif
3466} ASYNCEVT_ENABLE_VAR;
3467
3468
3469#define MAILBOX_CMD_WSIZE 32
3470#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3471
3472#define MAILBOX_EXT_WSIZE 512
3473#define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3474#define MAILBOX_HBA_EXT_OFFSET 0x100
3475
3476#define MAILBOX_SYSFS_MAX 4096
3477
3478typedef union {
3479 uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
3480
3481
3482 LOAD_SM_VAR varLdSM;
3483 READ_NV_VAR varRDnvp;
3484 WRITE_NV_VAR varWTnvp;
3485 BIU_DIAG_VAR varBIUdiag;
3486 INIT_LINK_VAR varInitLnk;
3487 DOWN_LINK_VAR varDwnLnk;
3488 CONFIG_LINK varCfgLnk;
3489 PART_SLIM_VAR varSlim;
3490 CONFIG_RING_VAR varCfgRing;
3491 RESET_RING_VAR varRstRing;
3492 READ_CONFIG_VAR varRdConfig;
3493 READ_RCONF_VAR varRdRConfig;
3494 READ_SPARM_VAR varRdSparm;
3495 READ_STATUS_VAR varRdStatus;
3496 READ_RPI_VAR varRdRPI;
3497 READ_XRI_VAR varRdXRI;
3498 READ_REV_VAR varRdRev;
3499 READ_LNK_VAR varRdLnk;
3500 REG_LOGIN_VAR varRegLogin;
3501 UNREG_LOGIN_VAR varUnregLogin;
3502 CLEAR_LA_VAR varClearLA;
3503 DUMP_VAR varDmp;
3504 UNREG_D_ID_VAR varUnregDID;
3505 CONFIG_FARP_VAR varCfgFarp;
3506
3507
3508 struct config_hbq_var varCfgHbq;
3509 struct update_cfg_var varUpdateCfg;
3510 CONFIG_PORT_VAR varCfgPort;
3511 struct lpfc_mbx_read_top varReadTop;
3512 REG_VPI_VAR varRegVpi;
3513 UNREG_VPI_VAR varUnregVpi;
3514 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent;
3515 struct READ_EVENT_LOG_VAR varRdEventLog;
3516
3517
3518 struct config_msi_var varCfgMSI;
3519} MAILVARIANTS;
3520
3521
3522
3523
3524
3525struct lpfc_hgp {
3526 __le32 cmdPutInx;
3527 __le32 rspGetInx;
3528};
3529
3530struct lpfc_pgp {
3531 __le32 cmdGetInx;
3532 __le32 rspPutInx;
3533};
3534
3535struct sli2_desc {
3536 uint32_t unused1[16];
3537 struct lpfc_hgp host[MAX_SLI3_RINGS];
3538 struct lpfc_pgp port[MAX_SLI3_RINGS];
3539};
3540
3541struct sli3_desc {
3542 struct lpfc_hgp host[MAX_SLI3_RINGS];
3543 uint32_t reserved[8];
3544 uint32_t hbq_put[16];
3545};
3546
3547struct sli3_pgp {
3548 struct lpfc_pgp port[MAX_SLI3_RINGS];
3549 uint32_t hbq_get[16];
3550};
3551
3552union sli_var {
3553 struct sli2_desc s2;
3554 struct sli3_desc s3;
3555 struct sli3_pgp s3_pgp;
3556};
3557
3558typedef struct {
3559#ifdef __BIG_ENDIAN_BITFIELD
3560 uint16_t mbxStatus;
3561 uint8_t mbxCommand;
3562 uint8_t mbxReserved:6;
3563 uint8_t mbxHc:1;
3564 uint8_t mbxOwner:1;
3565#else
3566 uint8_t mbxOwner:1;
3567 uint8_t mbxHc:1;
3568 uint8_t mbxReserved:6;
3569 uint8_t mbxCommand;
3570 uint16_t mbxStatus;
3571#endif
3572
3573 MAILVARIANTS un;
3574 union sli_var us;
3575} MAILBOX_t;
3576
3577
3578
3579
3580
3581typedef struct {
3582#ifdef __BIG_ENDIAN_BITFIELD
3583 uint8_t statAction;
3584 uint8_t statRsn;
3585 uint8_t statBaExp;
3586 uint8_t statLocalError;
3587#else
3588 uint8_t statLocalError;
3589 uint8_t statBaExp;
3590 uint8_t statRsn;
3591 uint8_t statAction;
3592#endif
3593
3594#define RJT_BAD_D_ID 0x01
3595#define RJT_BAD_S_ID 0x02
3596#define RJT_UNAVAIL_TEMP 0x03
3597#define RJT_UNAVAIL_PERM 0x04
3598#define RJT_UNSUP_CLASS 0x05
3599#define RJT_DELIM_ERR 0x06
3600#define RJT_UNSUP_TYPE 0x07
3601#define RJT_BAD_CONTROL 0x08
3602#define RJT_BAD_RCTL 0x09
3603#define RJT_BAD_FCTL 0x0A
3604#define RJT_BAD_OXID 0x0B
3605#define RJT_BAD_RXID 0x0C
3606#define RJT_BAD_SEQID 0x0D
3607#define RJT_BAD_DFCTL 0x0E
3608#define RJT_BAD_SEQCNT 0x0F
3609#define RJT_BAD_PARM 0x10
3610#define RJT_XCHG_ERR 0x11
3611#define RJT_PROT_ERR 0x12
3612#define RJT_BAD_LENGTH 0x13
3613#define RJT_UNEXPECTED_ACK 0x14
3614#define RJT_LOGIN_REQUIRED 0x16
3615#define RJT_TOO_MANY_SEQ 0x17
3616#define RJT_XCHG_NOT_STRT 0x18
3617#define RJT_UNSUP_SEC_HDR 0x19
3618#define RJT_UNAVAIL_PATH 0x1A
3619#define RJT_VENDOR_UNIQUE 0xFF
3620
3621#define IOERR_SUCCESS 0x00
3622#define IOERR_MISSING_CONTINUE 0x01
3623#define IOERR_SEQUENCE_TIMEOUT 0x02
3624#define IOERR_INTERNAL_ERROR 0x03
3625#define IOERR_INVALID_RPI 0x04
3626#define IOERR_NO_XRI 0x05
3627#define IOERR_ILLEGAL_COMMAND 0x06
3628#define IOERR_XCHG_DROPPED 0x07
3629#define IOERR_ILLEGAL_FIELD 0x08
3630#define IOERR_BAD_CONTINUE 0x09
3631#define IOERR_TOO_MANY_BUFFERS 0x0A
3632#define IOERR_RCV_BUFFER_WAITING 0x0B
3633#define IOERR_NO_CONNECTION 0x0C
3634#define IOERR_TX_DMA_FAILED 0x0D
3635#define IOERR_RX_DMA_FAILED 0x0E
3636#define IOERR_ILLEGAL_FRAME 0x0F
3637#define IOERR_EXTRA_DATA 0x10
3638#define IOERR_NO_RESOURCES 0x11
3639#define IOERR_RESERVED 0x12
3640#define IOERR_ILLEGAL_LENGTH 0x13
3641#define IOERR_UNSUPPORTED_FEATURE 0x14
3642#define IOERR_ABORT_IN_PROGRESS 0x15
3643#define IOERR_ABORT_REQUESTED 0x16
3644#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3645#define IOERR_LOOP_OPEN_FAILURE 0x18
3646#define IOERR_RING_RESET 0x19
3647#define IOERR_LINK_DOWN 0x1A
3648#define IOERR_CORRUPTED_DATA 0x1B
3649#define IOERR_CORRUPTED_RPI 0x1C
3650#define IOERR_OUT_OF_ORDER_DATA 0x1D
3651#define IOERR_OUT_OF_ORDER_ACK 0x1E
3652#define IOERR_DUP_FRAME 0x1F
3653#define IOERR_LINK_CONTROL_FRAME 0x20
3654#define IOERR_BAD_HOST_ADDRESS 0x21
3655#define IOERR_RCV_HDRBUF_WAITING 0x22
3656#define IOERR_MISSING_HDR_BUFFER 0x23
3657#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3658#define IOERR_ABORTMULT_REQUESTED 0x25
3659#define IOERR_BUFFER_SHORTAGE 0x28
3660#define IOERR_DEFAULT 0x29
3661#define IOERR_CNT 0x2A
3662#define IOERR_SLER_FAILURE 0x46
3663#define IOERR_SLER_CMD_RCV_FAILURE 0x47
3664#define IOERR_SLER_REC_RJT_ERR 0x48
3665#define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3666#define IOERR_SLER_SRR_RJT_ERR 0x4A
3667#define IOERR_SLER_RRQ_RJT_ERR 0x4C
3668#define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3669#define IOERR_SLER_ABTS_ERR 0x4E
3670#define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3671#define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3672#define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3673#define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3674#define IOERR_DRVR_MASK 0x100
3675#define IOERR_SLI_DOWN 0x101
3676#define IOERR_SLI_BRESET 0x102
3677#define IOERR_SLI_ABORTED 0x103
3678#define IOERR_PARAM_MASK 0x1ff
3679} PARM_ERR;
3680
3681typedef union {
3682 struct {
3683#ifdef __BIG_ENDIAN_BITFIELD
3684 uint8_t Rctl;
3685 uint8_t Type;
3686 uint8_t Dfctl;
3687 uint8_t Fctl;
3688#else
3689 uint8_t Fctl;
3690 uint8_t Dfctl;
3691 uint8_t Type;
3692 uint8_t Rctl;
3693#endif
3694
3695#define BC 0x02
3696#define SI 0x04
3697#define LA 0x08
3698#define LS 0x80
3699 } hcsw;
3700 uint32_t reserved;
3701} WORD5;
3702
3703
3704typedef struct {
3705 uint32_t reserved[4];
3706 PARM_ERR perr;
3707} GENERIC_RSP;
3708
3709
3710typedef struct {
3711 struct ulp_bde xrsqbde[2];
3712 uint32_t xrsqRo;
3713 WORD5 w5;
3714} XR_SEQ_FIELDS;
3715
3716
3717typedef struct {
3718 struct ulp_bde elsReq;
3719 struct ulp_bde elsRsp;
3720
3721#ifdef __BIG_ENDIAN_BITFIELD
3722 uint32_t word4Rsvd:7;
3723 uint32_t fl:1;
3724 uint32_t myID:24;
3725 uint32_t word5Rsvd:8;
3726 uint32_t remoteID:24;
3727#else
3728 uint32_t myID:24;
3729 uint32_t fl:1;
3730 uint32_t word4Rsvd:7;
3731 uint32_t remoteID:24;
3732 uint32_t word5Rsvd:8;
3733#endif
3734} ELS_REQUEST;
3735
3736
3737typedef struct {
3738 struct ulp_bde elsReq[2];
3739 uint32_t parmRo;
3740
3741#ifdef __BIG_ENDIAN_BITFIELD
3742 uint32_t word5Rsvd:8;
3743 uint32_t remoteID:24;
3744#else
3745 uint32_t remoteID:24;
3746 uint32_t word5Rsvd:8;
3747#endif
3748} RCV_ELS_REQ;
3749
3750
3751typedef struct {
3752 uint32_t rsvd[3];
3753 uint32_t abortType;
3754#define ABORT_TYPE_ABTX 0x00000000
3755#define ABORT_TYPE_ABTS 0x00000001
3756 uint32_t parm;
3757#ifdef __BIG_ENDIAN_BITFIELD
3758 uint16_t abortContextTag;
3759 uint16_t abortIoTag;
3760#else
3761 uint16_t abortIoTag;
3762 uint16_t abortContextTag;
3763#endif
3764} AC_XRI;
3765
3766
3767typedef struct {
3768 uint32_t rsvd[3];
3769 uint32_t abortType;
3770 uint32_t parm;
3771 uint32_t iotag32;
3772} A_MXRI64;
3773
3774
3775typedef struct {
3776 uint32_t rsvd[4];
3777 uint32_t parmRo;
3778#ifdef __BIG_ENDIAN_BITFIELD
3779 uint32_t word5Rsvd:8;
3780 uint32_t remoteID:24;
3781#else
3782 uint32_t remoteID:24;
3783 uint32_t word5Rsvd:8;
3784#endif
3785} GET_RPI;
3786
3787
3788typedef struct {
3789 struct ulp_bde fcpi_cmnd;
3790 struct ulp_bde fcpi_rsp;
3791 uint32_t fcpi_parm;
3792 uint32_t fcpi_XRdy;
3793} FCPI_FIELDS;
3794
3795
3796typedef struct {
3797 struct ulp_bde fcpt_Buffer[2];
3798 uint32_t fcpt_Offset;
3799 uint32_t fcpt_Length;
3800} FCPT_FIELDS;
3801
3802
3803
3804
3805typedef struct {
3806 ULP_BDL bdl;
3807 uint32_t xrsqRo;
3808 WORD5 w5;
3809} XMT_SEQ_FIELDS64;
3810
3811
3812#define xmit_els_remoteID xrsqRo
3813
3814
3815typedef struct {
3816 struct ulp_bde64 rcvBde;
3817 uint32_t rsvd1;
3818 uint32_t xrsqRo;
3819 WORD5 w5;
3820} RCV_SEQ_FIELDS64;
3821
3822
3823typedef struct {
3824 ULP_BDL bdl;
3825#ifdef __BIG_ENDIAN_BITFIELD
3826 uint32_t word4Rsvd:7;
3827 uint32_t fl:1;
3828 uint32_t myID:24;
3829 uint32_t word5Rsvd:8;
3830 uint32_t remoteID:24;
3831#else
3832 uint32_t myID:24;
3833 uint32_t fl:1;
3834 uint32_t word4Rsvd:7;
3835 uint32_t remoteID:24;
3836 uint32_t word5Rsvd:8;
3837#endif
3838} ELS_REQUEST64;
3839
3840
3841typedef struct {
3842 ULP_BDL bdl;
3843 uint32_t xrsqRo;
3844 WORD5 w5;
3845} GEN_REQUEST64;
3846
3847
3848typedef struct {
3849 struct ulp_bde64 elsReq;
3850 uint32_t rcvd1;
3851 uint32_t parmRo;
3852
3853#ifdef __BIG_ENDIAN_BITFIELD
3854 uint32_t word5Rsvd:8;
3855 uint32_t remoteID:24;
3856#else
3857 uint32_t remoteID:24;
3858 uint32_t word5Rsvd:8;
3859#endif
3860} RCV_ELS_REQ64;
3861
3862
3863struct rcv_seq64 {
3864 struct ulp_bde64 elsReq;
3865 uint32_t hbq_1;
3866 uint32_t parmRo;
3867#ifdef __BIG_ENDIAN_BITFIELD
3868 uint32_t rctl:8;
3869 uint32_t type:8;
3870 uint32_t dfctl:8;
3871 uint32_t ls:1;
3872 uint32_t fs:1;
3873 uint32_t rsvd2:3;
3874 uint32_t si:1;
3875 uint32_t bc:1;
3876 uint32_t rsvd3:1;
3877#else
3878 uint32_t rsvd3:1;
3879 uint32_t bc:1;
3880 uint32_t si:1;
3881 uint32_t rsvd2:3;
3882 uint32_t fs:1;
3883 uint32_t ls:1;
3884 uint32_t dfctl:8;
3885 uint32_t type:8;
3886 uint32_t rctl:8;
3887#endif
3888};
3889
3890
3891typedef struct {
3892 ULP_BDL bdl;
3893 uint32_t fcpi_parm;
3894 uint32_t fcpi_XRdy;
3895} FCPI_FIELDS64;
3896
3897
3898typedef struct {
3899 ULP_BDL bdl;
3900 uint32_t fcpt_Offset;
3901 uint32_t fcpt_Length;
3902} FCPT_FIELDS64;
3903
3904
3905typedef struct {
3906 uint32_t rsvd[4];
3907 uint32_t param;
3908#ifdef __BIG_ENDIAN_BITFIELD
3909 uint16_t evt_code;
3910 uint16_t sub_ctxt_tag;
3911#else
3912 uint16_t sub_ctxt_tag;
3913 uint16_t evt_code;
3914#endif
3915} ASYNCSTAT_FIELDS;
3916#define ASYNC_TEMP_WARN 0x100
3917#define ASYNC_TEMP_SAFE 0x101
3918#define ASYNC_STATUS_CN 0x102
3919
3920
3921
3922
3923struct rcv_sli3 {
3924#ifdef __BIG_ENDIAN_BITFIELD
3925 uint16_t ox_id;
3926 uint16_t seq_cnt;
3927
3928 uint16_t vpi;
3929 uint16_t word9Rsvd;
3930#else
3931 uint16_t seq_cnt;
3932 uint16_t ox_id;
3933
3934 uint16_t word9Rsvd;
3935 uint16_t vpi;
3936#endif
3937 uint32_t word10Rsvd;
3938 uint32_t acc_len;
3939 struct ulp_bde64 bde2;
3940};
3941
3942
3943struct lpfc_hbq_entry {
3944 struct ulp_bde64 bde;
3945 uint32_t buffer_tag;
3946};
3947
3948
3949typedef struct {
3950 struct lpfc_hbq_entry buff;
3951 uint32_t rsvd;
3952 uint32_t rsvd1;
3953} QUE_XRI64_CX_FIELDS;
3954
3955struct que_xri64cx_ext_fields {
3956 uint32_t iotag64_low;
3957 uint32_t iotag64_high;
3958 uint32_t ebde_count;
3959 uint32_t rsvd;
3960 struct lpfc_hbq_entry buff[5];
3961};
3962
3963struct sli3_bg_fields {
3964 uint32_t filler[6];
3965 uint32_t bghm;
3966
3967#define BGS_BIDIR_BG_PROF_MASK 0xff000000
3968#define BGS_BIDIR_BG_PROF_SHIFT 24
3969#define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3970#define BGS_BIDIR_ERR_COND_SHIFT 16
3971#define BGS_BG_PROFILE_MASK 0x0000ff00
3972#define BGS_BG_PROFILE_SHIFT 8
3973#define BGS_INVALID_PROF_MASK 0x00000020
3974#define BGS_INVALID_PROF_SHIFT 5
3975#define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3976#define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3977#define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3978#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3979#define BGS_REFTAG_ERR_MASK 0x00000004
3980#define BGS_REFTAG_ERR_SHIFT 2
3981#define BGS_APPTAG_ERR_MASK 0x00000002
3982#define BGS_APPTAG_ERR_SHIFT 1
3983#define BGS_GUARD_ERR_MASK 0x00000001
3984#define BGS_GUARD_ERR_SHIFT 0
3985 uint32_t bgstat;
3986};
3987
3988static inline uint32_t
3989lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3990{
3991 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3992 BGS_BIDIR_BG_PROF_SHIFT;
3993}
3994
3995static inline uint32_t
3996lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3997{
3998 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3999 BGS_BIDIR_ERR_COND_SHIFT;
4000}
4001
4002static inline uint32_t
4003lpfc_bgs_get_bg_prof(uint32_t bgstat)
4004{
4005 return (bgstat & BGS_BG_PROFILE_MASK) >>
4006 BGS_BG_PROFILE_SHIFT;
4007}
4008
4009static inline uint32_t
4010lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4011{
4012 return (bgstat & BGS_INVALID_PROF_MASK) >>
4013 BGS_INVALID_PROF_SHIFT;
4014}
4015
4016static inline uint32_t
4017lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4018{
4019 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4020 BGS_UNINIT_DIF_BLOCK_SHIFT;
4021}
4022
4023static inline uint32_t
4024lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4025{
4026 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4027 BGS_HI_WATER_MARK_PRESENT_SHIFT;
4028}
4029
4030static inline uint32_t
4031lpfc_bgs_get_reftag_err(uint32_t bgstat)
4032{
4033 return (bgstat & BGS_REFTAG_ERR_MASK) >>
4034 BGS_REFTAG_ERR_SHIFT;
4035}
4036
4037static inline uint32_t
4038lpfc_bgs_get_apptag_err(uint32_t bgstat)
4039{
4040 return (bgstat & BGS_APPTAG_ERR_MASK) >>
4041 BGS_APPTAG_ERR_SHIFT;
4042}
4043
4044static inline uint32_t
4045lpfc_bgs_get_guard_err(uint32_t bgstat)
4046{
4047 return (bgstat & BGS_GUARD_ERR_MASK) >>
4048 BGS_GUARD_ERR_SHIFT;
4049}
4050
4051#define LPFC_EXT_DATA_BDE_COUNT 3
4052struct fcp_irw_ext {
4053 uint32_t io_tag64_low;
4054 uint32_t io_tag64_high;
4055#ifdef __BIG_ENDIAN_BITFIELD
4056 uint8_t reserved1;
4057 uint8_t reserved2;
4058 uint8_t reserved3;
4059 uint8_t ebde_count;
4060#else
4061 uint8_t ebde_count;
4062 uint8_t reserved3;
4063 uint8_t reserved2;
4064 uint8_t reserved1;
4065#endif
4066 uint32_t reserved4;
4067 struct ulp_bde64 rbde;
4068 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT];
4069 uint8_t icd[32];
4070};
4071
4072typedef struct _IOCB {
4073 union {
4074 GENERIC_RSP grsp;
4075 XR_SEQ_FIELDS xrseq;
4076 struct ulp_bde cont[3];
4077 RCV_ELS_REQ rcvels;
4078 AC_XRI acxri;
4079 A_MXRI64 amxri;
4080 GET_RPI getrpi;
4081 FCPI_FIELDS fcpi;
4082 FCPT_FIELDS fcpt;
4083
4084
4085
4086 struct ulp_bde64 cont64[2];
4087
4088 ELS_REQUEST64 elsreq64;
4089 GEN_REQUEST64 genreq64;
4090 RCV_ELS_REQ64 rcvels64;
4091 XMT_SEQ_FIELDS64 xseq64;
4092 FCPI_FIELDS64 fcpi64;
4093 FCPT_FIELDS64 fcpt64;
4094 ASYNCSTAT_FIELDS asyncstat;
4095 QUE_XRI64_CX_FIELDS quexri64cx;
4096 struct rcv_seq64 rcvseq64;
4097 struct sli4_bls_rsp bls_rsp;
4098 uint32_t ulpWord[IOCB_WORD_SZ - 2];
4099 } un;
4100 union {
4101 struct {
4102#ifdef __BIG_ENDIAN_BITFIELD
4103 uint16_t ulpContext;
4104 uint16_t ulpIoTag;
4105#else
4106 uint16_t ulpIoTag;
4107 uint16_t ulpContext;
4108#endif
4109 } t1;
4110 struct {
4111#ifdef __BIG_ENDIAN_BITFIELD
4112 uint16_t ulpContext;
4113 uint16_t ulpIoTag1:2;
4114 uint16_t ulpIoTag0:14;
4115#else
4116 uint16_t ulpIoTag0:14;
4117 uint16_t ulpIoTag1:2;
4118 uint16_t ulpContext;
4119#endif
4120 } t2;
4121 } un1;
4122#define ulpContext un1.t1.ulpContext
4123#define ulpIoTag un1.t1.ulpIoTag
4124#define ulpIoTag0 un1.t2.ulpIoTag0
4125
4126#ifdef __BIG_ENDIAN_BITFIELD
4127 uint32_t ulpTimeout:8;
4128 uint32_t ulpXS:1;
4129 uint32_t ulpFCP2Rcvy:1;
4130 uint32_t ulpPU:2;
4131 uint32_t ulpIr:1;
4132 uint32_t ulpClass:3;
4133 uint32_t ulpCommand:8;
4134 uint32_t ulpStatus:4;
4135 uint32_t ulpBdeCount:2;
4136 uint32_t ulpLe:1;
4137 uint32_t ulpOwner:1;
4138#else
4139 uint32_t ulpOwner:1;
4140 uint32_t ulpLe:1;
4141 uint32_t ulpBdeCount:2;
4142 uint32_t ulpStatus:4;
4143 uint32_t ulpCommand:8;
4144 uint32_t ulpClass:3;
4145 uint32_t ulpIr:1;
4146 uint32_t ulpPU:2;
4147 uint32_t ulpFCP2Rcvy:1;
4148 uint32_t ulpXS:1;
4149 uint32_t ulpTimeout:8;
4150#endif
4151
4152 union {
4153 struct rcv_sli3 rcvsli3;
4154
4155
4156 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4157 struct fcp_irw_ext fcp_ext;
4158 uint32_t sli3Words[24];
4159
4160
4161 struct sli3_bg_fields sli3_bg;
4162 } unsli3;
4163
4164#define ulpCt_h ulpXS
4165#define ulpCt_l ulpFCP2Rcvy
4166
4167#define IOCB_FCP 1
4168#define IOCB_IP 2
4169#define PARM_UNUSED 0
4170#define PARM_REL_OFF 1
4171#define PARM_READ_CHECK 2
4172#define PARM_NPIV_DID 3
4173#define CLASS1 0
4174#define CLASS2 1
4175#define CLASS3 2
4176#define CLASS_FCP_INTERMIX 7
4177
4178#define IOSTAT_SUCCESS 0x0
4179#define IOSTAT_FCP_RSP_ERROR 0x1
4180#define IOSTAT_REMOTE_STOP 0x2
4181#define IOSTAT_LOCAL_REJECT 0x3
4182#define IOSTAT_NPORT_RJT 0x4
4183#define IOSTAT_FABRIC_RJT 0x5
4184#define IOSTAT_NPORT_BSY 0x6
4185#define IOSTAT_FABRIC_BSY 0x7
4186#define IOSTAT_INTERMED_RSP 0x8
4187#define IOSTAT_LS_RJT 0x9
4188#define IOSTAT_BA_RJT 0xA
4189#define IOSTAT_RSVD1 0xB
4190#define IOSTAT_RSVD2 0xC
4191#define IOSTAT_RSVD3 0xD
4192#define IOSTAT_RSVD4 0xE
4193#define IOSTAT_NEED_BUFFER 0xF
4194#define IOSTAT_DRIVER_REJECT 0x10
4195#define IOSTAT_DEFAULT 0xF
4196#define IOSTAT_CNT 0x11
4197
4198} IOCB_t;
4199
4200
4201#define SLI1_SLIM_SIZE (4 * 1024)
4202
4203
4204
4205
4206#define SLI2_SLIM_SIZE (64 * 1024)
4207
4208
4209#define MAX_SLI2_IOCB 498
4210#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4211 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4212 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4213
4214
4215#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4216 lpfc_sli_hbq_count())
4217
4218struct lpfc_sli2_slim {
4219 MAILBOX_t mbx;
4220 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4221 PCB_t pcb;
4222 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4223};
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234static inline int
4235lpfc_is_LC_HBA(unsigned short device)
4236{
4237 if ((device == PCI_DEVICE_ID_TFLY) ||
4238 (device == PCI_DEVICE_ID_PFLY) ||
4239 (device == PCI_DEVICE_ID_LP101) ||
4240 (device == PCI_DEVICE_ID_BMID) ||
4241 (device == PCI_DEVICE_ID_BSMB) ||
4242 (device == PCI_DEVICE_ID_ZMID) ||
4243 (device == PCI_DEVICE_ID_ZSMB) ||
4244 (device == PCI_DEVICE_ID_SAT_MID) ||
4245 (device == PCI_DEVICE_ID_SAT_SMB) ||
4246 (device == PCI_DEVICE_ID_RFLY))
4247 return 1;
4248 else
4249 return 0;
4250}
4251
4252
4253
4254
4255
4256static inline int
4257lpfc_error_lost_link(IOCB_t *iocbp)
4258{
4259 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4260 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4261 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4262 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4263}
4264
4265#define MENLO_TRANSPORT_TYPE 0xfe
4266#define MENLO_CONTEXT 0
4267#define MENLO_PU 3
4268#define MENLO_TIMEOUT 30
4269#define SETVAR_MLOMNT 0x103107
4270#define SETVAR_MLORST 0x103007
4271
4272#define BPL_ALIGN_SZ 8
4273