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8#include <linux/clk.h>
9#include <linux/interrupt.h>
10#include <linux/workqueue.h>
11#include <linux/device.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/sysfs.h>
15#include <linux/list.h>
16#include <linux/spi/spi.h>
17#include <linux/regulator/consumer.h>
18#include <linux/err.h>
19#include <linux/module.h>
20#include <asm/div64.h>
21
22#include <linux/iio/iio.h>
23#include <linux/iio/sysfs.h>
24#include "dds.h"
25
26#include "ad9834.h"
27
28
29
30#define AD9834_REG_CMD 0
31#define AD9834_REG_FREQ0 BIT(14)
32#define AD9834_REG_FREQ1 BIT(15)
33#define AD9834_REG_PHASE0 (BIT(15) | BIT(14))
34#define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13))
35
36
37
38#define AD9834_B28 BIT(13)
39#define AD9834_HLB BIT(12)
40#define AD9834_FSEL BIT(11)
41#define AD9834_PSEL BIT(10)
42#define AD9834_PIN_SW BIT(9)
43#define AD9834_RESET BIT(8)
44#define AD9834_SLEEP1 BIT(7)
45#define AD9834_SLEEP12 BIT(6)
46#define AD9834_OPBITEN BIT(5)
47#define AD9834_SIGN_PIB BIT(4)
48#define AD9834_DIV2 BIT(3)
49#define AD9834_MODE BIT(1)
50
51#define AD9834_FREQ_BITS 28
52#define AD9834_PHASE_BITS 12
53
54#define RES_MASK(bits) (BIT(bits) - 1)
55
56
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68
69
70struct ad9834_state {
71 struct spi_device *spi;
72 struct clk *mclk;
73 unsigned short control;
74 unsigned short devid;
75 struct spi_transfer xfer;
76 struct spi_message msg;
77 struct spi_transfer freq_xfer[2];
78 struct spi_message freq_msg;
79 struct mutex lock;
80
81
82
83
84
85 __be16 data ____cacheline_aligned;
86 __be16 freq_data[2];
87};
88
89
90
91
92
93enum ad9834_supported_device_ids {
94 ID_AD9833,
95 ID_AD9834,
96 ID_AD9837,
97 ID_AD9838,
98};
99
100static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout)
101{
102 unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS);
103
104 do_div(freqreg, mclk);
105 return freqreg;
106}
107
108static int ad9834_write_frequency(struct ad9834_state *st,
109 unsigned long addr, unsigned long fout)
110{
111 unsigned long clk_freq;
112 unsigned long regval;
113
114 clk_freq = clk_get_rate(st->mclk);
115
116 if (fout > (clk_freq / 2))
117 return -EINVAL;
118
119 regval = ad9834_calc_freqreg(clk_freq, fout);
120
121 st->freq_data[0] = cpu_to_be16(addr | (regval &
122 RES_MASK(AD9834_FREQ_BITS / 2)));
123 st->freq_data[1] = cpu_to_be16(addr | ((regval >>
124 (AD9834_FREQ_BITS / 2)) &
125 RES_MASK(AD9834_FREQ_BITS / 2)));
126
127 return spi_sync(st->spi, &st->freq_msg);
128}
129
130static int ad9834_write_phase(struct ad9834_state *st,
131 unsigned long addr, unsigned long phase)
132{
133 if (phase > BIT(AD9834_PHASE_BITS))
134 return -EINVAL;
135 st->data = cpu_to_be16(addr | phase);
136
137 return spi_sync(st->spi, &st->msg);
138}
139
140static ssize_t ad9834_write(struct device *dev,
141 struct device_attribute *attr,
142 const char *buf,
143 size_t len)
144{
145 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
146 struct ad9834_state *st = iio_priv(indio_dev);
147 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
148 int ret;
149 unsigned long val;
150
151 ret = kstrtoul(buf, 10, &val);
152 if (ret)
153 return ret;
154
155 mutex_lock(&st->lock);
156 switch ((u32)this_attr->address) {
157 case AD9834_REG_FREQ0:
158 case AD9834_REG_FREQ1:
159 ret = ad9834_write_frequency(st, this_attr->address, val);
160 break;
161 case AD9834_REG_PHASE0:
162 case AD9834_REG_PHASE1:
163 ret = ad9834_write_phase(st, this_attr->address, val);
164 break;
165 case AD9834_OPBITEN:
166 if (st->control & AD9834_MODE) {
167 ret = -EINVAL;
168 break;
169 }
170
171 if (val)
172 st->control |= AD9834_OPBITEN;
173 else
174 st->control &= ~AD9834_OPBITEN;
175
176 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
177 ret = spi_sync(st->spi, &st->msg);
178 break;
179 case AD9834_PIN_SW:
180 if (val)
181 st->control |= AD9834_PIN_SW;
182 else
183 st->control &= ~AD9834_PIN_SW;
184 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
185 ret = spi_sync(st->spi, &st->msg);
186 break;
187 case AD9834_FSEL:
188 case AD9834_PSEL:
189 if (!val) {
190 st->control &= ~(this_attr->address | AD9834_PIN_SW);
191 } else if (val == 1) {
192 st->control |= this_attr->address;
193 st->control &= ~AD9834_PIN_SW;
194 } else {
195 ret = -EINVAL;
196 break;
197 }
198 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
199 ret = spi_sync(st->spi, &st->msg);
200 break;
201 case AD9834_RESET:
202 if (val)
203 st->control &= ~AD9834_RESET;
204 else
205 st->control |= AD9834_RESET;
206
207 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
208 ret = spi_sync(st->spi, &st->msg);
209 break;
210 default:
211 ret = -ENODEV;
212 }
213 mutex_unlock(&st->lock);
214
215 return ret ? ret : len;
216}
217
218static ssize_t ad9834_store_wavetype(struct device *dev,
219 struct device_attribute *attr,
220 const char *buf,
221 size_t len)
222{
223 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
224 struct ad9834_state *st = iio_priv(indio_dev);
225 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
226 int ret = 0;
227 bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837);
228
229 mutex_lock(&st->lock);
230
231 switch ((u32)this_attr->address) {
232 case 0:
233 if (sysfs_streq(buf, "sine")) {
234 st->control &= ~AD9834_MODE;
235 if (is_ad9833_7)
236 st->control &= ~AD9834_OPBITEN;
237 } else if (sysfs_streq(buf, "triangle")) {
238 if (is_ad9833_7) {
239 st->control &= ~AD9834_OPBITEN;
240 st->control |= AD9834_MODE;
241 } else if (st->control & AD9834_OPBITEN) {
242 ret = -EINVAL;
243 } else {
244 st->control |= AD9834_MODE;
245 }
246 } else if (is_ad9833_7 && sysfs_streq(buf, "square")) {
247 st->control &= ~AD9834_MODE;
248 st->control |= AD9834_OPBITEN;
249 } else {
250 ret = -EINVAL;
251 }
252
253 break;
254 case 1:
255 if (sysfs_streq(buf, "square") &&
256 !(st->control & AD9834_MODE)) {
257 st->control &= ~AD9834_MODE;
258 st->control |= AD9834_OPBITEN;
259 } else {
260 ret = -EINVAL;
261 }
262 break;
263 default:
264 ret = -EINVAL;
265 break;
266 }
267
268 if (!ret) {
269 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
270 ret = spi_sync(st->spi, &st->msg);
271 }
272 mutex_unlock(&st->lock);
273
274 return ret ? ret : len;
275}
276
277static
278ssize_t ad9834_show_out0_wavetype_available(struct device *dev,
279 struct device_attribute *attr,
280 char *buf)
281{
282 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
283 struct ad9834_state *st = iio_priv(indio_dev);
284 char *str;
285
286 if (st->devid == ID_AD9833 || st->devid == ID_AD9837)
287 str = "sine triangle square";
288 else if (st->control & AD9834_OPBITEN)
289 str = "sine";
290 else
291 str = "sine triangle";
292
293 return sprintf(buf, "%s\n", str);
294}
295
296static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444,
297 ad9834_show_out0_wavetype_available, NULL, 0);
298
299static
300ssize_t ad9834_show_out1_wavetype_available(struct device *dev,
301 struct device_attribute *attr,
302 char *buf)
303{
304 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
305 struct ad9834_state *st = iio_priv(indio_dev);
306 char *str;
307
308 if (st->control & AD9834_MODE)
309 str = "";
310 else
311 str = "square";
312
313 return sprintf(buf, "%s\n", str);
314}
315
316static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444,
317 ad9834_show_out1_wavetype_available, NULL, 0);
318
319
320
321
322
323static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9834_write, AD9834_REG_FREQ0);
324static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9834_write, AD9834_REG_FREQ1);
325static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9834_write, AD9834_FSEL);
326static IIO_CONST_ATTR_FREQ_SCALE(0, "1");
327
328static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9834_write, AD9834_REG_PHASE0);
329static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9834_write, AD9834_REG_PHASE1);
330static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, ad9834_write, AD9834_PSEL);
331static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808");
332
333static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
334 ad9834_write, AD9834_PIN_SW);
335static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, ad9834_write, AD9834_RESET);
336static IIO_DEV_ATTR_OUTY_ENABLE(0, 1, 0200, NULL,
337 ad9834_write, AD9834_OPBITEN);
338static IIO_DEV_ATTR_OUT_WAVETYPE(0, 0, ad9834_store_wavetype, 0);
339static IIO_DEV_ATTR_OUT_WAVETYPE(0, 1, ad9834_store_wavetype, 1);
340
341static struct attribute *ad9834_attributes[] = {
342 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
343 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
344 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
345 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
346 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
347 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
348 &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
349 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
350 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
351 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
352 &iio_dev_attr_out_altvoltage0_out1_enable.dev_attr.attr,
353 &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
354 &iio_dev_attr_out_altvoltage0_out1_wavetype.dev_attr.attr,
355 &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
356 &iio_dev_attr_out_altvoltage0_out1_wavetype_available.dev_attr.attr,
357 NULL,
358};
359
360static struct attribute *ad9833_attributes[] = {
361 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
362 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
363 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
364 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
365 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
366 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
367 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
368 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
369 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
370 &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
371 &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
372 NULL,
373};
374
375static const struct attribute_group ad9834_attribute_group = {
376 .attrs = ad9834_attributes,
377};
378
379static const struct attribute_group ad9833_attribute_group = {
380 .attrs = ad9833_attributes,
381};
382
383static const struct iio_info ad9834_info = {
384 .attrs = &ad9834_attribute_group,
385};
386
387static const struct iio_info ad9833_info = {
388 .attrs = &ad9833_attribute_group,
389};
390
391static void ad9834_disable_reg(void *data)
392{
393 struct regulator *reg = data;
394
395 regulator_disable(reg);
396}
397
398static void ad9834_disable_clk(void *data)
399{
400 struct clk *clk = data;
401
402 clk_disable_unprepare(clk);
403}
404
405static int ad9834_probe(struct spi_device *spi)
406{
407 struct ad9834_state *st;
408 struct iio_dev *indio_dev;
409 struct regulator *reg;
410 int ret;
411
412 reg = devm_regulator_get(&spi->dev, "avdd");
413 if (IS_ERR(reg))
414 return PTR_ERR(reg);
415
416 ret = regulator_enable(reg);
417 if (ret) {
418 dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
419 return ret;
420 }
421
422 ret = devm_add_action_or_reset(&spi->dev, ad9834_disable_reg, reg);
423 if (ret)
424 return ret;
425
426 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
427 if (!indio_dev) {
428 ret = -ENOMEM;
429 return ret;
430 }
431 st = iio_priv(indio_dev);
432 mutex_init(&st->lock);
433 st->mclk = devm_clk_get(&spi->dev, NULL);
434 if (IS_ERR(st->mclk)) {
435 ret = PTR_ERR(st->mclk);
436 return ret;
437 }
438
439 ret = clk_prepare_enable(st->mclk);
440 if (ret) {
441 dev_err(&spi->dev, "Failed to enable master clock\n");
442 return ret;
443 }
444
445 ret = devm_add_action_or_reset(&spi->dev, ad9834_disable_clk, st->mclk);
446 if (ret)
447 return ret;
448
449 st->spi = spi;
450 st->devid = spi_get_device_id(spi)->driver_data;
451 indio_dev->name = spi_get_device_id(spi)->name;
452 switch (st->devid) {
453 case ID_AD9833:
454 case ID_AD9837:
455 indio_dev->info = &ad9833_info;
456 break;
457 default:
458 indio_dev->info = &ad9834_info;
459 break;
460 }
461 indio_dev->modes = INDIO_DIRECT_MODE;
462
463
464
465 st->xfer.tx_buf = &st->data;
466 st->xfer.len = 2;
467
468 spi_message_init(&st->msg);
469 spi_message_add_tail(&st->xfer, &st->msg);
470
471 st->freq_xfer[0].tx_buf = &st->freq_data[0];
472 st->freq_xfer[0].len = 2;
473 st->freq_xfer[0].cs_change = 1;
474 st->freq_xfer[1].tx_buf = &st->freq_data[1];
475 st->freq_xfer[1].len = 2;
476
477 spi_message_init(&st->freq_msg);
478 spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
479 spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
480
481 st->control = AD9834_B28 | AD9834_RESET;
482 st->control |= AD9834_DIV2;
483
484 if (st->devid == ID_AD9834)
485 st->control |= AD9834_SIGN_PIB;
486
487 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
488 ret = spi_sync(st->spi, &st->msg);
489 if (ret) {
490 dev_err(&spi->dev, "device init failed\n");
491 return ret;
492 }
493
494 ret = ad9834_write_frequency(st, AD9834_REG_FREQ0, 1000000);
495 if (ret)
496 return ret;
497
498 ret = ad9834_write_frequency(st, AD9834_REG_FREQ1, 5000000);
499 if (ret)
500 return ret;
501
502 ret = ad9834_write_phase(st, AD9834_REG_PHASE0, 512);
503 if (ret)
504 return ret;
505
506 ret = ad9834_write_phase(st, AD9834_REG_PHASE1, 1024);
507 if (ret)
508 return ret;
509
510 return devm_iio_device_register(&spi->dev, indio_dev);
511}
512
513static const struct spi_device_id ad9834_id[] = {
514 {"ad9833", ID_AD9833},
515 {"ad9834", ID_AD9834},
516 {"ad9837", ID_AD9837},
517 {"ad9838", ID_AD9838},
518 {}
519};
520MODULE_DEVICE_TABLE(spi, ad9834_id);
521
522static const struct of_device_id ad9834_of_match[] = {
523 {.compatible = "adi,ad9833"},
524 {.compatible = "adi,ad9834"},
525 {.compatible = "adi,ad9837"},
526 {.compatible = "adi,ad9838"},
527 {}
528};
529
530MODULE_DEVICE_TABLE(of, ad9834_of_match);
531
532static struct spi_driver ad9834_driver = {
533 .driver = {
534 .name = "ad9834",
535 .of_match_table = ad9834_of_match
536 },
537 .probe = ad9834_probe,
538 .id_table = ad9834_id,
539};
540module_spi_driver(ad9834_driver);
541
542MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
543MODULE_DESCRIPTION("Analog Devices AD9833/AD9834/AD9837/AD9838 DDS");
544MODULE_LICENSE("GPL v2");
545
