LXR linux/drivers/staging/kpc2000/kpc2000

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * KP2000 SPI controller driver
   4 *
   5 * Copyright (C) 2014-2018 Daktronics
   6 * Author: Matt Sickler <matt.sickler@daktronics.com>
   7 * Very loosely based on spi-omap2-mcspi.c
   8 */
   9
  10#include <linux/kernel.h>
  11#include <linux/init.h>
  12#include <linux/interrupt.h>
  13#include <linux/io-64-nonatomic-lo-hi.h>
  14#include <linux/module.h>
  15#include <linux/device.h>
  16#include <linux/delay.h>
  17#include <linux/platform_device.h>
  18#include <linux/err.h>
  19#include <linux/clk.h>
  20#include <linux/io.h>
  21#include <linux/slab.h>
  22#include <linux/pm_runtime.h>
  23#include <linux/of.h>
  24#include <linux/of_device.h>
  25#include <linux/gcd.h>
  26#include <linux/spi/spi.h>
  27#include <linux/spi/flash.h>
  28#include <linux/mtd/partitions.h>
  29
  30#include "kpc.h"
  31
  32static struct mtd_partition p2kr0_spi0_parts[] = {
  33        { .name = "SLOT_0",     .size = 7798784,                .offset = 0,                },
  34        { .name = "SLOT_1",     .size = 7798784,                .offset = MTDPART_OFS_NXTBLK},
  35        { .name = "SLOT_2",     .size = 7798784,                .offset = MTDPART_OFS_NXTBLK},
  36        { .name = "SLOT_3",     .size = 7798784,                .offset = MTDPART_OFS_NXTBLK},
  37        { .name = "CS0_EXTRA",  .size = MTDPART_SIZ_FULL,       .offset = MTDPART_OFS_NXTBLK},
  38};
  39
  40static struct mtd_partition p2kr0_spi1_parts[] = {
  41        { .name = "SLOT_4",     .size = 7798784,                .offset = 0,                },
  42        { .name = "SLOT_5",     .size = 7798784,                .offset = MTDPART_OFS_NXTBLK},
  43        { .name = "SLOT_6",     .size = 7798784,                .offset = MTDPART_OFS_NXTBLK},
  44        { .name = "SLOT_7",     .size = 7798784,                .offset = MTDPART_OFS_NXTBLK},
  45        { .name = "CS1_EXTRA",  .size = MTDPART_SIZ_FULL,       .offset = MTDPART_OFS_NXTBLK},
  46};
  47
  48static struct flash_platform_data p2kr0_spi0_pdata = {
  49        .name =         "SPI0",
  50        .nr_parts =     ARRAY_SIZE(p2kr0_spi0_parts),
  51        .parts =        p2kr0_spi0_parts,
  52};
  53
  54static struct flash_platform_data p2kr0_spi1_pdata = {
  55        .name =         "SPI1",
  56        .nr_parts =     ARRAY_SIZE(p2kr0_spi1_parts),
  57        .parts =        p2kr0_spi1_parts,
  58};
  59
  60static struct spi_board_info p2kr0_board_info[] = {
  61        {
  62                .modalias =             "n25q256a11",
  63                .bus_num =              1,
  64                .chip_select =          0,
  65                .mode =                 SPI_MODE_0,
  66                .platform_data =        &p2kr0_spi0_pdata
  67        },
  68        {
  69                .modalias =             "n25q256a11",
  70                .bus_num =              1,
  71                .chip_select =          1,
  72                .mode =                 SPI_MODE_0,
  73                .platform_data =        &p2kr0_spi1_pdata
  74        },
  75};
  76
  77/***************
  78 * SPI Defines *
  79 ***************/
  80#define KP_SPI_REG_CONFIG 0x0 /* 0x00 */
  81#define KP_SPI_REG_STATUS 0x1 /* 0x08 */
  82#define KP_SPI_REG_FFCTRL 0x2 /* 0x10 */
  83#define KP_SPI_REG_TXDATA 0x3 /* 0x18 */
  84#define KP_SPI_REG_RXDATA 0x4 /* 0x20 */
  85
  86#define KP_SPI_CLK           48000000
  87#define KP_SPI_MAX_FIFODEPTH 64
  88#define KP_SPI_MAX_FIFOWCNT  0xFFFF
  89
  90#define KP_SPI_REG_CONFIG_TRM_TXRX 0
  91#define KP_SPI_REG_CONFIG_TRM_RX   1
  92#define KP_SPI_REG_CONFIG_TRM_TX   2
  93
  94#define KP_SPI_REG_STATUS_RXS   0x01
  95#define KP_SPI_REG_STATUS_TXS   0x02
  96#define KP_SPI_REG_STATUS_EOT   0x04
  97#define KP_SPI_REG_STATUS_TXFFE 0x10
  98#define KP_SPI_REG_STATUS_TXFFF 0x20
  99#define KP_SPI_REG_STATUS_RXFFE 0x40
 100#define KP_SPI_REG_STATUS_RXFFF 0x80
 101
 102/******************
 103 * SPI Structures *
 104 ******************/
 105struct kp_spi {
 106        struct spi_master  *master;
 107        u64 __iomem        *base;
 108        struct device      *dev;
 109};
 110
 111struct kp_spi_controller_state {
 112        void __iomem   *base;
 113        s64             conf_cache;
 114};
 115
 116union kp_spi_config {
 117        /* use this to access individual elements */
 118        struct __packed spi_config_bitfield {
 119                unsigned int pha       : 1; /* spim_clk Phase      */
 120                unsigned int pol       : 1; /* spim_clk Polarity   */
 121                unsigned int epol      : 1; /* spim_csx Polarity   */
 122                unsigned int dpe       : 1; /* Transmission Enable */
 123                unsigned int wl        : 5; /* Word Length         */
 124                unsigned int           : 3;
 125                unsigned int trm       : 2; /* TxRx Mode           */
 126                unsigned int cs        : 4; /* Chip Select         */
 127                unsigned int wcnt      : 7; /* Word Count          */
 128                unsigned int ffen      : 1; /* FIFO Enable         */
 129                unsigned int spi_en    : 1; /* SPI Enable          */
 130                unsigned int           : 5;
 131        } bitfield;
 132        /* use this to grab the whole register */
 133        u32 reg;
 134};
 135
 136union kp_spi_status {
 137        struct __packed spi_status_bitfield {
 138                unsigned int rx    :  1; /* Rx Status       */
 139                unsigned int tx    :  1; /* Tx Status       */
 140                unsigned int eo    :  1; /* End of Transfer */
 141                unsigned int       :  1;
 142                unsigned int txffe :  1; /* Tx FIFO Empty   */
 143                unsigned int txfff :  1; /* Tx FIFO Full    */
 144                unsigned int rxffe :  1; /* Rx FIFO Empty   */
 145                unsigned int rxfff :  1; /* Rx FIFO Full    */
 146                unsigned int       : 24;
 147        } bitfield;
 148        u32 reg;
 149};
 150
 151union kp_spi_ffctrl {
 152        struct __packed spi_ffctrl_bitfield {
 153                unsigned int ffstart :  1; /* FIFO Start */
 154                unsigned int         : 31;
 155        } bitfield;
 156        u32 reg;
 157};
 158
 159/***************
 160 * SPI Helpers *
 161 ***************/
 162        static inline u64
 163kp_spi_read_reg(struct kp_spi_controller_state *cs, int idx)
 164{
 165        u64 __iomem *addr = cs->base;
 166
 167        addr += idx;
 168        if ((idx == KP_SPI_REG_CONFIG) && (cs->conf_cache >= 0))
 169                return cs->conf_cache;
 170
 171        return readq(addr);
 172}
 173
 174        static inline void
 175kp_spi_write_reg(struct kp_spi_controller_state *cs, int idx, u64 val)
 176{
 177        u64 __iomem *addr = cs->base;
 178
 179        addr += idx;
 180        writeq(val, addr);
 181        if (idx == KP_SPI_REG_CONFIG)
 182                cs->conf_cache = val;
 183}
 184
 185        static int
 186kp_spi_wait_for_reg_bit(struct kp_spi_controller_state *cs, int idx,
 187                        unsigned long bit)
 188{
 189        unsigned long timeout;
 190
 191        timeout = jiffies + msecs_to_jiffies(1000);
 192        while (!(kp_spi_read_reg(cs, idx) & bit)) {
 193                if (time_after(jiffies, timeout)) {
 194                        if (!(kp_spi_read_reg(cs, idx) & bit))
 195                                return -ETIMEDOUT;
 196                        else
 197                                return 0;
 198                }
 199                cpu_relax();
 200        }
 201        return 0;
 202}
 203
 204        static unsigned
 205kp_spi_txrx_pio(struct spi_device *spidev, struct spi_transfer *transfer)
 206{
 207        struct kp_spi_controller_state *cs = spidev->controller_state;
 208        unsigned int count = transfer->len;
 209        unsigned int c = count;
 210
 211        int i;
 212        int res;
 213        u8 *rx       = transfer->rx_buf;
 214        const u8 *tx = transfer->tx_buf;
 215        int processed = 0;
 216
 217        if (tx) {
 218                for (i = 0 ; i < c ; i++) {
 219                        char val = *tx++;
 220
 221                        res = kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
 222                                                      KP_SPI_REG_STATUS_TXS);
 223                        if (res < 0)
 224                                goto out;
 225
 226                        kp_spi_write_reg(cs, KP_SPI_REG_TXDATA, val);
 227                        processed++;
 228                }
 229        } else if (rx) {
 230                for (i = 0 ; i < c ; i++) {
 231                        char test = 0;
 232
 233                        kp_spi_write_reg(cs, KP_SPI_REG_TXDATA, 0x00);
 234                        res = kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
 235                                                      KP_SPI_REG_STATUS_RXS);
 236                        if (res < 0)
 237                                goto out;
 238
 239                        test = kp_spi_read_reg(cs, KP_SPI_REG_RXDATA);
 240                        *rx++ = test;
 241                        processed++;
 242                }
 243        }
 244
 245        if (kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
 246                                    KP_SPI_REG_STATUS_EOT) < 0) {
 247                //TODO: Figure out how to abort transaction??
 248                //Ths has never happened in practice though...
 249        }
 250
 251out:
 252        return processed;
 253}
 254
 255/*****************
 256 * SPI Functions *
 257 *****************/
 258        static int
 259kp_spi_setup(struct spi_device *spidev)
 260{
 261        union kp_spi_config sc;
 262        struct kp_spi *kpspi = spi_master_get_devdata(spidev->master);
 263        struct kp_spi_controller_state *cs;
 264
 265        /* setup controller state */
 266        cs = spidev->controller_state;
 267        if (!cs) {
 268                cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 269                if (!cs)
 270                        return -ENOMEM;
 271                cs->base = kpspi->base;
 272                cs->conf_cache = -1;
 273                spidev->controller_state = cs;
 274        }
 275
 276        /* set config register */
 277        sc.bitfield.wl = spidev->bits_per_word - 1;
 278        sc.bitfield.cs = spidev->chip_select;
 279        sc.bitfield.spi_en = 0;
 280        sc.bitfield.trm = 0;
 281        sc.bitfield.ffen = 0;
 282        kp_spi_write_reg(spidev->controller_state, KP_SPI_REG_CONFIG, sc.reg);
 283        return 0;
 284}
 285
 286        static int
 287kp_spi_transfer_one_message(struct spi_master *master, struct spi_message *m)
 288{
 289        struct kp_spi_controller_state *cs;
 290        struct spi_device   *spidev;
 291        struct kp_spi       *kpspi;
 292        struct spi_transfer *transfer;
 293        union kp_spi_config sc;
 294        int status = 0;
 295
 296        spidev = m->spi;
 297        kpspi = spi_master_get_devdata(master);
 298        m->actual_length = 0;
 299        m->status = 0;
 300
 301        cs = spidev->controller_state;
 302
 303        /* reject invalid messages and transfers */
 304        if (list_empty(&m->transfers))
 305                return -EINVAL;
 306
 307        /* validate input */
 308        list_for_each_entry(transfer, &m->transfers, transfer_list) {
 309                const void *tx_buf = transfer->tx_buf;
 310                void       *rx_buf = transfer->rx_buf;
 311                unsigned int len = transfer->len;
 312
 313                if (transfer->speed_hz > KP_SPI_CLK ||
 314                    (len && !(rx_buf || tx_buf))) {
 315                        dev_dbg(kpspi->dev, "  transfer: %d Hz, %d %s%s, %d bpw\n",
 316                                transfer->speed_hz,
 317                                len,
 318                                tx_buf ? "tx" : "",
 319                                rx_buf ? "rx" : "",
 320                                transfer->bits_per_word);
 321                        dev_dbg(kpspi->dev, "  transfer -EINVAL\n");
 322                        return -EINVAL;
 323                }
 324                if (transfer->speed_hz &&
 325                    transfer->speed_hz < (KP_SPI_CLK >> 15)) {
 326                        dev_dbg(kpspi->dev, "speed_hz %d below minimum %d Hz\n",
 327                                transfer->speed_hz,
 328                                KP_SPI_CLK >> 15);
 329                        dev_dbg(kpspi->dev, "  speed_hz -EINVAL\n");
 330                        return -EINVAL;
 331                }
 332        }
 333
 334        /* assert chip select to start the sequence*/
 335        sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
 336        sc.bitfield.spi_en = 1;
 337        kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
 338
 339        /* work */
 340        if (kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
 341                                    KP_SPI_REG_STATUS_EOT) < 0) {
 342                dev_info(kpspi->dev, "EOT timed out\n");
 343                goto out;
 344        }
 345
 346        /* do the transfers for this message */
 347        list_for_each_entry(transfer, &m->transfers, transfer_list) {
 348                if (!transfer->tx_buf && !transfer->rx_buf &&
 349                    transfer->len) {
 350                        status = -EINVAL;
 351                        goto error;
 352                }
 353
 354                /* transfer */
 355                if (transfer->len) {
 356                        unsigned int word_len = spidev->bits_per_word;
 357                        unsigned int count;
 358
 359                        /* set up the transfer... */
 360                        sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
 361
 362                        /* ...direction */
 363                        if (transfer->tx_buf)
 364                                sc.bitfield.trm = KP_SPI_REG_CONFIG_TRM_TX;
 365                        else if (transfer->rx_buf)
 366                                sc.bitfield.trm = KP_SPI_REG_CONFIG_TRM_RX;
 367
 368                        /* ...word length */
 369                        if (transfer->bits_per_word)
 370                                word_len = transfer->bits_per_word;
 371                        sc.bitfield.wl = word_len - 1;
 372
 373                        /* ...chip select */
 374                        sc.bitfield.cs = spidev->chip_select;
 375
 376                        /* ...and write the new settings */
 377                        kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
 378
 379                        /* do the transfer */
 380                        count = kp_spi_txrx_pio(spidev, transfer);
 381                        m->actual_length += count;
 382
 383                        if (count != transfer->len) {
 384                                status = -EIO;
 385                                goto error;
 386                        }
 387                }
 388
 389                if (transfer->delay.value)
 390                        ndelay(spi_delay_to_ns(&transfer->delay, transfer));
 391        }
 392
 393        /* de-assert chip select to end the sequence */
 394        sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
 395        sc.bitfield.spi_en = 0;
 396        kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
 397
 398out:
 399        /* done work */
 400        spi_finalize_current_message(master);
 401        return 0;
 402
 403error:
 404        m->status = status;
 405        return status;
 406}
 407
 408        static void
 409kp_spi_cleanup(struct spi_device *spidev)
 410{
 411        struct kp_spi_controller_state *cs = spidev->controller_state;
 412
 413        kfree(cs);
 414}
 415
 416/******************
 417 * Probe / Remove *
 418 ******************/
 419        static int
 420kp_spi_probe(struct platform_device *pldev)
 421{
 422        struct kpc_core_device_platdata *drvdata;
 423        struct spi_master *master;
 424        struct kp_spi *kpspi;
 425        struct resource *r;
 426        int status = 0;
 427        int i;
 428
 429        drvdata = pldev->dev.platform_data;
 430        if (!drvdata) {
 431                dev_err(&pldev->dev, "%s: platform_data is NULL\n", __func__);
 432                return -ENODEV;
 433        }
 434
 435        master = spi_alloc_master(&pldev->dev, sizeof(struct kp_spi));
 436        if (!master) {
 437                dev_err(&pldev->dev, "%s: master allocation failed\n",
 438                        __func__);
 439                return -ENOMEM;
 440        }
 441
 442        /* set up the spi functions */
 443        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 444        master->bits_per_word_mask = (unsigned int)SPI_BPW_RANGE_MASK(4, 32);
 445        master->setup = kp_spi_setup;
 446        master->transfer_one_message = kp_spi_transfer_one_message;
 447        master->cleanup = kp_spi_cleanup;
 448
 449        platform_set_drvdata(pldev, master);
 450
 451        kpspi = spi_master_get_devdata(master);
 452        kpspi->master = master;
 453        kpspi->dev = &pldev->dev;
 454
 455        master->num_chipselect = 4;
 456        if (pldev->id != -1)
 457                master->bus_num = pldev->id;
 458
 459        r = platform_get_resource(pldev, IORESOURCE_MEM, 0);
 460        if (!r) {
 461                dev_err(&pldev->dev, "%s: Unable to get platform resources\n",
 462                        __func__);
 463                status = -ENODEV;
 464                goto free_master;
 465        }
 466
 467        kpspi->base = devm_ioremap(&pldev->dev, r->start,
 468                                   resource_size(r));
 469
 470        status = spi_register_master(master);
 471        if (status < 0) {
 472                dev_err(&pldev->dev, "Unable to register SPI device\n");
 473                goto free_master;
 474        }
 475
 476        /* register the slave boards */
 477#define NEW_SPI_DEVICE_FROM_BOARD_INFO_TABLE(table) \
 478        for (i = 0 ; i < ARRAY_SIZE(table) ; i++) { \
 479                spi_new_device(master, &table[i]); \
 480        }
 481
 482        switch ((drvdata->card_id & 0xFFFF0000) >> 16) {
 483        case PCI_DEVICE_ID_DAKTRONICS_KADOKA_P2KR0:
 484                NEW_SPI_DEVICE_FROM_BOARD_INFO_TABLE(p2kr0_board_info);
 485                break;
 486        default:
 487                dev_err(&pldev->dev, "Unknown hardware, cant know what partition table to use!\n");
 488                goto free_master;
 489        }
 490
 491        return status;
 492
 493free_master:
 494        spi_master_put(master);
 495        return status;
 496}
 497
 498        static int
 499kp_spi_remove(struct platform_device *pldev)
 500{
 501        struct spi_master *master = platform_get_drvdata(pldev);
 502
 503        spi_unregister_master(master);
 504        return 0;
 505}
 506
 507static struct platform_driver kp_spi_driver = {
 508        .driver = {
 509                .name =     KP_DRIVER_NAME_SPI,
 510        },
 511        .probe =    kp_spi_probe,
 512        .remove =   kp_spi_remove,
 513};
 514
 515module_platform_driver(kp_spi_driver);
 516MODULE_LICENSE("GPL");
 517MODULE_ALIAS("platform:kp_spi");
 518