LXR linux/drivers/tty/serial/stm32-usart.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) Maxime Coquelin 2015
   4 * Copyright (C) STMicroelectronics SA 2017
   5 * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6 *           Gerald Baeza <gerald_baeza@yahoo.fr>
   7 */
   8
   9#define DRIVER_NAME "stm32-usart"
  10
  11struct stm32_usart_offsets {
  12        u8 cr1;
  13        u8 cr2;
  14        u8 cr3;
  15        u8 brr;
  16        u8 gtpr;
  17        u8 rtor;
  18        u8 rqr;
  19        u8 isr;
  20        u8 icr;
  21        u8 rdr;
  22        u8 tdr;
  23};
  24
  25struct stm32_usart_config {
  26        u8 uart_enable_bit; /* USART_CR1_UE */
  27        bool has_7bits_data;
  28        bool has_swap;
  29        bool has_wakeup;
  30        bool has_fifo;
  31        int fifosize;
  32};
  33
  34struct stm32_usart_info {
  35        struct stm32_usart_offsets ofs;
  36        struct stm32_usart_config cfg;
  37};
  38
  39#define UNDEF_REG 0xff
  40
  41/* Register offsets */
  42struct stm32_usart_info stm32f4_info = {
  43        .ofs = {
  44                .isr    = 0x00,
  45                .rdr    = 0x04,
  46                .tdr    = 0x04,
  47                .brr    = 0x08,
  48                .cr1    = 0x0c,
  49                .cr2    = 0x10,
  50                .cr3    = 0x14,
  51                .gtpr   = 0x18,
  52                .rtor   = UNDEF_REG,
  53                .rqr    = UNDEF_REG,
  54                .icr    = UNDEF_REG,
  55        },
  56        .cfg = {
  57                .uart_enable_bit = 13,
  58                .has_7bits_data = false,
  59                .fifosize = 1,
  60        }
  61};
  62
  63struct stm32_usart_info stm32f7_info = {
  64        .ofs = {
  65                .cr1    = 0x00,
  66                .cr2    = 0x04,
  67                .cr3    = 0x08,
  68                .brr    = 0x0c,
  69                .gtpr   = 0x10,
  70                .rtor   = 0x14,
  71                .rqr    = 0x18,
  72                .isr    = 0x1c,
  73                .icr    = 0x20,
  74                .rdr    = 0x24,
  75                .tdr    = 0x28,
  76        },
  77        .cfg = {
  78                .uart_enable_bit = 0,
  79                .has_7bits_data = true,
  80                .has_swap = true,
  81                .fifosize = 1,
  82        }
  83};
  84
  85struct stm32_usart_info stm32h7_info = {
  86        .ofs = {
  87                .cr1    = 0x00,
  88                .cr2    = 0x04,
  89                .cr3    = 0x08,
  90                .brr    = 0x0c,
  91                .gtpr   = 0x10,
  92                .rtor   = 0x14,
  93                .rqr    = 0x18,
  94                .isr    = 0x1c,
  95                .icr    = 0x20,
  96                .rdr    = 0x24,
  97                .tdr    = 0x28,
  98        },
  99        .cfg = {
 100                .uart_enable_bit = 0,
 101                .has_7bits_data = true,
 102                .has_swap = true,
 103                .has_wakeup = true,
 104                .has_fifo = true,
 105                .fifosize = 16,
 106        }
 107};
 108
 109/* USART_SR (F4) / USART_ISR (F7) */
 110#define USART_SR_PE             BIT(0)
 111#define USART_SR_FE             BIT(1)
 112#define USART_SR_NF             BIT(2)
 113#define USART_SR_ORE            BIT(3)
 114#define USART_SR_IDLE           BIT(4)
 115#define USART_SR_RXNE           BIT(5)
 116#define USART_SR_TC             BIT(6)
 117#define USART_SR_TXE            BIT(7)
 118#define USART_SR_CTSIF          BIT(9)
 119#define USART_SR_CTS            BIT(10)         /* F7 */
 120#define USART_SR_RTOF           BIT(11)         /* F7 */
 121#define USART_SR_EOBF           BIT(12)         /* F7 */
 122#define USART_SR_ABRE           BIT(14)         /* F7 */
 123#define USART_SR_ABRF           BIT(15)         /* F7 */
 124#define USART_SR_BUSY           BIT(16)         /* F7 */
 125#define USART_SR_CMF            BIT(17)         /* F7 */
 126#define USART_SR_SBKF           BIT(18)         /* F7 */
 127#define USART_SR_WUF            BIT(20)         /* H7 */
 128#define USART_SR_TEACK          BIT(21)         /* F7 */
 129#define USART_SR_ERR_MASK       (USART_SR_ORE | USART_SR_FE | USART_SR_PE)
 130/* Dummy bits */
 131#define USART_SR_DUMMY_RX       BIT(16)
 132
 133/* USART_DR */
 134#define USART_DR_MASK           GENMASK(8, 0)
 135
 136/* USART_BRR */
 137#define USART_BRR_DIV_F_MASK    GENMASK(3, 0)
 138#define USART_BRR_DIV_M_MASK    GENMASK(15, 4)
 139#define USART_BRR_DIV_M_SHIFT   4
 140#define USART_BRR_04_R_SHIFT    1
 141
 142/* USART_CR1 */
 143#define USART_CR1_SBK           BIT(0)
 144#define USART_CR1_RWU           BIT(1)          /* F4 */
 145#define USART_CR1_UESM          BIT(1)          /* H7 */
 146#define USART_CR1_RE            BIT(2)
 147#define USART_CR1_TE            BIT(3)
 148#define USART_CR1_IDLEIE        BIT(4)
 149#define USART_CR1_RXNEIE        BIT(5)
 150#define USART_CR1_TCIE          BIT(6)
 151#define USART_CR1_TXEIE         BIT(7)
 152#define USART_CR1_PEIE          BIT(8)
 153#define USART_CR1_PS            BIT(9)
 154#define USART_CR1_PCE           BIT(10)
 155#define USART_CR1_WAKE          BIT(11)
 156#define USART_CR1_M0            BIT(12)         /* F7 (CR1_M for F4) */
 157#define USART_CR1_MME           BIT(13)         /* F7 */
 158#define USART_CR1_CMIE          BIT(14)         /* F7 */
 159#define USART_CR1_OVER8         BIT(15)
 160#define USART_CR1_DEDT_MASK     GENMASK(20, 16) /* F7 */
 161#define USART_CR1_DEAT_MASK     GENMASK(25, 21) /* F7 */
 162#define USART_CR1_RTOIE         BIT(26)         /* F7 */
 163#define USART_CR1_EOBIE         BIT(27)         /* F7 */
 164#define USART_CR1_M1            BIT(28)         /* F7 */
 165#define USART_CR1_IE_MASK       (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
 166#define USART_CR1_FIFOEN        BIT(29)         /* H7 */
 167#define USART_CR1_DEAT_SHIFT 21
 168#define USART_CR1_DEDT_SHIFT 16
 169
 170/* USART_CR2 */
 171#define USART_CR2_ADD_MASK      GENMASK(3, 0)   /* F4 */
 172#define USART_CR2_ADDM7         BIT(4)          /* F7 */
 173#define USART_CR2_LBCL          BIT(8)
 174#define USART_CR2_CPHA          BIT(9)
 175#define USART_CR2_CPOL          BIT(10)
 176#define USART_CR2_CLKEN         BIT(11)
 177#define USART_CR2_STOP_2B       BIT(13)
 178#define USART_CR2_STOP_MASK     GENMASK(13, 12)
 179#define USART_CR2_LINEN         BIT(14)
 180#define USART_CR2_SWAP          BIT(15)         /* F7 */
 181#define USART_CR2_RXINV         BIT(16)         /* F7 */
 182#define USART_CR2_TXINV         BIT(17)         /* F7 */
 183#define USART_CR2_DATAINV       BIT(18)         /* F7 */
 184#define USART_CR2_MSBFIRST      BIT(19)         /* F7 */
 185#define USART_CR2_ABREN         BIT(20)         /* F7 */
 186#define USART_CR2_ABRMOD_MASK   GENMASK(22, 21) /* F7 */
 187#define USART_CR2_RTOEN         BIT(23)         /* F7 */
 188#define USART_CR2_ADD_F7_MASK   GENMASK(31, 24) /* F7 */
 189
 190/* USART_CR3 */
 191#define USART_CR3_EIE           BIT(0)
 192#define USART_CR3_IREN          BIT(1)
 193#define USART_CR3_IRLP          BIT(2)
 194#define USART_CR3_HDSEL         BIT(3)
 195#define USART_CR3_NACK          BIT(4)
 196#define USART_CR3_SCEN          BIT(5)
 197#define USART_CR3_DMAR          BIT(6)
 198#define USART_CR3_DMAT          BIT(7)
 199#define USART_CR3_RTSE          BIT(8)
 200#define USART_CR3_CTSE          BIT(9)
 201#define USART_CR3_CTSIE         BIT(10)
 202#define USART_CR3_ONEBIT        BIT(11)
 203#define USART_CR3_OVRDIS        BIT(12)         /* F7 */
 204#define USART_CR3_DDRE          BIT(13)         /* F7 */
 205#define USART_CR3_DEM           BIT(14)         /* F7 */
 206#define USART_CR3_DEP           BIT(15)         /* F7 */
 207#define USART_CR3_SCARCNT_MASK  GENMASK(19, 17) /* F7 */
 208#define USART_CR3_WUS_MASK      GENMASK(21, 20) /* H7 */
 209#define USART_CR3_WUS_START_BIT BIT(21)         /* H7 */
 210#define USART_CR3_WUFIE         BIT(22)         /* H7 */
 211#define USART_CR3_TXFTIE        BIT(23)         /* H7 */
 212#define USART_CR3_TCBGTIE       BIT(24)         /* H7 */
 213#define USART_CR3_RXFTCFG_MASK  GENMASK(27, 25) /* H7 */
 214#define USART_CR3_RXFTCFG_SHIFT 25              /* H7 */
 215#define USART_CR3_RXFTIE        BIT(28)         /* H7 */
 216#define USART_CR3_TXFTCFG_MASK  GENMASK(31, 29) /* H7 */
 217#define USART_CR3_TXFTCFG_SHIFT 29              /* H7 */
 218
 219/* USART_GTPR */
 220#define USART_GTPR_PSC_MASK     GENMASK(7, 0)
 221#define USART_GTPR_GT_MASK      GENMASK(15, 8)
 222
 223/* USART_RTOR */
 224#define USART_RTOR_RTO_MASK     GENMASK(23, 0)  /* F7 */
 225#define USART_RTOR_BLEN_MASK    GENMASK(31, 24) /* F7 */
 226
 227/* USART_RQR */
 228#define USART_RQR_ABRRQ         BIT(0)          /* F7 */
 229#define USART_RQR_SBKRQ         BIT(1)          /* F7 */
 230#define USART_RQR_MMRQ          BIT(2)          /* F7 */
 231#define USART_RQR_RXFRQ         BIT(3)          /* F7 */
 232#define USART_RQR_TXFRQ         BIT(4)          /* F7 */
 233
 234/* USART_ICR */
 235#define USART_ICR_PECF          BIT(0)          /* F7 */
 236#define USART_ICR_FECF          BIT(1)          /* F7 */
 237#define USART_ICR_ORECF         BIT(3)          /* F7 */
 238#define USART_ICR_IDLECF        BIT(4)          /* F7 */
 239#define USART_ICR_TCCF          BIT(6)          /* F7 */
 240#define USART_ICR_CTSCF         BIT(9)          /* F7 */
 241#define USART_ICR_RTOCF         BIT(11)         /* F7 */
 242#define USART_ICR_EOBCF         BIT(12)         /* F7 */
 243#define USART_ICR_CMCF          BIT(17)         /* F7 */
 244#define USART_ICR_WUCF          BIT(20)         /* H7 */
 245
 246#define STM32_SERIAL_NAME "ttySTM"
 247#define STM32_MAX_PORTS 8
 248
 249#define RX_BUF_L 200             /* dma rx buffer length     */
 250#define RX_BUF_P RX_BUF_L        /* dma rx buffer period     */
 251#define TX_BUF_L 200             /* dma tx buffer length     */
 252
 253struct stm32_port {
 254        struct uart_port port;
 255        struct clk *clk;
 256        const struct stm32_usart_info *info;
 257        struct dma_chan *rx_ch;  /* dma rx channel            */
 258        dma_addr_t rx_dma_buf;   /* dma rx buffer bus address */
 259        unsigned char *rx_buf;   /* dma rx buffer cpu address */
 260        struct dma_chan *tx_ch;  /* dma tx channel            */
 261        dma_addr_t tx_dma_buf;   /* dma tx buffer bus address */
 262        unsigned char *tx_buf;   /* dma tx buffer cpu address */
 263        u32 cr1_irq;             /* USART_CR1_RXNEIE or RTOIE */
 264        u32 cr3_irq;             /* USART_CR3_RXFTIE */
 265        int last_res;
 266        bool tx_dma_busy;        /* dma tx busy               */
 267        bool hw_flow_control;
 268        bool swap;               /* swap RX & TX pins */
 269        bool fifoen;
 270        int rxftcfg;            /* RX FIFO threshold CFG      */
 271        int txftcfg;            /* TX FIFO threshold CFG      */
 272        bool wakeup_src;
 273        int rdr_mask;           /* receive data register mask */
 274        struct mctrl_gpios *gpios; /* modem control gpios */
 275};
 276
 277static struct stm32_port stm32_ports[STM32_MAX_PORTS];
 278static struct uart_driver stm32_usart_driver;
 279