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10#ifndef __ACTBL1_H__
11#define __ACTBL1_H__
12
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25
26
27#define ACPI_SIG_ASF "ASF!"
28#define ACPI_SIG_BERT "BERT"
29#define ACPI_SIG_BGRT "BGRT"
30#define ACPI_SIG_BOOT "BOOT"
31#define ACPI_SIG_CEDT "CEDT"
32#define ACPI_SIG_CPEP "CPEP"
33#define ACPI_SIG_CSRT "CSRT"
34#define ACPI_SIG_DBG2 "DBG2"
35#define ACPI_SIG_DBGP "DBGP"
36#define ACPI_SIG_DMAR "DMAR"
37#define ACPI_SIG_DRTM "DRTM"
38#define ACPI_SIG_ECDT "ECDT"
39#define ACPI_SIG_EINJ "EINJ"
40#define ACPI_SIG_ERST "ERST"
41#define ACPI_SIG_FPDT "FPDT"
42#define ACPI_SIG_GTDT "GTDT"
43#define ACPI_SIG_HEST "HEST"
44#define ACPI_SIG_HMAT "HMAT"
45#define ACPI_SIG_HPET "HPET"
46#define ACPI_SIG_IBFT "IBFT"
47
48#define ACPI_SIG_S3PT "S3PT"
49#define ACPI_SIG_PCCS "PCC"
50
51
52
53#define ACPI_SIG_MATR "MATR"
54#define ACPI_SIG_MSDM "MSDM"
55
56
57
58
59#ifdef ACPI_UNDEFINED_TABLES
60#define ACPI_SIG_ATKG "ATKG"
61#define ACPI_SIG_GSCI "GSCI"
62#define ACPI_SIG_IEIT "IEIT"
63#endif
64
65
66
67
68
69#pragma pack(1)
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89
90
91struct acpi_subtable_header {
92 u8 type;
93 u8 length;
94};
95
96
97
98struct acpi_whea_header {
99 u8 action;
100 u8 instruction;
101 u8 flags;
102 u8 reserved;
103 struct acpi_generic_address register_region;
104 u64 value;
105 u64 mask;
106};
107
108
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115
116
117struct acpi_table_asf {
118 struct acpi_table_header header;
119};
120
121
122
123struct acpi_asf_header {
124 u8 type;
125 u8 reserved;
126 u16 length;
127};
128
129
130
131enum acpi_asf_type {
132 ACPI_ASF_TYPE_INFO = 0,
133 ACPI_ASF_TYPE_ALERT = 1,
134 ACPI_ASF_TYPE_CONTROL = 2,
135 ACPI_ASF_TYPE_BOOT = 3,
136 ACPI_ASF_TYPE_ADDRESS = 4,
137 ACPI_ASF_TYPE_RESERVED = 5
138};
139
140
141
142
143
144
145
146struct acpi_asf_info {
147 struct acpi_asf_header header;
148 u8 min_reset_value;
149 u8 min_poll_interval;
150 u16 system_id;
151 u32 mfg_id;
152 u8 flags;
153 u8 reserved2[3];
154};
155
156
157
158#define ACPI_ASF_SMBUS_PROTOCOLS (1)
159
160
161
162struct acpi_asf_alert {
163 struct acpi_asf_header header;
164 u8 assert_mask;
165 u8 deassert_mask;
166 u8 alerts;
167 u8 data_length;
168};
169
170struct acpi_asf_alert_data {
171 u8 address;
172 u8 command;
173 u8 mask;
174 u8 value;
175 u8 sensor_type;
176 u8 type;
177 u8 offset;
178 u8 source_type;
179 u8 severity;
180 u8 sensor_number;
181 u8 entity;
182 u8 instance;
183};
184
185
186
187struct acpi_asf_remote {
188 struct acpi_asf_header header;
189 u8 controls;
190 u8 data_length;
191 u16 reserved2;
192};
193
194struct acpi_asf_control_data {
195 u8 function;
196 u8 address;
197 u8 command;
198 u8 value;
199};
200
201
202
203struct acpi_asf_rmcp {
204 struct acpi_asf_header header;
205 u8 capabilities[7];
206 u8 completion_code;
207 u32 enterprise_id;
208 u8 command;
209 u16 parameter;
210 u16 boot_options;
211 u16 oem_parameters;
212};
213
214
215
216struct acpi_asf_address {
217 struct acpi_asf_header header;
218 u8 eprom_address;
219 u8 devices;
220};
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227
228
229struct acpi_table_bert {
230 struct acpi_table_header header;
231 u32 region_length;
232 u64 address;
233};
234
235
236
237struct acpi_bert_region {
238 u32 block_status;
239 u32 raw_data_offset;
240 u32 raw_data_length;
241 u32 data_length;
242 u32 error_severity;
243};
244
245
246
247#define ACPI_BERT_UNCORRECTABLE (1)
248#define ACPI_BERT_CORRECTABLE (1<<1)
249#define ACPI_BERT_MULTIPLE_UNCORRECTABLE (1<<2)
250#define ACPI_BERT_MULTIPLE_CORRECTABLE (1<<3)
251#define ACPI_BERT_ERROR_ENTRY_COUNT (0xFF<<4)
252
253
254
255enum acpi_bert_error_severity {
256 ACPI_BERT_ERROR_CORRECTABLE = 0,
257 ACPI_BERT_ERROR_FATAL = 1,
258 ACPI_BERT_ERROR_CORRECTED = 2,
259 ACPI_BERT_ERROR_NONE = 3,
260 ACPI_BERT_ERROR_RESERVED = 4
261};
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273
274
275struct acpi_table_bgrt {
276 struct acpi_table_header header;
277 u16 version;
278 u8 status;
279 u8 image_type;
280 u64 image_address;
281 u32 image_offset_x;
282 u32 image_offset_y;
283};
284
285
286
287#define ACPI_BGRT_DISPLAYED (1)
288#define ACPI_BGRT_ORIENTATION_OFFSET (3 << 1)
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298
299struct acpi_table_boot {
300 struct acpi_table_header header;
301 u8 cmos_index;
302 u8 reserved[3];
303};
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312
313
314struct acpi_table_cedt {
315 struct acpi_table_header header;
316};
317
318
319
320struct acpi_cedt_header {
321 u8 type;
322 u8 reserved;
323 u16 length;
324};
325
326
327
328enum acpi_cedt_type {
329 ACPI_CEDT_TYPE_CHBS = 0,
330 ACPI_CEDT_TYPE_RESERVED = 1
331};
332
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338
339struct acpi_cedt_chbs {
340 struct acpi_cedt_header header;
341 u32 uid;
342 u32 cxl_version;
343 u32 reserved;
344 u64 base;
345 u64 length;
346};
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354
355struct acpi_table_cpep {
356 struct acpi_table_header header;
357 u64 reserved;
358};
359
360
361
362struct acpi_cpep_polling {
363 struct acpi_subtable_header header;
364 u8 id;
365 u8 eid;
366 u32 interval;
367};
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375
376
377
378struct acpi_table_csrt {
379 struct acpi_table_header header;
380};
381
382
383
384struct acpi_csrt_group {
385 u32 length;
386 u32 vendor_id;
387 u32 subvendor_id;
388 u16 device_id;
389 u16 subdevice_id;
390 u16 revision;
391 u16 reserved;
392 u32 shared_info_length;
393
394
395};
396
397
398
399struct acpi_csrt_shared_info {
400 u16 major_version;
401 u16 minor_version;
402 u32 mmio_base_low;
403 u32 mmio_base_high;
404 u32 gsi_interrupt;
405 u8 interrupt_polarity;
406 u8 interrupt_mode;
407 u8 num_channels;
408 u8 dma_address_width;
409 u16 base_request_line;
410 u16 num_handshake_signals;
411 u32 max_block_size;
412
413
414};
415
416
417
418struct acpi_csrt_descriptor {
419 u32 length;
420 u16 type;
421 u16 subtype;
422 u32 uid;
423
424
425};
426
427
428
429#define ACPI_CSRT_TYPE_INTERRUPT 0x0001
430#define ACPI_CSRT_TYPE_TIMER 0x0002
431#define ACPI_CSRT_TYPE_DMA 0x0003
432
433
434
435#define ACPI_CSRT_XRUPT_LINE 0x0000
436#define ACPI_CSRT_XRUPT_CONTROLLER 0x0001
437#define ACPI_CSRT_TIMER 0x0000
438#define ACPI_CSRT_DMA_CHANNEL 0x0000
439#define ACPI_CSRT_DMA_CONTROLLER 0x0001
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447
448
449
450struct acpi_table_dbg2 {
451 struct acpi_table_header header;
452 u32 info_offset;
453 u32 info_count;
454};
455
456struct acpi_dbg2_header {
457 u32 info_offset;
458 u32 info_count;
459};
460
461
462
463struct acpi_dbg2_device {
464 u8 revision;
465 u16 length;
466 u8 register_count;
467 u16 namepath_length;
468 u16 namepath_offset;
469 u16 oem_data_length;
470 u16 oem_data_offset;
471 u16 port_type;
472 u16 port_subtype;
473 u16 reserved;
474 u16 base_address_offset;
475 u16 address_size_offset;
476
477
478
479
480
481
482
483};
484
485
486
487#define ACPI_DBG2_SERIAL_PORT 0x8000
488#define ACPI_DBG2_1394_PORT 0x8001
489#define ACPI_DBG2_USB_PORT 0x8002
490#define ACPI_DBG2_NET_PORT 0x8003
491
492
493
494#define ACPI_DBG2_16550_COMPATIBLE 0x0000
495#define ACPI_DBG2_16550_SUBSET 0x0001
496#define ACPI_DBG2_ARM_PL011 0x0003
497#define ACPI_DBG2_ARM_SBSA_32BIT 0x000D
498#define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E
499#define ACPI_DBG2_ARM_DCC 0x000F
500#define ACPI_DBG2_BCM2835 0x0010
501
502#define ACPI_DBG2_1394_STANDARD 0x0000
503
504#define ACPI_DBG2_USB_XHCI 0x0000
505#define ACPI_DBG2_USB_EHCI 0x0001
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515
516struct acpi_table_dbgp {
517 struct acpi_table_header header;
518 u8 type;
519 u8 reserved[3];
520 struct acpi_generic_address debug_port;
521};
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531
532
533struct acpi_table_dmar {
534 struct acpi_table_header header;
535 u8 width;
536 u8 flags;
537 u8 reserved[10];
538};
539
540
541
542#define ACPI_DMAR_INTR_REMAP (1)
543#define ACPI_DMAR_X2APIC_OPT_OUT (1<<1)
544#define ACPI_DMAR_X2APIC_MODE (1<<2)
545
546
547
548struct acpi_dmar_header {
549 u16 type;
550 u16 length;
551};
552
553
554
555enum acpi_dmar_type {
556 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0,
557 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1,
558 ACPI_DMAR_TYPE_ROOT_ATS = 2,
559 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3,
560 ACPI_DMAR_TYPE_NAMESPACE = 4,
561 ACPI_DMAR_TYPE_SATC = 5,
562 ACPI_DMAR_TYPE_RESERVED = 6
563};
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565
566
567struct acpi_dmar_device_scope {
568 u8 entry_type;
569 u8 length;
570 u16 reserved;
571 u8 enumeration_id;
572 u8 bus;
573};
574
575
576
577enum acpi_dmar_scope_type {
578 ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0,
579 ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1,
580 ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2,
581 ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3,
582 ACPI_DMAR_SCOPE_TYPE_HPET = 4,
583 ACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5,
584 ACPI_DMAR_SCOPE_TYPE_RESERVED = 6
585};
586
587struct acpi_dmar_pci_path {
588 u8 device;
589 u8 function;
590};
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598struct acpi_dmar_hardware_unit {
599 struct acpi_dmar_header header;
600 u8 flags;
601 u8 reserved;
602 u16 segment;
603 u64 address;
604};
605
606
607
608#define ACPI_DMAR_INCLUDE_ALL (1)
609
610
611
612struct acpi_dmar_reserved_memory {
613 struct acpi_dmar_header header;
614 u16 reserved;
615 u16 segment;
616 u64 base_address;
617 u64 end_address;
618};
619
620
621
622#define ACPI_DMAR_ALLOW_ALL (1)
623
624
625
626struct acpi_dmar_atsr {
627 struct acpi_dmar_header header;
628 u8 flags;
629 u8 reserved;
630 u16 segment;
631};
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634
635#define ACPI_DMAR_ALL_PORTS (1)
636
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638
639struct acpi_dmar_rhsa {
640 struct acpi_dmar_header header;
641 u32 reserved;
642 u64 base_address;
643 u32 proximity_domain;
644};
645
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647
648struct acpi_dmar_andd {
649 struct acpi_dmar_header header;
650 u8 reserved[3];
651 u8 device_number;
652 char device_name[1];
653};
654
655
656
657struct acpi_dmar_satc {
658 struct acpi_dmar_header header;
659 u8 flags;
660 u8 reserved;
661 u16 segment;
662};
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671struct acpi_table_drtm {
672 struct acpi_table_header header;
673 u64 entry_base_address;
674 u64 entry_length;
675 u32 entry_address32;
676 u64 entry_address64;
677 u64 exit_address;
678 u64 log_area_address;
679 u32 log_area_length;
680 u64 arch_dependent_address;
681 u32 flags;
682};
683
684
685
686#define ACPI_DRTM_ACCESS_ALLOWED (1)
687#define ACPI_DRTM_ENABLE_GAP_CODE (1<<1)
688#define ACPI_DRTM_INCOMPLETE_MEASUREMENTS (1<<2)
689#define ACPI_DRTM_AUTHORITY_ORDER (1<<3)
690
691
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693struct acpi_drtm_vtable_list {
694 u32 validated_table_count;
695 u64 validated_tables[1];
696};
697
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699
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701
702struct acpi_drtm_resource {
703 u8 size[7];
704 u8 type;
705 u64 address;
706};
707
708struct acpi_drtm_resource_list {
709 u32 resource_count;
710 struct acpi_drtm_resource resources[1];
711};
712
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715struct acpi_drtm_dps_id {
716 u32 dps_id_length;
717 u8 dps_id[16];
718};
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727struct acpi_table_ecdt {
728 struct acpi_table_header header;
729 struct acpi_generic_address control;
730 struct acpi_generic_address data;
731 u32 uid;
732 u8 gpe;
733 u8 id[1];
734};
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743struct acpi_table_einj {
744 struct acpi_table_header header;
745 u32 header_length;
746 u8 flags;
747 u8 reserved[3];
748 u32 entries;
749};
750
751
752
753struct acpi_einj_entry {
754 struct acpi_whea_header whea_header;
755};
756
757
758
759#define ACPI_EINJ_PRESERVE (1)
760
761
762
763enum acpi_einj_actions {
764 ACPI_EINJ_BEGIN_OPERATION = 0,
765 ACPI_EINJ_GET_TRIGGER_TABLE = 1,
766 ACPI_EINJ_SET_ERROR_TYPE = 2,
767 ACPI_EINJ_GET_ERROR_TYPE = 3,
768 ACPI_EINJ_END_OPERATION = 4,
769 ACPI_EINJ_EXECUTE_OPERATION = 5,
770 ACPI_EINJ_CHECK_BUSY_STATUS = 6,
771 ACPI_EINJ_GET_COMMAND_STATUS = 7,
772 ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS = 8,
773 ACPI_EINJ_GET_EXECUTE_TIMINGS = 9,
774 ACPI_EINJ_ACTION_RESERVED = 10,
775 ACPI_EINJ_TRIGGER_ERROR = 0xFF
776};
777
778
779
780enum acpi_einj_instructions {
781 ACPI_EINJ_READ_REGISTER = 0,
782 ACPI_EINJ_READ_REGISTER_VALUE = 1,
783 ACPI_EINJ_WRITE_REGISTER = 2,
784 ACPI_EINJ_WRITE_REGISTER_VALUE = 3,
785 ACPI_EINJ_NOOP = 4,
786 ACPI_EINJ_FLUSH_CACHELINE = 5,
787 ACPI_EINJ_INSTRUCTION_RESERVED = 6
788};
789
790struct acpi_einj_error_type_with_addr {
791 u32 error_type;
792 u32 vendor_struct_offset;
793 u32 flags;
794 u32 apic_id;
795 u64 address;
796 u64 range;
797 u32 pcie_id;
798};
799
800struct acpi_einj_vendor {
801 u32 length;
802 u32 pcie_id;
803 u16 vendor_id;
804 u16 device_id;
805 u8 revision_id;
806 u8 reserved[3];
807};
808
809
810
811struct acpi_einj_trigger {
812 u32 header_size;
813 u32 revision;
814 u32 table_size;
815 u32 entry_count;
816};
817
818
819
820enum acpi_einj_command_status {
821 ACPI_EINJ_SUCCESS = 0,
822 ACPI_EINJ_FAILURE = 1,
823 ACPI_EINJ_INVALID_ACCESS = 2,
824 ACPI_EINJ_STATUS_RESERVED = 3
825};
826
827
828
829#define ACPI_EINJ_PROCESSOR_CORRECTABLE (1)
830#define ACPI_EINJ_PROCESSOR_UNCORRECTABLE (1<<1)
831#define ACPI_EINJ_PROCESSOR_FATAL (1<<2)
832#define ACPI_EINJ_MEMORY_CORRECTABLE (1<<3)
833#define ACPI_EINJ_MEMORY_UNCORRECTABLE (1<<4)
834#define ACPI_EINJ_MEMORY_FATAL (1<<5)
835#define ACPI_EINJ_PCIX_CORRECTABLE (1<<6)
836#define ACPI_EINJ_PCIX_UNCORRECTABLE (1<<7)
837#define ACPI_EINJ_PCIX_FATAL (1<<8)
838#define ACPI_EINJ_PLATFORM_CORRECTABLE (1<<9)
839#define ACPI_EINJ_PLATFORM_UNCORRECTABLE (1<<10)
840#define ACPI_EINJ_PLATFORM_FATAL (1<<11)
841#define ACPI_EINJ_VENDOR_DEFINED (1<<31)
842
843
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845
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848
849
850struct acpi_table_erst {
851 struct acpi_table_header header;
852 u32 header_length;
853 u32 reserved;
854 u32 entries;
855};
856
857
858
859struct acpi_erst_entry {
860 struct acpi_whea_header whea_header;
861};
862
863
864
865#define ACPI_ERST_PRESERVE (1)
866
867
868
869enum acpi_erst_actions {
870 ACPI_ERST_BEGIN_WRITE = 0,
871 ACPI_ERST_BEGIN_READ = 1,
872 ACPI_ERST_BEGIN_CLEAR = 2,
873 ACPI_ERST_END = 3,
874 ACPI_ERST_SET_RECORD_OFFSET = 4,
875 ACPI_ERST_EXECUTE_OPERATION = 5,
876 ACPI_ERST_CHECK_BUSY_STATUS = 6,
877 ACPI_ERST_GET_COMMAND_STATUS = 7,
878 ACPI_ERST_GET_RECORD_ID = 8,
879 ACPI_ERST_SET_RECORD_ID = 9,
880 ACPI_ERST_GET_RECORD_COUNT = 10,
881 ACPI_ERST_BEGIN_DUMMY_WRIITE = 11,
882 ACPI_ERST_NOT_USED = 12,
883 ACPI_ERST_GET_ERROR_RANGE = 13,
884 ACPI_ERST_GET_ERROR_LENGTH = 14,
885 ACPI_ERST_GET_ERROR_ATTRIBUTES = 15,
886 ACPI_ERST_EXECUTE_TIMINGS = 16,
887 ACPI_ERST_ACTION_RESERVED = 17
888};
889
890
891
892enum acpi_erst_instructions {
893 ACPI_ERST_READ_REGISTER = 0,
894 ACPI_ERST_READ_REGISTER_VALUE = 1,
895 ACPI_ERST_WRITE_REGISTER = 2,
896 ACPI_ERST_WRITE_REGISTER_VALUE = 3,
897 ACPI_ERST_NOOP = 4,
898 ACPI_ERST_LOAD_VAR1 = 5,
899 ACPI_ERST_LOAD_VAR2 = 6,
900 ACPI_ERST_STORE_VAR1 = 7,
901 ACPI_ERST_ADD = 8,
902 ACPI_ERST_SUBTRACT = 9,
903 ACPI_ERST_ADD_VALUE = 10,
904 ACPI_ERST_SUBTRACT_VALUE = 11,
905 ACPI_ERST_STALL = 12,
906 ACPI_ERST_STALL_WHILE_TRUE = 13,
907 ACPI_ERST_SKIP_NEXT_IF_TRUE = 14,
908 ACPI_ERST_GOTO = 15,
909 ACPI_ERST_SET_SRC_ADDRESS_BASE = 16,
910 ACPI_ERST_SET_DST_ADDRESS_BASE = 17,
911 ACPI_ERST_MOVE_DATA = 18,
912 ACPI_ERST_INSTRUCTION_RESERVED = 19
913};
914
915
916
917enum acpi_erst_command_status {
918 ACPI_ERST_SUCCESS = 0,
919 ACPI_ERST_NO_SPACE = 1,
920 ACPI_ERST_NOT_AVAILABLE = 2,
921 ACPI_ERST_FAILURE = 3,
922 ACPI_ERST_RECORD_EMPTY = 4,
923 ACPI_ERST_NOT_FOUND = 5,
924 ACPI_ERST_STATUS_RESERVED = 6
925};
926
927
928
929struct acpi_erst_info {
930 u16 signature;
931 u8 data[48];
932};
933
934
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936
937
938
939
940
941struct acpi_table_fpdt {
942 struct acpi_table_header header;
943};
944
945
946
947struct acpi_fpdt_header {
948 u16 type;
949 u8 length;
950 u8 revision;
951};
952
953
954
955enum acpi_fpdt_type {
956 ACPI_FPDT_TYPE_BOOT = 0,
957 ACPI_FPDT_TYPE_S3PERF = 1
958};
959
960
961
962
963
964
965
966struct acpi_fpdt_boot_pointer {
967 struct acpi_fpdt_header header;
968 u8 reserved[4];
969 u64 address;
970};
971
972
973
974struct acpi_fpdt_s3pt_pointer {
975 struct acpi_fpdt_header header;
976 u8 reserved[4];
977 u64 address;
978};
979
980
981
982
983
984struct acpi_table_s3pt {
985 u8 signature[4];
986 u32 length;
987};
988
989
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991
992
993
994
995enum acpi_s3pt_type {
996 ACPI_S3PT_TYPE_RESUME = 0,
997 ACPI_S3PT_TYPE_SUSPEND = 1,
998 ACPI_FPDT_BOOT_PERFORMANCE = 2
999};
1000
1001struct acpi_s3pt_resume {
1002 struct acpi_fpdt_header header;
1003 u32 resume_count;
1004 u64 full_resume;
1005 u64 average_resume;
1006};
1007
1008struct acpi_s3pt_suspend {
1009 struct acpi_fpdt_header header;
1010 u64 suspend_start;
1011 u64 suspend_end;
1012};
1013
1014
1015
1016
1017struct acpi_fpdt_boot {
1018 struct acpi_fpdt_header header;
1019 u8 reserved[4];
1020 u64 reset_end;
1021 u64 load_start;
1022 u64 startup_start;
1023 u64 exit_services_entry;
1024 u64 exit_services_exit;
1025};
1026
1027
1028
1029
1030
1031
1032
1033
1034struct acpi_table_gtdt {
1035 struct acpi_table_header header;
1036 u64 counter_block_addresss;
1037 u32 reserved;
1038 u32 secure_el1_interrupt;
1039 u32 secure_el1_flags;
1040 u32 non_secure_el1_interrupt;
1041 u32 non_secure_el1_flags;
1042 u32 virtual_timer_interrupt;
1043 u32 virtual_timer_flags;
1044 u32 non_secure_el2_interrupt;
1045 u32 non_secure_el2_flags;
1046 u64 counter_read_block_address;
1047 u32 platform_timer_count;
1048 u32 platform_timer_offset;
1049};
1050
1051
1052
1053#define ACPI_GTDT_INTERRUPT_MODE (1)
1054#define ACPI_GTDT_INTERRUPT_POLARITY (1<<1)
1055#define ACPI_GTDT_ALWAYS_ON (1<<2)
1056
1057struct acpi_gtdt_el2 {
1058 u32 virtual_el2_timer_gsiv;
1059 u32 virtual_el2_timer_flags;
1060};
1061
1062
1063
1064struct acpi_gtdt_header {
1065 u8 type;
1066 u16 length;
1067};
1068
1069
1070
1071enum acpi_gtdt_type {
1072 ACPI_GTDT_TYPE_TIMER_BLOCK = 0,
1073 ACPI_GTDT_TYPE_WATCHDOG = 1,
1074 ACPI_GTDT_TYPE_RESERVED = 2
1075};
1076
1077
1078
1079
1080
1081struct acpi_gtdt_timer_block {
1082 struct acpi_gtdt_header header;
1083 u8 reserved;
1084 u64 block_address;
1085 u32 timer_count;
1086 u32 timer_offset;
1087};
1088
1089
1090
1091struct acpi_gtdt_timer_entry {
1092 u8 frame_number;
1093 u8 reserved[3];
1094 u64 base_address;
1095 u64 el0_base_address;
1096 u32 timer_interrupt;
1097 u32 timer_flags;
1098 u32 virtual_timer_interrupt;
1099 u32 virtual_timer_flags;
1100 u32 common_flags;
1101};
1102
1103
1104
1105#define ACPI_GTDT_GT_IRQ_MODE (1)
1106#define ACPI_GTDT_GT_IRQ_POLARITY (1<<1)
1107
1108
1109
1110#define ACPI_GTDT_GT_IS_SECURE_TIMER (1)
1111#define ACPI_GTDT_GT_ALWAYS_ON (1<<1)
1112
1113
1114
1115struct acpi_gtdt_watchdog {
1116 struct acpi_gtdt_header header;
1117 u8 reserved;
1118 u64 refresh_frame_address;
1119 u64 control_frame_address;
1120 u32 timer_interrupt;
1121 u32 timer_flags;
1122};
1123
1124
1125
1126#define ACPI_GTDT_WATCHDOG_IRQ_MODE (1)
1127#define ACPI_GTDT_WATCHDOG_IRQ_POLARITY (1<<1)
1128#define ACPI_GTDT_WATCHDOG_SECURE (1<<2)
1129
1130
1131
1132
1133
1134
1135
1136
1137struct acpi_table_hest {
1138 struct acpi_table_header header;
1139 u32 error_source_count;
1140};
1141
1142
1143
1144struct acpi_hest_header {
1145 u16 type;
1146 u16 source_id;
1147};
1148
1149
1150
1151enum acpi_hest_types {
1152 ACPI_HEST_TYPE_IA32_CHECK = 0,
1153 ACPI_HEST_TYPE_IA32_CORRECTED_CHECK = 1,
1154 ACPI_HEST_TYPE_IA32_NMI = 2,
1155 ACPI_HEST_TYPE_NOT_USED3 = 3,
1156 ACPI_HEST_TYPE_NOT_USED4 = 4,
1157 ACPI_HEST_TYPE_NOT_USED5 = 5,
1158 ACPI_HEST_TYPE_AER_ROOT_PORT = 6,
1159 ACPI_HEST_TYPE_AER_ENDPOINT = 7,
1160 ACPI_HEST_TYPE_AER_BRIDGE = 8,
1161 ACPI_HEST_TYPE_GENERIC_ERROR = 9,
1162 ACPI_HEST_TYPE_GENERIC_ERROR_V2 = 10,
1163 ACPI_HEST_TYPE_IA32_DEFERRED_CHECK = 11,
1164 ACPI_HEST_TYPE_RESERVED = 12
1165};
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175struct acpi_hest_ia_error_bank {
1176 u8 bank_number;
1177 u8 clear_status_on_init;
1178 u8 status_format;
1179 u8 reserved;
1180 u32 control_register;
1181 u64 control_data;
1182 u32 status_register;
1183 u32 address_register;
1184 u32 misc_register;
1185};
1186
1187
1188
1189struct acpi_hest_aer_common {
1190 u16 reserved1;
1191 u8 flags;
1192 u8 enabled;
1193 u32 records_to_preallocate;
1194 u32 max_sections_per_record;
1195 u32 bus;
1196 u16 device;
1197 u16 function;
1198 u16 device_control;
1199 u16 reserved2;
1200 u32 uncorrectable_mask;
1201 u32 uncorrectable_severity;
1202 u32 correctable_mask;
1203 u32 advanced_capabilities;
1204};
1205
1206
1207
1208#define ACPI_HEST_FIRMWARE_FIRST (1)
1209#define ACPI_HEST_GLOBAL (1<<1)
1210#define ACPI_HEST_GHES_ASSIST (1<<2)
1211
1212
1213
1214
1215
1216
1217#define ACPI_HEST_BUS(bus) ((bus) & 0xFF)
1218#define ACPI_HEST_SEGMENT(bus) (((bus) >> 8) & 0xFFFF)
1219
1220
1221
1222struct acpi_hest_notify {
1223 u8 type;
1224 u8 length;
1225 u16 config_write_enable;
1226 u32 poll_interval;
1227 u32 vector;
1228 u32 polling_threshold_value;
1229 u32 polling_threshold_window;
1230 u32 error_threshold_value;
1231 u32 error_threshold_window;
1232};
1233
1234
1235
1236enum acpi_hest_notify_types {
1237 ACPI_HEST_NOTIFY_POLLED = 0,
1238 ACPI_HEST_NOTIFY_EXTERNAL = 1,
1239 ACPI_HEST_NOTIFY_LOCAL = 2,
1240 ACPI_HEST_NOTIFY_SCI = 3,
1241 ACPI_HEST_NOTIFY_NMI = 4,
1242 ACPI_HEST_NOTIFY_CMCI = 5,
1243 ACPI_HEST_NOTIFY_MCE = 6,
1244 ACPI_HEST_NOTIFY_GPIO = 7,
1245 ACPI_HEST_NOTIFY_SEA = 8,
1246 ACPI_HEST_NOTIFY_SEI = 9,
1247 ACPI_HEST_NOTIFY_GSIV = 10,
1248 ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED = 11,
1249 ACPI_HEST_NOTIFY_RESERVED = 12
1250};
1251
1252
1253
1254#define ACPI_HEST_TYPE (1)
1255#define ACPI_HEST_POLL_INTERVAL (1<<1)
1256#define ACPI_HEST_POLL_THRESHOLD_VALUE (1<<2)
1257#define ACPI_HEST_POLL_THRESHOLD_WINDOW (1<<3)
1258#define ACPI_HEST_ERR_THRESHOLD_VALUE (1<<4)
1259#define ACPI_HEST_ERR_THRESHOLD_WINDOW (1<<5)
1260
1261
1262
1263
1264
1265
1266
1267struct acpi_hest_ia_machine_check {
1268 struct acpi_hest_header header;
1269 u16 reserved1;
1270 u8 flags;
1271 u8 enabled;
1272 u32 records_to_preallocate;
1273 u32 max_sections_per_record;
1274 u64 global_capability_data;
1275 u64 global_control_data;
1276 u8 num_hardware_banks;
1277 u8 reserved3[7];
1278};
1279
1280
1281
1282struct acpi_hest_ia_corrected {
1283 struct acpi_hest_header header;
1284 u16 reserved1;
1285 u8 flags;
1286 u8 enabled;
1287 u32 records_to_preallocate;
1288 u32 max_sections_per_record;
1289 struct acpi_hest_notify notify;
1290 u8 num_hardware_banks;
1291 u8 reserved2[3];
1292};
1293
1294
1295
1296struct acpi_hest_ia_nmi {
1297 struct acpi_hest_header header;
1298 u32 reserved;
1299 u32 records_to_preallocate;
1300 u32 max_sections_per_record;
1301 u32 max_raw_data_length;
1302};
1303
1304
1305
1306
1307
1308struct acpi_hest_aer_root {
1309 struct acpi_hest_header header;
1310 struct acpi_hest_aer_common aer;
1311 u32 root_error_command;
1312};
1313
1314
1315
1316struct acpi_hest_aer {
1317 struct acpi_hest_header header;
1318 struct acpi_hest_aer_common aer;
1319};
1320
1321
1322
1323struct acpi_hest_aer_bridge {
1324 struct acpi_hest_header header;
1325 struct acpi_hest_aer_common aer;
1326 u32 uncorrectable_mask2;
1327 u32 uncorrectable_severity2;
1328 u32 advanced_capabilities2;
1329};
1330
1331
1332
1333struct acpi_hest_generic {
1334 struct acpi_hest_header header;
1335 u16 related_source_id;
1336 u8 reserved;
1337 u8 enabled;
1338 u32 records_to_preallocate;
1339 u32 max_sections_per_record;
1340 u32 max_raw_data_length;
1341 struct acpi_generic_address error_status_address;
1342 struct acpi_hest_notify notify;
1343 u32 error_block_length;
1344};
1345
1346
1347
1348struct acpi_hest_generic_v2 {
1349 struct acpi_hest_header header;
1350 u16 related_source_id;
1351 u8 reserved;
1352 u8 enabled;
1353 u32 records_to_preallocate;
1354 u32 max_sections_per_record;
1355 u32 max_raw_data_length;
1356 struct acpi_generic_address error_status_address;
1357 struct acpi_hest_notify notify;
1358 u32 error_block_length;
1359 struct acpi_generic_address read_ack_register;
1360 u64 read_ack_preserve;
1361 u64 read_ack_write;
1362};
1363
1364
1365
1366struct acpi_hest_generic_status {
1367 u32 block_status;
1368 u32 raw_data_offset;
1369 u32 raw_data_length;
1370 u32 data_length;
1371 u32 error_severity;
1372};
1373
1374
1375
1376#define ACPI_HEST_UNCORRECTABLE (1)
1377#define ACPI_HEST_CORRECTABLE (1<<1)
1378#define ACPI_HEST_MULTIPLE_UNCORRECTABLE (1<<2)
1379#define ACPI_HEST_MULTIPLE_CORRECTABLE (1<<3)
1380#define ACPI_HEST_ERROR_ENTRY_COUNT (0xFF<<4)
1381
1382
1383
1384struct acpi_hest_generic_data {
1385 u8 section_type[16];
1386 u32 error_severity;
1387 u16 revision;
1388 u8 validation_bits;
1389 u8 flags;
1390 u32 error_data_length;
1391 u8 fru_id[16];
1392 u8 fru_text[20];
1393};
1394
1395
1396
1397struct acpi_hest_generic_data_v300 {
1398 u8 section_type[16];
1399 u32 error_severity;
1400 u16 revision;
1401 u8 validation_bits;
1402 u8 flags;
1403 u32 error_data_length;
1404 u8 fru_id[16];
1405 u8 fru_text[20];
1406 u64 time_stamp;
1407};
1408
1409
1410
1411#define ACPI_HEST_GEN_ERROR_RECOVERABLE 0
1412#define ACPI_HEST_GEN_ERROR_FATAL 1
1413#define ACPI_HEST_GEN_ERROR_CORRECTED 2
1414#define ACPI_HEST_GEN_ERROR_NONE 3
1415
1416
1417
1418#define ACPI_HEST_GEN_VALID_FRU_ID (1)
1419#define ACPI_HEST_GEN_VALID_FRU_STRING (1<<1)
1420#define ACPI_HEST_GEN_VALID_TIMESTAMP (1<<2)
1421
1422
1423
1424struct acpi_hest_ia_deferred_check {
1425 struct acpi_hest_header header;
1426 u16 reserved1;
1427 u8 flags;
1428 u8 enabled;
1429 u32 records_to_preallocate;
1430 u32 max_sections_per_record;
1431 struct acpi_hest_notify notify;
1432 u8 num_hardware_banks;
1433 u8 reserved2[3];
1434};
1435
1436
1437
1438
1439
1440
1441
1442
1443struct acpi_table_hmat {
1444 struct acpi_table_header header;
1445 u32 reserved;
1446};
1447
1448
1449
1450enum acpi_hmat_type {
1451 ACPI_HMAT_TYPE_PROXIMITY = 0,
1452 ACPI_HMAT_TYPE_LOCALITY = 1,
1453 ACPI_HMAT_TYPE_CACHE = 2,
1454 ACPI_HMAT_TYPE_RESERVED = 3
1455};
1456
1457struct acpi_hmat_structure {
1458 u16 type;
1459 u16 reserved;
1460 u32 length;
1461};
1462
1463
1464
1465
1466
1467
1468
1469struct acpi_hmat_proximity_domain {
1470 struct acpi_hmat_structure header;
1471 u16 flags;
1472 u16 reserved1;
1473 u32 processor_PD;
1474 u32 memory_PD;
1475 u32 reserved2;
1476 u64 reserved3;
1477 u64 reserved4;
1478};
1479
1480
1481
1482#define ACPI_HMAT_PROCESSOR_PD_VALID (1)
1483#define ACPI_HMAT_MEMORY_PD_VALID (1<<1)
1484#define ACPI_HMAT_RESERVATION_HINT (1<<2)
1485
1486
1487
1488struct acpi_hmat_locality {
1489 struct acpi_hmat_structure header;
1490 u8 flags;
1491 u8 data_type;
1492 u8 min_transfer_size;
1493 u8 reserved1;
1494 u32 number_of_initiator_Pds;
1495 u32 number_of_target_Pds;
1496 u32 reserved2;
1497 u64 entry_base_unit;
1498};
1499
1500
1501
1502#define ACPI_HMAT_MEMORY_HIERARCHY (0x0F)
1503
1504
1505
1506#define ACPI_HMAT_MEMORY 0
1507#define ACPI_HMAT_LAST_LEVEL_CACHE 1
1508#define ACPI_HMAT_1ST_LEVEL_CACHE 2
1509#define ACPI_HMAT_2ND_LEVEL_CACHE 3
1510#define ACPI_HMAT_3RD_LEVEL_CACHE 4
1511#define ACPI_HMAT_MINIMUM_XFER_SIZE 0x10
1512#define ACPI_HMAT_NON_SEQUENTIAL_XFERS 0x20
1513
1514
1515
1516
1517#define ACPI_HMAT_ACCESS_LATENCY 0
1518#define ACPI_HMAT_READ_LATENCY 1
1519#define ACPI_HMAT_WRITE_LATENCY 2
1520#define ACPI_HMAT_ACCESS_BANDWIDTH 3
1521#define ACPI_HMAT_READ_BANDWIDTH 4
1522#define ACPI_HMAT_WRITE_BANDWIDTH 5
1523
1524
1525
1526struct acpi_hmat_cache {
1527 struct acpi_hmat_structure header;
1528 u32 memory_PD;
1529 u32 reserved1;
1530 u64 cache_size;
1531 u32 cache_attributes;
1532 u16 reserved2;
1533 u16 number_of_SMBIOShandles;
1534};
1535
1536
1537
1538#define ACPI_HMAT_TOTAL_CACHE_LEVEL (0x0000000F)
1539#define ACPI_HMAT_CACHE_LEVEL (0x000000F0)
1540#define ACPI_HMAT_CACHE_ASSOCIATIVITY (0x00000F00)
1541#define ACPI_HMAT_WRITE_POLICY (0x0000F000)
1542#define ACPI_HMAT_CACHE_LINE_SIZE (0xFFFF0000)
1543
1544
1545
1546#define ACPI_HMAT_CA_NONE (0)
1547#define ACPI_HMAT_CA_DIRECT_MAPPED (1)
1548#define ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING (2)
1549
1550
1551
1552#define ACPI_HMAT_CP_NONE (0)
1553#define ACPI_HMAT_CP_WB (1)
1554#define ACPI_HMAT_CP_WT (2)
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566struct acpi_table_hpet {
1567 struct acpi_table_header header;
1568 u32 id;
1569 struct acpi_generic_address address;
1570 u8 sequence;
1571 u16 minimum_tick;
1572 u8 flags;
1573};
1574
1575
1576
1577#define ACPI_HPET_PAGE_PROTECT_MASK (3)
1578
1579
1580
1581enum acpi_hpet_page_protect {
1582 ACPI_HPET_NO_PAGE_PROTECT = 0,
1583 ACPI_HPET_PAGE_PROTECT4 = 1,
1584 ACPI_HPET_PAGE_PROTECT64 = 2
1585};
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600struct acpi_table_ibft {
1601 struct acpi_table_header header;
1602 u8 reserved[12];
1603};
1604
1605
1606
1607struct acpi_ibft_header {
1608 u8 type;
1609 u8 version;
1610 u16 length;
1611 u8 index;
1612 u8 flags;
1613};
1614
1615
1616
1617enum acpi_ibft_type {
1618 ACPI_IBFT_TYPE_NOT_USED = 0,
1619 ACPI_IBFT_TYPE_CONTROL = 1,
1620 ACPI_IBFT_TYPE_INITIATOR = 2,
1621 ACPI_IBFT_TYPE_NIC = 3,
1622 ACPI_IBFT_TYPE_TARGET = 4,
1623 ACPI_IBFT_TYPE_EXTENSIONS = 5,
1624 ACPI_IBFT_TYPE_RESERVED = 6
1625};
1626
1627
1628
1629struct acpi_ibft_control {
1630 struct acpi_ibft_header header;
1631 u16 extensions;
1632 u16 initiator_offset;
1633 u16 nic0_offset;
1634 u16 target0_offset;
1635 u16 nic1_offset;
1636 u16 target1_offset;
1637};
1638
1639struct acpi_ibft_initiator {
1640 struct acpi_ibft_header header;
1641 u8 sns_server[16];
1642 u8 slp_server[16];
1643 u8 primary_server[16];
1644 u8 secondary_server[16];
1645 u16 name_length;
1646 u16 name_offset;
1647};
1648
1649struct acpi_ibft_nic {
1650 struct acpi_ibft_header header;
1651 u8 ip_address[16];
1652 u8 subnet_mask_prefix;
1653 u8 origin;
1654 u8 gateway[16];
1655 u8 primary_dns[16];
1656 u8 secondary_dns[16];
1657 u8 dhcp[16];
1658 u16 vlan;
1659 u8 mac_address[6];
1660 u16 pci_address;
1661 u16 name_length;
1662 u16 name_offset;
1663};
1664
1665struct acpi_ibft_target {
1666 struct acpi_ibft_header header;
1667 u8 target_ip_address[16];
1668 u16 target_ip_socket;
1669 u8 target_boot_lun[8];
1670 u8 chap_type;
1671 u8 nic_association;
1672 u16 target_name_length;
1673 u16 target_name_offset;
1674 u16 chap_name_length;
1675 u16 chap_name_offset;
1676 u16 chap_secret_length;
1677 u16 chap_secret_offset;
1678 u16 reverse_chap_name_length;
1679 u16 reverse_chap_name_offset;
1680 u16 reverse_chap_secret_length;
1681 u16 reverse_chap_secret_offset;
1682};
1683
1684
1685
1686#pragma pack()
1687
1688#endif
1689