1
2
3
4
5
6
7
8
9#ifndef _ASM_GENERIC_HYPERV_TLFS_H
10#define _ASM_GENERIC_HYPERV_TLFS_H
11
12#include <linux/types.h>
13#include <linux/bits.h>
14#include <linux/time64.h>
15
16
17
18
19
20
21
22#define HV_HYP_PAGE_SHIFT 12
23#define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT)
24#define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1))
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50#define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0)
51
52#define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1)
53
54#define HV_MSR_SYNIC_AVAILABLE BIT(2)
55
56#define HV_MSR_SYNTIMER_AVAILABLE BIT(3)
57
58#define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4)
59
60#define HV_MSR_HYPERCALL_AVAILABLE BIT(5)
61
62#define HV_MSR_VP_INDEX_AVAILABLE BIT(6)
63
64#define HV_MSR_RESET_AVAILABLE BIT(7)
65
66#define HV_MSR_STAT_PAGES_AVAILABLE BIT(8)
67
68#define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9)
69
70#define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10)
71
72#define HV_ACCESS_FREQUENCY_MSRS BIT(11)
73
74#define HV_ACCESS_REENLIGHTENMENT BIT(13)
75
76#define HV_ACCESS_TSC_INVARIANT BIT(15)
77
78
79
80
81#define HV_CREATE_PARTITIONS BIT(0)
82#define HV_ACCESS_PARTITION_ID BIT(1)
83#define HV_ACCESS_MEMORY_POOL BIT(2)
84#define HV_ADJUST_MESSAGE_BUFFERS BIT(3)
85#define HV_POST_MESSAGES BIT(4)
86#define HV_SIGNAL_EVENTS BIT(5)
87#define HV_CREATE_PORT BIT(6)
88#define HV_CONNECT_PORT BIT(7)
89#define HV_ACCESS_STATS BIT(8)
90#define HV_DEBUGGING BIT(11)
91#define HV_CPU_MANAGEMENT BIT(12)
92#define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20)
93#define HV_ISOLATION BIT(22)
94
95
96
97
98struct ms_hyperv_tsc_page {
99 volatile u32 tsc_sequence;
100 u32 reserved1;
101 volatile u64 tsc_scale;
102 volatile s64 tsc_offset;
103} __packed;
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129#define HV_LINUX_VENDOR_ID 0x8100
130
131
132
133
134#define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62)
135#define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63)
136
137
138#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002
139#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003
140#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
141#define HVCALL_SEND_IPI 0x000b
142#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013
143#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014
144#define HVCALL_SEND_IPI_EX 0x0015
145#define HVCALL_GET_PARTITION_ID 0x0046
146#define HVCALL_DEPOSIT_MEMORY 0x0048
147#define HVCALL_CREATE_VP 0x004e
148#define HVCALL_GET_VP_REGISTERS 0x0050
149#define HVCALL_SET_VP_REGISTERS 0x0051
150#define HVCALL_POST_MESSAGE 0x005c
151#define HVCALL_SIGNAL_EVENT 0x005d
152#define HVCALL_POST_DEBUG_DATA 0x0069
153#define HVCALL_RETRIEVE_DEBUG_DATA 0x006a
154#define HVCALL_RESET_DEBUG_SESSION 0x006b
155#define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076
156#define HVCALL_MAP_DEVICE_INTERRUPT 0x007c
157#define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d
158#define HVCALL_RETARGET_INTERRUPT 0x007e
159#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af
160#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0
161
162
163#define HV_EXT_CALL_QUERY_CAPABILITIES 0x8001
164#define HV_EXT_CALL_MEMORY_HEAT_HINT 0x8003
165
166#define HV_FLUSH_ALL_PROCESSORS BIT(0)
167#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1)
168#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2)
169#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3)
170
171
172#define HV_EXT_CAPABILITY_MEMORY_COLD_DISCARD_HINT BIT(8)
173
174enum HV_GENERIC_SET_FORMAT {
175 HV_GENERIC_SET_SPARSE_4K,
176 HV_GENERIC_SET_ALL,
177};
178
179#define HV_PARTITION_ID_SELF ((u64)-1)
180#define HV_VP_INDEX_SELF ((u32)-2)
181
182#define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0)
183#define HV_HYPERCALL_FAST_BIT BIT(16)
184#define HV_HYPERCALL_VARHEAD_OFFSET 17
185#define HV_HYPERCALL_REP_COMP_OFFSET 32
186#define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32)
187#define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32)
188#define HV_HYPERCALL_REP_START_OFFSET 48
189#define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48)
190
191
192#define HV_STATUS_SUCCESS 0
193#define HV_STATUS_INVALID_HYPERCALL_CODE 2
194#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
195#define HV_STATUS_INVALID_ALIGNMENT 4
196#define HV_STATUS_INVALID_PARAMETER 5
197#define HV_STATUS_OPERATION_DENIED 8
198#define HV_STATUS_INSUFFICIENT_MEMORY 11
199#define HV_STATUS_INVALID_PORT_ID 17
200#define HV_STATUS_INVALID_CONNECTION_ID 18
201#define HV_STATUS_INSUFFICIENT_BUFFERS 19
202
203
204
205
206
207#define HV_CLOCK_HZ (NSEC_PER_SEC/100)
208
209
210#define HV_SYNIC_SINT_COUNT (16)
211
212#define HV_SYNIC_VERSION_1 (0x1)
213
214#define HV_SYNIC_FIRST_VALID_VECTOR (16)
215
216#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0)
217#define HV_SYNIC_SIMP_ENABLE (1ULL << 0)
218#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0)
219#define HV_SYNIC_SINT_MASKED (1ULL << 16)
220#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17)
221#define HV_SYNIC_SINT_VECTOR_MASK (0xFF)
222
223#define HV_SYNIC_STIMER_COUNT (4)
224
225
226#define HV_MESSAGE_SIZE (256)
227#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
228#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
229
230
231
232
233
234
235
236
237
238enum hv_message_type {
239 HVMSG_NONE = 0x00000000,
240
241
242 HVMSG_UNMAPPED_GPA = 0x80000000,
243 HVMSG_GPA_INTERCEPT = 0x80000001,
244
245
246 HVMSG_TIMER_EXPIRED = 0x80000010,
247
248
249 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
250 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
251 HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
252
253
254 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
255
256
257 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000,
258 HVMSG_X64_MSR_INTERCEPT = 0x80010001,
259 HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
260 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
261 HVMSG_X64_APIC_EOI = 0x80010004,
262 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005
263};
264
265
266union hv_message_flags {
267 __u8 asu8;
268 struct {
269 __u8 msg_pending:1;
270 __u8 reserved:7;
271 } __packed;
272};
273
274
275union hv_port_id {
276 __u32 asu32;
277 struct {
278 __u32 id:24;
279 __u32 reserved:8;
280 } __packed u;
281};
282
283
284struct hv_message_header {
285 __u32 message_type;
286 __u8 payload_size;
287 union hv_message_flags message_flags;
288 __u8 reserved[2];
289 union {
290 __u64 sender;
291 union hv_port_id port;
292 };
293} __packed;
294
295
296struct hv_message {
297 struct hv_message_header header;
298 union {
299 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
300 } u;
301} __packed;
302
303
304struct hv_message_page {
305 struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
306} __packed;
307
308
309struct hv_timer_message_payload {
310 __u32 timer_index;
311 __u32 reserved;
312 __u64 expiration_time;
313 __u64 delivery_time;
314} __packed;
315
316
317
318#define HV_EVENT_FLAGS_COUNT (256 * 8)
319#define HV_EVENT_FLAGS_LONG_COUNT (256 / sizeof(unsigned long))
320
321
322
323
324union hv_stimer_config {
325 u64 as_uint64;
326 struct {
327 u64 enable:1;
328 u64 periodic:1;
329 u64 lazy:1;
330 u64 auto_enable:1;
331 u64 apic_vector:8;
332 u64 direct_mode:1;
333 u64 reserved_z0:3;
334 u64 sintx:4;
335 u64 reserved_z1:44;
336 } __packed;
337};
338
339
340
341union hv_synic_event_flags {
342 unsigned long flags[HV_EVENT_FLAGS_LONG_COUNT];
343};
344
345
346union hv_synic_scontrol {
347 u64 as_uint64;
348 struct {
349 u64 enable:1;
350 u64 reserved:63;
351 } __packed;
352};
353
354
355union hv_synic_sint {
356 u64 as_uint64;
357 struct {
358 u64 vector:8;
359 u64 reserved1:8;
360 u64 masked:1;
361 u64 auto_eoi:1;
362 u64 polling:1;
363 u64 reserved2:45;
364 } __packed;
365};
366
367
368union hv_synic_simp {
369 u64 as_uint64;
370 struct {
371 u64 simp_enabled:1;
372 u64 preserved:11;
373 u64 base_simp_gpa:52;
374 } __packed;
375};
376
377
378union hv_synic_siefp {
379 u64 as_uint64;
380 struct {
381 u64 siefp_enabled:1;
382 u64 preserved:11;
383 u64 base_siefp_gpa:52;
384 } __packed;
385};
386
387struct hv_vpset {
388 u64 format;
389 u64 valid_bank_mask;
390 u64 bank_contents[];
391} __packed;
392
393
394struct hv_send_ipi {
395 u32 vector;
396 u32 reserved;
397 u64 cpu_mask;
398} __packed;
399
400
401struct hv_send_ipi_ex {
402 u32 vector;
403 u32 reserved;
404 struct hv_vpset vp_set;
405} __packed;
406
407
408struct hv_guest_mapping_flush {
409 u64 address_space;
410 u64 flags;
411} __packed;
412
413
414
415
416
417#define HV_MAX_FLUSH_PAGES (2048)
418#define HV_GPA_PAGE_RANGE_PAGE_SIZE_2MB 0
419#define HV_GPA_PAGE_RANGE_PAGE_SIZE_1GB 1
420
421
422union hv_gpa_page_range {
423 u64 address_space;
424 struct {
425 u64 additional_pages:11;
426 u64 largepage:1;
427 u64 basepfn:52;
428 } page;
429 struct {
430 u64 reserved:12;
431 u64 page_size:1;
432 u64 reserved1:8;
433 u64 base_large_pfn:43;
434 };
435};
436
437
438
439
440
441
442#define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \
443 sizeof(union hv_gpa_page_range))
444
445struct hv_guest_mapping_flush_list {
446 u64 address_space;
447 u64 flags;
448 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT];
449};
450
451
452struct hv_tlb_flush {
453 u64 address_space;
454 u64 flags;
455 u64 processor_mask;
456 u64 gva_list[];
457} __packed;
458
459
460struct hv_tlb_flush_ex {
461 u64 address_space;
462 u64 flags;
463 struct hv_vpset hv_vp_set;
464 u64 gva_list[];
465} __packed;
466
467
468struct hv_get_partition_id {
469 u64 partition_id;
470} __packed;
471
472
473struct hv_deposit_memory {
474 u64 partition_id;
475 u64 gpa_page_list[];
476} __packed;
477
478struct hv_proximity_domain_flags {
479 u32 proximity_preferred : 1;
480 u32 reserved : 30;
481 u32 proximity_info_valid : 1;
482} __packed;
483
484
485union hv_proximity_domain_info {
486 struct {
487 u32 domain_id;
488 struct hv_proximity_domain_flags flags;
489 };
490 u64 as_uint64;
491} __packed;
492
493struct hv_lp_startup_status {
494 u64 hv_status;
495 u64 substatus1;
496 u64 substatus2;
497 u64 substatus3;
498 u64 substatus4;
499 u64 substatus5;
500 u64 substatus6;
501} __packed;
502
503
504struct hv_add_logical_processor_in {
505 u32 lp_index;
506 u32 apic_id;
507 union hv_proximity_domain_info proximity_domain_info;
508 u64 flags;
509} __packed;
510
511struct hv_add_logical_processor_out {
512 struct hv_lp_startup_status startup_status;
513} __packed;
514
515enum HV_SUBNODE_TYPE
516{
517 HvSubnodeAny = 0,
518 HvSubnodeSocket = 1,
519 HvSubnodeAmdNode = 2,
520 HvSubnodeL3 = 3,
521 HvSubnodeCount = 4,
522 HvSubnodeInvalid = -1
523};
524
525
526struct hv_create_vp {
527 u64 partition_id;
528 u32 vp_index;
529 u8 padding[3];
530 u8 subnode_type;
531 u64 subnode_id;
532 union hv_proximity_domain_info proximity_domain_info;
533 u64 flags;
534} __packed;
535
536enum hv_interrupt_source {
537 HV_INTERRUPT_SOURCE_MSI = 1,
538 HV_INTERRUPT_SOURCE_IOAPIC,
539};
540
541union hv_msi_address_register {
542 u32 as_uint32;
543 struct {
544 u32 reserved1:2;
545 u32 destination_mode:1;
546 u32 redirection_hint:1;
547 u32 reserved2:8;
548 u32 destination_id:8;
549 u32 msi_base:12;
550 };
551} __packed;
552
553union hv_msi_data_register {
554 u32 as_uint32;
555 struct {
556 u32 vector:8;
557 u32 delivery_mode:3;
558 u32 reserved1:3;
559 u32 level_assert:1;
560 u32 trigger_mode:1;
561 u32 reserved2:16;
562 };
563} __packed;
564
565
566union hv_msi_entry {
567 u64 as_uint64;
568 struct {
569 union hv_msi_address_register address;
570 union hv_msi_data_register data;
571 } __packed;
572};
573
574union hv_ioapic_rte {
575 u64 as_uint64;
576
577 struct {
578 u32 vector:8;
579 u32 delivery_mode:3;
580 u32 destination_mode:1;
581 u32 delivery_status:1;
582 u32 interrupt_polarity:1;
583 u32 remote_irr:1;
584 u32 trigger_mode:1;
585 u32 interrupt_mask:1;
586 u32 reserved1:15;
587
588 u32 reserved2:24;
589 u32 destination_id:8;
590 };
591
592 struct {
593 u32 low_uint32;
594 u32 high_uint32;
595 };
596} __packed;
597
598struct hv_interrupt_entry {
599 u32 source;
600 u32 reserved1;
601 union {
602 union hv_msi_entry msi_entry;
603 union hv_ioapic_rte ioapic_rte;
604 };
605} __packed;
606
607
608
609
610#define HV_DEVICE_INTERRUPT_TARGET_MULTICAST 1
611#define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET 2
612
613struct hv_device_interrupt_target {
614 u32 vector;
615 u32 flags;
616 union {
617 u64 vp_mask;
618 struct hv_vpset vp_set;
619 };
620} __packed;
621
622struct hv_retarget_device_interrupt {
623 u64 partition_id;
624 u64 device_id;
625 struct hv_interrupt_entry int_entry;
626 u64 reserved2;
627 struct hv_device_interrupt_target int_target;
628} __packed __aligned(8);
629
630
631
632struct hv_get_vp_registers_input {
633 struct {
634 u64 partitionid;
635 u32 vpindex;
636 u8 inputvtl;
637 u8 padding[3];
638 } header;
639 struct input {
640 u32 name0;
641 u32 name1;
642 } element[];
643} __packed;
644
645
646
647struct hv_get_vp_registers_output {
648 union {
649 struct {
650 u32 a;
651 u32 b;
652 u32 c;
653 u32 d;
654 } as32 __packed;
655 struct {
656 u64 low;
657 u64 high;
658 } as64 __packed;
659 };
660};
661
662
663struct hv_set_vp_registers_input {
664 struct {
665 u64 partitionid;
666 u32 vpindex;
667 u8 inputvtl;
668 u8 padding[3];
669 } header;
670 struct {
671 u32 name;
672 u32 padding1;
673 u64 padding2;
674 u64 valuelow;
675 u64 valuehigh;
676 } element[];
677} __packed;
678
679enum hv_device_type {
680 HV_DEVICE_TYPE_LOGICAL = 0,
681 HV_DEVICE_TYPE_PCI = 1,
682 HV_DEVICE_TYPE_IOAPIC = 2,
683 HV_DEVICE_TYPE_ACPI = 3,
684};
685
686typedef u16 hv_pci_rid;
687typedef u16 hv_pci_segment;
688typedef u64 hv_logical_device_id;
689union hv_pci_bdf {
690 u16 as_uint16;
691
692 struct {
693 u8 function:3;
694 u8 device:5;
695 u8 bus;
696 };
697} __packed;
698
699union hv_pci_bus_range {
700 u16 as_uint16;
701
702 struct {
703 u8 subordinate_bus;
704 u8 secondary_bus;
705 };
706} __packed;
707
708union hv_device_id {
709 u64 as_uint64;
710
711 struct {
712 u64 reserved0:62;
713 u64 device_type:2;
714 };
715
716
717 struct {
718 u64 id:62;
719 u64 device_type:2;
720 } logical;
721
722
723 struct {
724 union {
725 hv_pci_rid rid;
726 union hv_pci_bdf bdf;
727 };
728
729 hv_pci_segment segment;
730 union hv_pci_bus_range shadow_bus_range;
731
732 u16 phantom_function_bits:2;
733 u16 source_shadow:1;
734
735 u16 rsvdz0:11;
736 u16 device_type:2;
737 } pci;
738
739
740 struct {
741 u8 ioapic_id;
742 u8 rsvdz0;
743 u16 rsvdz1;
744 u16 rsvdz2;
745
746 u16 rsvdz3:14;
747 u16 device_type:2;
748 } ioapic;
749
750
751 struct {
752 u32 input_mapping_base;
753 u32 input_mapping_count:30;
754 u32 device_type:2;
755 } acpi;
756} __packed;
757
758enum hv_interrupt_trigger_mode {
759 HV_INTERRUPT_TRIGGER_MODE_EDGE = 0,
760 HV_INTERRUPT_TRIGGER_MODE_LEVEL = 1,
761};
762
763struct hv_device_interrupt_descriptor {
764 u32 interrupt_type;
765 u32 trigger_mode;
766 u32 vector_count;
767 u32 reserved;
768 struct hv_device_interrupt_target target;
769} __packed;
770
771struct hv_input_map_device_interrupt {
772 u64 partition_id;
773 u64 device_id;
774 u64 flags;
775 struct hv_interrupt_entry logical_interrupt_entry;
776 struct hv_device_interrupt_descriptor interrupt_descriptor;
777} __packed;
778
779struct hv_output_map_device_interrupt {
780 struct hv_interrupt_entry interrupt_entry;
781} __packed;
782
783struct hv_input_unmap_device_interrupt {
784 u64 partition_id;
785 u64 device_id;
786 struct hv_interrupt_entry interrupt_entry;
787} __packed;
788
789#define HV_SOURCE_SHADOW_NONE 0x0
790#define HV_SOURCE_SHADOW_BRIDGE_BUS_RANGE 0x1
791
792
793
794
795
796#define HV_MEMORY_HINT_MAX_GPA_PAGE_RANGES \
797 ((HV_HYP_PAGE_SIZE - sizeof(struct hv_memory_hint)) / \
798 sizeof(union hv_gpa_page_range))
799
800
801#define HV_EXT_MEMORY_HEAT_HINT_TYPE_COLD_DISCARD 2
802struct hv_memory_hint {
803 u64 type:2;
804 u64 reserved:62;
805 union hv_gpa_page_range ranges[];
806} __packed;
807
808#endif
809