1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 */ 5 6#ifndef _DT_BINDINGS_RESET_IPQ_806X_H 7#define _DT_BINDINGS_RESET_IPQ_806X_H 8 9#define QDSS_STM_RESET 0 10#define AFAB_SMPSS_S_RESET 1 11#define AFAB_SMPSS_M1_RESET 2 12#define AFAB_SMPSS_M0_RESET 3 13#define AFAB_EBI1_CH0_RESET 4 14#define AFAB_EBI1_CH1_RESET 5 15#define SFAB_ADM0_M0_RESET 6 16#define SFAB_ADM0_M1_RESET 7 17#define SFAB_ADM0_M2_RESET 8 18#define ADM0_C2_RESET 9 19#define ADM0_C1_RESET 10 20#define ADM0_C0_RESET 11 21#define ADM0_PBUS_RESET 12 22#define ADM0_RESET 13 23#define QDSS_CLKS_SW_RESET 14 24#define QDSS_POR_RESET 15 25#define QDSS_TSCTR_RESET 16 26#define QDSS_HRESET_RESET 17 27#define QDSS_AXI_RESET 18 28#define QDSS_DBG_RESET 19 29#define SFAB_PCIE_M_RESET 20 30#define SFAB_PCIE_S_RESET 21 31#define PCIE_EXT_RESET 22 32#define PCIE_PHY_RESET 23 33#define PCIE_PCI_RESET 24 34#define PCIE_POR_RESET 25 35#define PCIE_HCLK_RESET 26 36#define PCIE_ACLK_RESET 27 37#define SFAB_LPASS_RESET 28 38#define SFAB_AFAB_M_RESET 29 39#define AFAB_SFAB_M0_RESET 30 40#define AFAB_SFAB_M1_RESET 31 41#define SFAB_SATA_S_RESET 32 42#define SFAB_DFAB_M_RESET 33 43#define DFAB_SFAB_M_RESET 34 44#define DFAB_SWAY0_RESET 35 45#define DFAB_SWAY1_RESET 36 46#define DFAB_ARB0_RESET 37 47#define DFAB_ARB1_RESET 38 48#define PPSS_PROC_RESET 39 49#define PPSS_RESET 40 50#define DMA_BAM_RESET 41 51#define SPS_TIC_H_RESET 42 52#define SFAB_CFPB_M_RESET 43 53#define SFAB_CFPB_S_RESET 44 54#define TSIF_H_RESET 45 55#define CE1_H_RESET 46 56#define CE1_CORE_RESET 47 57#define CE1_SLEEP_RESET 48 58#define CE2_H_RESET 49 59#define CE2_CORE_RESET 50 60#define SFAB_SFPB_M_RESET 51 61#define SFAB_SFPB_S_RESET 52 62#define RPM_PROC_RESET 53 63#define PMIC_SSBI2_RESET 54 64#define SDC1_RESET 55 65#define SDC2_RESET 56 66#define SDC3_RESET 57 67#define SDC4_RESET 58 68#define USB_HS1_RESET 59 69#define USB_HSIC_RESET 60 70#define USB_FS1_XCVR_RESET 61 71#define USB_FS1_RESET 62 72#define GSBI1_RESET 63 73#define GSBI2_RESET 64 74#define GSBI3_RESET 65 75#define GSBI4_RESET 66 76#define GSBI5_RESET 67 77#define GSBI6_RESET 68 78#define GSBI7_RESET 69 79#define SPDM_RESET 70 80#define SEC_CTRL_RESET 71 81#define TLMM_H_RESET 72 82#define SFAB_SATA_M_RESET 73 83#define SATA_RESET 74 84#define TSSC_RESET 75 85#define PDM_RESET 76 86#define MPM_H_RESET 77 87#define MPM_RESET 78 88#define SFAB_SMPSS_S_RESET 79 89#define PRNG_RESET 80 90#define SFAB_CE3_M_RESET 81 91#define SFAB_CE3_S_RESET 82 92#define CE3_SLEEP_RESET 83 93#define PCIE_1_M_RESET 84 94#define PCIE_1_S_RESET 85 95#define PCIE_1_EXT_RESET 86 96#define PCIE_1_PHY_RESET 87 97#define PCIE_1_PCI_RESET 88 98#define PCIE_1_POR_RESET 89 99#define PCIE_1_HCLK_RESET 90 100#define PCIE_1_ACLK_RESET 91 101#define PCIE_2_M_RESET 92 102#define PCIE_2_S_RESET 93 103#define PCIE_2_EXT_RESET 94 104#define PCIE_2_PHY_RESET 95 105#define PCIE_2_PCI_RESET 96 106#define PCIE_2_POR_RESET 97 107#define PCIE_2_HCLK_RESET 98 108#define PCIE_2_ACLK_RESET 99 109#define SFAB_USB30_S_RESET 100 110#define SFAB_USB30_M_RESET 101 111#define USB30_0_PORT2_HS_PHY_RESET 102 112#define USB30_0_MASTER_RESET 103 113#define USB30_0_SLEEP_RESET 104 114#define USB30_0_UTMI_PHY_RESET 105 115#define USB30_0_POWERON_RESET 106 116#define USB30_0_PHY_RESET 107 117#define USB30_1_MASTER_RESET 108 118#define USB30_1_SLEEP_RESET 109 119#define USB30_1_UTMI_PHY_RESET 110 120#define USB30_1_POWERON_RESET 111 121#define USB30_1_PHY_RESET 112 122#define NSSFB0_RESET 113 123#define NSSFB1_RESET 114 124#define UBI32_CORE1_CLKRST_CLAMP_RESET 115 125#define UBI32_CORE1_CLAMP_RESET 116 126#define UBI32_CORE1_AHB_RESET 117 127#define UBI32_CORE1_AXI_RESET 118 128#define UBI32_CORE2_CLKRST_CLAMP_RESET 119 129#define UBI32_CORE2_CLAMP_RESET 120 130#define UBI32_CORE2_AHB_RESET 121 131#define UBI32_CORE2_AXI_RESET 122 132#define GMAC_CORE1_RESET 123 133#define GMAC_CORE2_RESET 124 134#define GMAC_CORE3_RESET 125 135#define GMAC_CORE4_RESET 126 136#define GMAC_AHB_RESET 127 137#define NSS_CH0_RST_RX_CLK_N_RESET 128 138#define NSS_CH0_RST_TX_CLK_N_RESET 129 139#define NSS_CH0_RST_RX_125M_N_RESET 130 140#define NSS_CH0_HW_RST_RX_125M_N_RESET 131 141#define NSS_CH0_RST_TX_125M_N_RESET 132 142#define NSS_CH1_RST_RX_CLK_N_RESET 133 143#define NSS_CH1_RST_TX_CLK_N_RESET 134 144#define NSS_CH1_RST_RX_125M_N_RESET 135 145#define NSS_CH1_HW_RST_RX_125M_N_RESET 136 146#define NSS_CH1_RST_TX_125M_N_RESET 137 147#define NSS_CH2_RST_RX_CLK_N_RESET 138 148#define NSS_CH2_RST_TX_CLK_N_RESET 139 149#define NSS_CH2_RST_RX_125M_N_RESET 140 150#define NSS_CH2_HW_RST_RX_125M_N_RESET 141 151#define NSS_CH2_RST_TX_125M_N_RESET 142 152#define NSS_CH3_RST_RX_CLK_N_RESET 143 153#define NSS_CH3_RST_TX_CLK_N_RESET 144 154#define NSS_CH3_RST_RX_125M_N_RESET 145 155#define NSS_CH3_HW_RST_RX_125M_N_RESET 146 156#define NSS_CH3_RST_TX_125M_N_RESET 147 157#define NSS_RST_RX_250M_125M_N_RESET 148 158#define NSS_RST_TX_250M_125M_N_RESET 149 159#define NSS_QSGMII_TXPI_RST_N_RESET 150 160#define NSS_QSGMII_CDR_RST_N_RESET 151 161#define NSS_SGMII2_CDR_RST_N_RESET 152 162#define NSS_SGMII3_CDR_RST_N_RESET 153 163#define NSS_CAL_PRBS_RST_N_RESET 154 164#define NSS_LCKDT_RST_N_RESET 155 165#define NSS_SRDS_N_RESET 156 166 167#endif 168