1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _LINUX_BRCMPHY_H 3#define _LINUX_BRCMPHY_H 4 5#include <linux/phy.h> 6 7/* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used 8 * to configure the switch internal registers via MDIO accesses. 9 */ 10#define BRCM_PSEUDO_PHY_ADDR 30 11 12#define PHY_ID_BCM50610 0x0143bd60 13#define PHY_ID_BCM50610M 0x0143bd70 14#define PHY_ID_BCM5241 0x0143bc30 15#define PHY_ID_BCMAC131 0x0143bc70 16#define PHY_ID_BCM5481 0x0143bca0 17#define PHY_ID_BCM5395 0x0143bcf0 18#define PHY_ID_BCM53125 0x03625f20 19#define PHY_ID_BCM54810 0x03625d00 20#define PHY_ID_BCM54811 0x03625cc0 21#define PHY_ID_BCM5482 0x0143bcb0 22#define PHY_ID_BCM5411 0x00206070 23#define PHY_ID_BCM5421 0x002060e0 24#define PHY_ID_BCM54210E 0x600d84a0 25#define PHY_ID_BCM5464 0x002060b0 26#define PHY_ID_BCM5461 0x002060c0 27#define PHY_ID_BCM54612E 0x03625e60 28#define PHY_ID_BCM54616S 0x03625d10 29#define PHY_ID_BCM54140 0xae025009 30#define PHY_ID_BCM57780 0x03625d90 31#define PHY_ID_BCM89610 0x03625cd0 32 33#define PHY_ID_BCM72113 0x35905310 34#define PHY_ID_BCM72116 0x35905350 35#define PHY_ID_BCM7250 0xae025280 36#define PHY_ID_BCM7255 0xae025120 37#define PHY_ID_BCM7260 0xae025190 38#define PHY_ID_BCM7268 0xae025090 39#define PHY_ID_BCM7271 0xae0253b0 40#define PHY_ID_BCM7278 0xae0251a0 41#define PHY_ID_BCM7364 0xae025260 42#define PHY_ID_BCM7366 0x600d8490 43#define PHY_ID_BCM7346 0x600d8650 44#define PHY_ID_BCM7362 0x600d84b0 45#define PHY_ID_BCM7425 0x600d86b0 46#define PHY_ID_BCM7429 0x600d8730 47#define PHY_ID_BCM7435 0x600d8750 48#define PHY_ID_BCM74371 0xae0252e0 49#define PHY_ID_BCM7439 0x600d8480 50#define PHY_ID_BCM7439_2 0xae025080 51#define PHY_ID_BCM7445 0x600d8510 52 53#define PHY_ID_BCM_CYGNUS 0xae025200 54#define PHY_ID_BCM_OMEGA 0xae025100 55 56#define PHY_BCM_OUI_MASK 0xfffffc00 57#define PHY_BCM_OUI_1 0x00206000 58#define PHY_BCM_OUI_2 0x0143bc00 59#define PHY_BCM_OUI_3 0x03625c00 60#define PHY_BCM_OUI_4 0x600d8400 61#define PHY_BCM_OUI_5 0x03625e00 62#define PHY_BCM_OUI_6 0xae025000 63 64#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000001 65#define PHY_BRCM_RX_REFCLK_UNUSED 0x00000002 66#define PHY_BRCM_CLEAR_RGMII_MODE 0x00000004 67#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00000008 68#define PHY_BRCM_EN_MASTER_MODE 0x00000010 69 70/* Broadcom BCM7xxx specific workarounds */ 71#define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff) 72#define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff) 73#define PHY_BCM_FLAGS_VALID 0x80000000 74 75/* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */ 76#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */ 77#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */ 78#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */ 79#define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIFO elasticity */ 80 81#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */ 82#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */ 83 84#define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ 85#define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ 86#define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ 87#define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ 88#define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */ 89 90#define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */ 91#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */ 92#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */ 93#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */ 94#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */ 95#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */ 96#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */ 97#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */ 98#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */ 99#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */ 100#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */ 101#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */ 102#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */ 103#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */ 104#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */ 105#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */ 106#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */ 107#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */ 108 109#define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ 110#define MII_BCM54XX_SHD_WRITE 0x8000 111#define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) 112#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) 113 114#define MII_BCM54XX_RDB_ADDR 0x1e 115#define MII_BCM54XX_RDB_DATA 0x1f 116 117/* legacy access control via rdb/expansion register */ 118#define BCM54XX_RDB_REG0087 0x0087 119#define BCM54XX_EXP_REG7E (MII_BCM54XX_EXP_SEL_ER + 0x7E) 120#define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15) 121 122/* 123 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18) 124 */ 125#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00 126#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400 127#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800 128#define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 0x4000 129 130#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07 131#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010 132#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080 133#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100 134#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200 135#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000 136 137#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12 138#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007 139 140/* 141 * Broadcom LED source encodings. These are used in BCM5461, BCM5481, 142 * BCM5482, and possibly some others. 143 */ 144#define BCM_LED_SRC_LINKSPD1 0x0 145#define BCM_LED_SRC_LINKSPD2 0x1 146#define BCM_LED_SRC_XMITLED 0x2 147#define BCM_LED_SRC_ACTIVITYLED 0x3 148#define BCM_LED_SRC_FDXLED 0x4 149#define BCM_LED_SRC_SLAVE 0x5 150#define BCM_LED_SRC_INTR 0x6 151#define BCM_LED_SRC_QUALITY 0x7 152#define BCM_LED_SRC_RCVLED 0x8 153#define BCM_LED_SRC_WIRESPEED 0x9 154#define BCM_LED_SRC_MULTICOLOR1 0xa 155#define BCM_LED_SRC_OPENSHORT 0xb 156#define BCM_LED_SRC_OFF 0xe /* Tied high */ 157#define BCM_LED_SRC_ON 0xf /* Tied low */ 158 159/* 160 * Broadcom Multicolor LED configurations (expansion register 4) 161 */ 162#define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04) 163#define BCM_LED_MULTICOLOR_IN_PHASE BIT(8) 164#define BCM_LED_MULTICOLOR_LINK_ACT 0x0 165#define BCM_LED_MULTICOLOR_SPEED 0x1 166#define BCM_LED_MULTICOLOR_ACT_FLASH 0x2 167#define BCM_LED_MULTICOLOR_FDX 0x3 168#define BCM_LED_MULTICOLOR_OFF 0x4 169#define BCM_LED_MULTICOLOR_ON 0x5 170#define BCM_LED_MULTICOLOR_ALT 0x6 171#define BCM_LED_MULTICOLOR_FLASH 0x7 172#define BCM_LED_MULTICOLOR_LINK 0x8 173#define BCM_LED_MULTICOLOR_ACT 0x9 174#define BCM_LED_MULTICOLOR_PROGRAM 0xa 175 176/* 177 * BCM5482: Shadow registers 178 * Shadow values go into bits [14:10] of register 0x1c to select a shadow 179 * register to access. 180 */ 181 182/* 00100: Reserved control register 2 */ 183#define BCM54XX_SHD_SCR2 0x04 184#define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100 185#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2 186#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2 187#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7 188 189/* 00101: Spare Control Register 3 */ 190#define BCM54XX_SHD_SCR3 0x05 191#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001 192#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002 193#define BCM54XX_SHD_SCR3_TRDDAPD 0x0004 194#define BCM54XX_SHD_SCR3_RXCTXC_DIS 0x0100 195 196/* 01010: Auto Power-Down */ 197#define BCM54XX_SHD_APD 0x0a 198#define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */ 199#define BCM54XX_SHD_APD_EN 0x0020 200#define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */ 201#define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */ 202 203#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */ 204 /* LED3 / ~LINKSPD[2] selector */ 205#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4) 206 /* LED1 / ~LINKSPD[1] selector */ 207#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0) 208#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */ 209#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */ 210#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */ 211#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */ 212 213/* 10011: SerDes 100-FX Control Register */ 214#define BCM54616S_SHD_100FX_CTRL 0x13 215#define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */ 216 217/* 11111: Mode Control Register */ 218#define BCM54XX_SHD_MODE 0x1f 219#define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */ 220#define BCM54XX_SHD_INTF_SEL_RGMII 0x02 221#define BCM54XX_SHD_INTF_SEL_SGMII 0x04 222#define BCM54XX_SHD_INTF_SEL_GBIC 0x06 223#define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */ 224 225/* 226 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17) 227 */ 228#define MII_BCM54XX_EXP_AADJ1CH0 0x001f 229#define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200 230#define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100 231#define MII_BCM54XX_EXP_AADJ1CH3 0x601f 232#define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002 233#define MII_BCM54XX_EXP_EXP08 0x0F08 234#define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001 235#define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200 236#define MII_BCM54XX_EXP_EXP75 0x0f75 237#define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c 238#define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001 239#define MII_BCM54XX_EXP_EXP96 0x0f96 240#define MII_BCM54XX_EXP_EXP96_MYST 0x0010 241#define MII_BCM54XX_EXP_EXP97 0x0f97 242#define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c 243 244/* 245 * BCM5482: Secondary SerDes registers 246 */ 247#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */ 248#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */ 249#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */ 250#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */ 251#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */ 252 253/* BCM54810 Registers */ 254#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90) 255#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0) 256#define BCM54810_SHD_CLK_CTL 0x3 257#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9) 258 259/* BCM54612E Registers */ 260#define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34) 261#define BCM54612E_LED4_CLK125OUT_EN (1 << 1) 262 263/*****************************************************************************/ 264/* Fast Ethernet Transceiver definitions. */ 265/*****************************************************************************/ 266 267#define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */ 268#define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */ 269#define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */ 270#define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */ 271#define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */ 272#define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */ 273 274#define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */ 275#define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */ 276 277 278/*** Shadow register definitions ***/ 279 280#define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */ 281#define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */ 282 283#define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */ 284#define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003 285#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001 286 287#define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */ 288#define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */ 289 290#define BRCM_CL45VEN_EEE_CONTROL 0x803d 291#define LPI_FEATURE_EN 0x8000 292#define LPI_FEATURE_EN_DIG1000X 0x4000 293 294/* Core register definitions*/ 295#define MII_BRCM_CORE_BASE12 0x12 296#define MII_BRCM_CORE_BASE13 0x13 297#define MII_BRCM_CORE_BASE14 0x14 298#define MII_BRCM_CORE_BASE1E 0x1E 299#define MII_BRCM_CORE_EXPB0 0xB0 300#define MII_BRCM_CORE_EXPB1 0xB1 301 302/* Enhanced Cable Diagnostics */ 303#define BCM54XX_RDB_ECD_CTRL 0x2a0 304#define BCM54XX_EXP_ECD_CTRL (MII_BCM54XX_EXP_SEL_ER + 0xc0) 305 306#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 1 /* CAT3 or worse */ 307#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 0 /* CAT5 or better */ 308#define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK BIT(0) /* cable type */ 309#define BCM54XX_ECD_CTRL_INVALID BIT(3) /* invalid result */ 310#define BCM54XX_ECD_CTRL_UNIT_CM 0 /* centimeters */ 311#define BCM54XX_ECD_CTRL_UNIT_M 1 /* meters */ 312#define BCM54XX_ECD_CTRL_UNIT_MASK BIT(10) /* cable length unit */ 313#define BCM54XX_ECD_CTRL_IN_PROGRESS BIT(11) /* test in progress */ 314#define BCM54XX_ECD_CTRL_BREAK_LINK BIT(12) /* unconnect link 315 * during test 316 */ 317#define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS BIT(13) /* disable inter-pair 318 * short check 319 */ 320#define BCM54XX_ECD_CTRL_RUN BIT(15) /* run immediate */ 321 322#define BCM54XX_RDB_ECD_FAULT_TYPE 0x2a1 323#define BCM54XX_EXP_ECD_FAULT_TYPE (MII_BCM54XX_EXP_SEL_ER + 0xc1) 324#define BCM54XX_ECD_FAULT_TYPE_INVALID 0x0 325#define BCM54XX_ECD_FAULT_TYPE_OK 0x1 326#define BCM54XX_ECD_FAULT_TYPE_OPEN 0x2 327#define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 0x3 /* short same pair */ 328#define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 0x4 /* short different pairs */ 329#define BCM54XX_ECD_FAULT_TYPE_BUSY 0x9 330#define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0) 331#define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4) 332#define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8) 333#define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12) 334#define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 0x2a2 335#define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 0x2a3 336#define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 0x2a4 337#define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 0x2a5 338 339#define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 0x2a2 340#define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc2) 341#define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 0x2a3 342#define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc3) 343#define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 0x2a4 344#define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc4) 345#define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 0x2a5 346#define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc5) 347#define BCM54XX_ECD_LENGTH_RESULTS_INVALID 0xffff 348 349#endif /* _LINUX_BRCMPHY_H */ 350