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13#ifndef _FSL_DEVICE_H_
14#define _FSL_DEVICE_H_
15
16#define FSL_UTMI_PHY_DLY 10
17
18#define FSL_USB_PHY_CLK_TIMEOUT 10000
19
20#include <linux/types.h>
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46enum fsl_usb2_controller_ver {
47 FSL_USB_VER_NONE = -1,
48 FSL_USB_VER_OLD = 0,
49 FSL_USB_VER_1_6 = 1,
50 FSL_USB_VER_2_2 = 2,
51 FSL_USB_VER_2_4 = 3,
52 FSL_USB_VER_2_5 = 4,
53};
54
55enum fsl_usb2_operating_modes {
56 FSL_USB2_MPH_HOST,
57 FSL_USB2_DR_HOST,
58 FSL_USB2_DR_DEVICE,
59 FSL_USB2_DR_OTG,
60};
61
62enum fsl_usb2_phy_modes {
63 FSL_USB2_PHY_NONE,
64 FSL_USB2_PHY_ULPI,
65 FSL_USB2_PHY_UTMI,
66 FSL_USB2_PHY_UTMI_WIDE,
67 FSL_USB2_PHY_SERIAL,
68 FSL_USB2_PHY_UTMI_DUAL,
69};
70
71struct clk;
72struct platform_device;
73
74struct fsl_usb2_platform_data {
75
76 enum fsl_usb2_controller_ver controller_ver;
77 enum fsl_usb2_operating_modes operating_mode;
78 enum fsl_usb2_phy_modes phy_mode;
79 unsigned int port_enables;
80 unsigned int workaround;
81
82 int (*init)(struct platform_device *);
83 void (*exit)(struct platform_device *);
84 void __iomem *regs;
85 struct clk *clk;
86 unsigned power_budget;
87 unsigned big_endian_mmio:1;
88 unsigned big_endian_desc:1;
89 unsigned es:1;
90 unsigned le_setup_buf:1;
91 unsigned have_sysif_regs:1;
92 unsigned invert_drvvbus:1;
93 unsigned invert_pwr_fault:1;
94
95 unsigned suspended:1;
96 unsigned already_suspended:1;
97 unsigned has_fsl_erratum_a007792:1;
98 unsigned has_fsl_erratum_14:1;
99 unsigned has_fsl_erratum_a005275:1;
100 unsigned has_fsl_erratum_a005697:1;
101 unsigned has_fsl_erratum_a006918:1;
102 unsigned check_phy_clk_valid:1;
103
104
105 u32 pm_command;
106 u32 pm_status;
107 u32 pm_intr_enable;
108 u32 pm_frame_index;
109 u32 pm_segment;
110 u32 pm_frame_list;
111 u32 pm_async_next;
112 u32 pm_configured_flag;
113 u32 pm_portsc;
114 u32 pm_usbgenctrl;
115};
116
117
118#define FSL_USB2_PORT0_ENABLED 0x00000001
119#define FSL_USB2_PORT1_ENABLED 0x00000002
120
121#define FLS_USB2_WORKAROUND_ENGCM09152 (1 << 0)
122
123struct spi_device;
124
125struct fsl_spi_platform_data {
126 u32 initial_spmode;
127 s16 bus_num;
128 unsigned int flags;
129#define SPI_QE_CPU_MODE (1 << 0)
130#define SPI_CPM_MODE (1 << 1)
131#define SPI_CPM1 (1 << 2)
132#define SPI_CPM2 (1 << 3)
133#define SPI_QE (1 << 4)
134
135 u16 max_chipselect;
136 void (*cs_control)(struct spi_device *spi, bool on);
137 u32 sysclk;
138};
139
140struct mpc8xx_pcmcia_ops {
141 void(*hw_ctrl)(int slot, int enable);
142 int(*voltage_set)(int slot, int vcc, int vpp);
143};
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149#if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
150int fsl_deep_sleep(void);
151#else
152static inline int fsl_deep_sleep(void) { return 0; }
153#endif
154
155#endif
156