linux/sound/soc/ti/omap-mcbsp.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   4 *
   5 * Copyright (C) 2008 Nokia Corporation
   6 *
   7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   8 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   9 */
  10
  11#include <linux/init.h>
  12#include <linux/module.h>
  13#include <linux/device.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/of.h>
  16#include <linux/of_device.h>
  17#include <sound/core.h>
  18#include <sound/pcm.h>
  19#include <sound/pcm_params.h>
  20#include <sound/initval.h>
  21#include <sound/soc.h>
  22#include <sound/dmaengine_pcm.h>
  23
  24#include "omap-mcbsp-priv.h"
  25#include "omap-mcbsp.h"
  26#include "sdma-pcm.h"
  27
  28#define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  29
  30enum {
  31        OMAP_MCBSP_WORD_8 = 0,
  32        OMAP_MCBSP_WORD_12,
  33        OMAP_MCBSP_WORD_16,
  34        OMAP_MCBSP_WORD_20,
  35        OMAP_MCBSP_WORD_24,
  36        OMAP_MCBSP_WORD_32,
  37};
  38
  39static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
  40{
  41        dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  42        dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n", MCBSP_READ(mcbsp, DRR2));
  43        dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n", MCBSP_READ(mcbsp, DRR1));
  44        dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n", MCBSP_READ(mcbsp, DXR2));
  45        dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n", MCBSP_READ(mcbsp, DXR1));
  46        dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
  47        dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
  48        dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n", MCBSP_READ(mcbsp, RCR2));
  49        dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n", MCBSP_READ(mcbsp, RCR1));
  50        dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n", MCBSP_READ(mcbsp, XCR2));
  51        dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n", MCBSP_READ(mcbsp, XCR1));
  52        dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
  53        dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
  54        dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n", MCBSP_READ(mcbsp, PCR0));
  55        dev_dbg(mcbsp->dev, "***********************\n");
  56}
  57
  58static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
  59{
  60        struct clk *fck_src;
  61        const char *src;
  62        int r;
  63
  64        if (fck_src_id == MCBSP_CLKS_PAD_SRC)
  65                src = "pad_fck";
  66        else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
  67                src = "prcm_fck";
  68        else
  69                return -EINVAL;
  70
  71        fck_src = clk_get(mcbsp->dev, src);
  72        if (IS_ERR(fck_src)) {
  73                dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
  74                return -EINVAL;
  75        }
  76
  77        pm_runtime_put_sync(mcbsp->dev);
  78
  79        r = clk_set_parent(mcbsp->fclk, fck_src);
  80        if (r)
  81                dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
  82                        src);
  83
  84        pm_runtime_get_sync(mcbsp->dev);
  85
  86        clk_put(fck_src);
  87
  88        return r;
  89}
  90
  91static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data)
  92{
  93        struct omap_mcbsp *mcbsp = data;
  94        u16 irqst;
  95
  96        irqst = MCBSP_READ(mcbsp, IRQST);
  97        dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
  98
  99        if (irqst & RSYNCERREN)
 100                dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
 101        if (irqst & RFSREN)
 102                dev_dbg(mcbsp->dev, "RX Frame Sync\n");
 103        if (irqst & REOFEN)
 104                dev_dbg(mcbsp->dev, "RX End Of Frame\n");
 105        if (irqst & RRDYEN)
 106                dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
 107        if (irqst & RUNDFLEN)
 108                dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
 109        if (irqst & ROVFLEN)
 110                dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
 111
 112        if (irqst & XSYNCERREN)
 113                dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
 114        if (irqst & XFSXEN)
 115                dev_dbg(mcbsp->dev, "TX Frame Sync\n");
 116        if (irqst & XEOFEN)
 117                dev_dbg(mcbsp->dev, "TX End Of Frame\n");
 118        if (irqst & XRDYEN)
 119                dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
 120        if (irqst & XUNDFLEN)
 121                dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
 122        if (irqst & XOVFLEN)
 123                dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
 124        if (irqst & XEMPTYEOFEN)
 125                dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
 126
 127        MCBSP_WRITE(mcbsp, IRQST, irqst);
 128
 129        return IRQ_HANDLED;
 130}
 131
 132static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data)
 133{
 134        struct omap_mcbsp *mcbsp = data;
 135        u16 irqst_spcr2;
 136
 137        irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
 138        dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 139
 140        if (irqst_spcr2 & XSYNC_ERR) {
 141                dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
 142                        irqst_spcr2);
 143                /* Writing zero to XSYNC_ERR clears the IRQ */
 144                MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
 145        }
 146
 147        return IRQ_HANDLED;
 148}
 149
 150static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data)
 151{
 152        struct omap_mcbsp *mcbsp = data;
 153        u16 irqst_spcr1;
 154
 155        irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
 156        dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 157
 158        if (irqst_spcr1 & RSYNC_ERR) {
 159                dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
 160                        irqst_spcr1);
 161                /* Writing zero to RSYNC_ERR clears the IRQ */
 162                MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
 163        }
 164
 165        return IRQ_HANDLED;
 166}
 167
 168/*
 169 * omap_mcbsp_config simply write a config to the
 170 * appropriate McBSP.
 171 * You either call this function or set the McBSP registers
 172 * by yourself before calling omap_mcbsp_start().
 173 */
 174static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
 175                              const struct omap_mcbsp_reg_cfg *config)
 176{
 177        dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 178                mcbsp->id, mcbsp->phys_base);
 179
 180        /* We write the given config */
 181        MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 182        MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 183        MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 184        MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 185        MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 186        MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 187        MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 188        MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 189        MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 190        MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 191        MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 192        if (mcbsp->pdata->has_ccr) {
 193                MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 194                MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 195        }
 196        /* Enable wakeup behavior */
 197        if (mcbsp->pdata->has_wakeup)
 198                MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 199
 200        /* Enable TX/RX sync error interrupts by default */
 201        if (mcbsp->irq)
 202                MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
 203                            RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
 204}
 205
 206/**
 207 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
 208 * @mcbsp: omap_mcbsp struct for the McBSP instance
 209 * @stream: Stream direction (playback/capture)
 210 *
 211 * Returns the address of mcbsp data transmit register or data receive register
 212 * to be used by DMA for transferring/receiving data
 213 */
 214static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
 215                                     unsigned int stream)
 216{
 217        int data_reg;
 218
 219        if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 220                if (mcbsp->pdata->reg_size == 2)
 221                        data_reg = OMAP_MCBSP_REG_DXR1;
 222                else
 223                        data_reg = OMAP_MCBSP_REG_DXR;
 224        } else {
 225                if (mcbsp->pdata->reg_size == 2)
 226                        data_reg = OMAP_MCBSP_REG_DRR1;
 227                else
 228                        data_reg = OMAP_MCBSP_REG_DRR;
 229        }
 230
 231        return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
 232}
 233
 234/*
 235 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 236 * The threshold parameter is 1 based, and it is converted (threshold - 1)
 237 * for the THRSH2 register.
 238 */
 239static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 240{
 241        if (threshold && threshold <= mcbsp->max_tx_thres)
 242                MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 243}
 244
 245/*
 246 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 247 * The threshold parameter is 1 based, and it is converted (threshold - 1)
 248 * for the THRSH1 register.
 249 */
 250static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 251{
 252        if (threshold && threshold <= mcbsp->max_rx_thres)
 253                MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 254}
 255
 256/*
 257 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 258 */
 259static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
 260{
 261        u16 buffstat;
 262
 263        /* Returns the number of free locations in the buffer */
 264        buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 265
 266        /* Number of slots are different in McBSP ports */
 267        return mcbsp->pdata->buffer_size - buffstat;
 268}
 269
 270/*
 271 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 272 * to reach the threshold value (when the DMA will be triggered to read it)
 273 */
 274static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
 275{
 276        u16 buffstat, threshold;
 277
 278        /* Returns the number of used locations in the buffer */
 279        buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 280        /* RX threshold */
 281        threshold = MCBSP_READ(mcbsp, THRSH1);
 282
 283        /* Return the number of location till we reach the threshold limit */
 284        if (threshold <= buffstat)
 285                return 0;
 286        else
 287                return threshold - buffstat;
 288}
 289
 290static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
 291{
 292        void *reg_cache;
 293        int err;
 294
 295        reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
 296        if (!reg_cache)
 297                return -ENOMEM;
 298
 299        spin_lock(&mcbsp->lock);
 300        if (!mcbsp->free) {
 301                dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
 302                err = -EBUSY;
 303                goto err_kfree;
 304        }
 305
 306        mcbsp->free = false;
 307        mcbsp->reg_cache = reg_cache;
 308        spin_unlock(&mcbsp->lock);
 309
 310        if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 311                mcbsp->pdata->ops->request(mcbsp->id - 1);
 312
 313        /*
 314         * Make sure that transmitter, receiver and sample-rate generator are
 315         * not running before activating IRQs.
 316         */
 317        MCBSP_WRITE(mcbsp, SPCR1, 0);
 318        MCBSP_WRITE(mcbsp, SPCR2, 0);
 319
 320        if (mcbsp->irq) {
 321                err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
 322                                  "McBSP", (void *)mcbsp);
 323                if (err != 0) {
 324                        dev_err(mcbsp->dev, "Unable to request IRQ\n");
 325                        goto err_clk_disable;
 326                }
 327        } else {
 328                err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
 329                                  "McBSP TX", (void *)mcbsp);
 330                if (err != 0) {
 331                        dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
 332                        goto err_clk_disable;
 333                }
 334
 335                err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
 336                                  "McBSP RX", (void *)mcbsp);
 337                if (err != 0) {
 338                        dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
 339                        goto err_free_irq;
 340                }
 341        }
 342
 343        return 0;
 344err_free_irq:
 345        free_irq(mcbsp->tx_irq, (void *)mcbsp);
 346err_clk_disable:
 347        if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 348                mcbsp->pdata->ops->free(mcbsp->id - 1);
 349
 350        /* Disable wakeup behavior */
 351        if (mcbsp->pdata->has_wakeup)
 352                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 353
 354        spin_lock(&mcbsp->lock);
 355        mcbsp->free = true;
 356        mcbsp->reg_cache = NULL;
 357err_kfree:
 358        spin_unlock(&mcbsp->lock);
 359        kfree(reg_cache);
 360
 361        return err;
 362}
 363
 364static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
 365{
 366        void *reg_cache;
 367
 368        if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 369                mcbsp->pdata->ops->free(mcbsp->id - 1);
 370
 371        /* Disable wakeup behavior */
 372        if (mcbsp->pdata->has_wakeup)
 373                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 374
 375        /* Disable interrupt requests */
 376        if (mcbsp->irq) {
 377                MCBSP_WRITE(mcbsp, IRQEN, 0);
 378
 379                free_irq(mcbsp->irq, (void *)mcbsp);
 380        } else {
 381                free_irq(mcbsp->rx_irq, (void *)mcbsp);
 382                free_irq(mcbsp->tx_irq, (void *)mcbsp);
 383        }
 384
 385        reg_cache = mcbsp->reg_cache;
 386
 387        /*
 388         * Select CLKS source from internal source unconditionally before
 389         * marking the McBSP port as free.
 390         * If the external clock source via MCBSP_CLKS pin has been selected the
 391         * system will refuse to enter idle if the CLKS pin source is not reset
 392         * back to internal source.
 393         */
 394        if (!mcbsp_omap1())
 395                omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
 396
 397        spin_lock(&mcbsp->lock);
 398        if (mcbsp->free)
 399                dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 400        else
 401                mcbsp->free = true;
 402        mcbsp->reg_cache = NULL;
 403        spin_unlock(&mcbsp->lock);
 404
 405        kfree(reg_cache);
 406}
 407
 408/*
 409 * Here we start the McBSP, by enabling transmitter, receiver or both.
 410 * If no transmitter or receiver is active prior calling, then sample-rate
 411 * generator and frame sync are started.
 412 */
 413static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
 414{
 415        int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
 416        int rx = !tx;
 417        int enable_srg = 0;
 418        u16 w;
 419
 420        if (mcbsp->st_data)
 421                omap_mcbsp_st_start(mcbsp);
 422
 423        /* Only enable SRG, if McBSP is master */
 424        w = MCBSP_READ_CACHE(mcbsp, PCR0);
 425        if (w & (FSXM | FSRM | CLKXM | CLKRM))
 426                enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 427                                MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 428
 429        if (enable_srg) {
 430                /* Start the sample generator */
 431                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 432                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 433        }
 434
 435        /* Enable transmitter and receiver */
 436        tx &= 1;
 437        w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 438        MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 439
 440        rx &= 1;
 441        w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 442        MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 443
 444        /*
 445         * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 446         * REVISIT: 100us may give enough time for two CLKSRG, however
 447         * due to some unknown PM related, clock gating etc. reason it
 448         * is now at 500us.
 449         */
 450        udelay(500);
 451
 452        if (enable_srg) {
 453                /* Start frame sync */
 454                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 455                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 456        }
 457
 458        if (mcbsp->pdata->has_ccr) {
 459                /* Release the transmitter and receiver */
 460                w = MCBSP_READ_CACHE(mcbsp, XCCR);
 461                w &= ~(tx ? XDISABLE : 0);
 462                MCBSP_WRITE(mcbsp, XCCR, w);
 463                w = MCBSP_READ_CACHE(mcbsp, RCCR);
 464                w &= ~(rx ? RDISABLE : 0);
 465                MCBSP_WRITE(mcbsp, RCCR, w);
 466        }
 467
 468        /* Dump McBSP Regs */
 469        omap_mcbsp_dump_reg(mcbsp);
 470}
 471
 472static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
 473{
 474        int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
 475        int rx = !tx;
 476        int idle;
 477        u16 w;
 478
 479        /* Reset transmitter */
 480        tx &= 1;
 481        if (mcbsp->pdata->has_ccr) {
 482                w = MCBSP_READ_CACHE(mcbsp, XCCR);
 483                w |= (tx ? XDISABLE : 0);
 484                MCBSP_WRITE(mcbsp, XCCR, w);
 485        }
 486        w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 487        MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 488
 489        /* Reset receiver */
 490        rx &= 1;
 491        if (mcbsp->pdata->has_ccr) {
 492                w = MCBSP_READ_CACHE(mcbsp, RCCR);
 493                w |= (rx ? RDISABLE : 0);
 494                MCBSP_WRITE(mcbsp, RCCR, w);
 495        }
 496        w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 497        MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 498
 499        idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 500                        MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 501
 502        if (idle) {
 503                /* Reset the sample rate generator */
 504                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 505                MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 506        }
 507
 508        if (mcbsp->st_data)
 509                omap_mcbsp_st_stop(mcbsp);
 510}
 511
 512#define max_thres(m)                    (mcbsp->pdata->buffer_size)
 513#define valid_threshold(m, val)         ((val) <= max_thres(m))
 514#define THRESHOLD_PROP_BUILDER(prop)                                    \
 515static ssize_t prop##_show(struct device *dev,                          \
 516                        struct device_attribute *attr, char *buf)       \
 517{                                                                       \
 518        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 519                                                                        \
 520        return sprintf(buf, "%u\n", mcbsp->prop);                       \
 521}                                                                       \
 522                                                                        \
 523static ssize_t prop##_store(struct device *dev,                         \
 524                                struct device_attribute *attr,          \
 525                                const char *buf, size_t size)           \
 526{                                                                       \
 527        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 528        unsigned long val;                                              \
 529        int status;                                                     \
 530                                                                        \
 531        status = kstrtoul(buf, 0, &val);                                \
 532        if (status)                                                     \
 533                return status;                                          \
 534                                                                        \
 535        if (!valid_threshold(mcbsp, val))                               \
 536                return -EDOM;                                           \
 537                                                                        \
 538        mcbsp->prop = val;                                              \
 539        return size;                                                    \
 540}                                                                       \
 541                                                                        \
 542static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store)
 543
 544THRESHOLD_PROP_BUILDER(max_tx_thres);
 545THRESHOLD_PROP_BUILDER(max_rx_thres);
 546
 547static const char * const dma_op_modes[] = {
 548        "element", "threshold",
 549};
 550
 551static ssize_t dma_op_mode_show(struct device *dev,
 552                                struct device_attribute *attr, char *buf)
 553{
 554        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 555        int dma_op_mode, i = 0;
 556        ssize_t len = 0;
 557        const char * const *s;
 558
 559        dma_op_mode = mcbsp->dma_op_mode;
 560
 561        for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
 562                if (dma_op_mode == i)
 563                        len += sprintf(buf + len, "[%s] ", *s);
 564                else
 565                        len += sprintf(buf + len, "%s ", *s);
 566        }
 567        len += sprintf(buf + len, "\n");
 568
 569        return len;
 570}
 571
 572static ssize_t dma_op_mode_store(struct device *dev,
 573                                 struct device_attribute *attr, const char *buf,
 574                                 size_t size)
 575{
 576        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 577        int i;
 578
 579        i = sysfs_match_string(dma_op_modes, buf);
 580        if (i < 0)
 581                return i;
 582
 583        spin_lock_irq(&mcbsp->lock);
 584        if (!mcbsp->free) {
 585                size = -EBUSY;
 586                goto unlock;
 587        }
 588        mcbsp->dma_op_mode = i;
 589
 590unlock:
 591        spin_unlock_irq(&mcbsp->lock);
 592
 593        return size;
 594}
 595
 596static DEVICE_ATTR_RW(dma_op_mode);
 597
 598static const struct attribute *additional_attrs[] = {
 599        &dev_attr_max_tx_thres.attr,
 600        &dev_attr_max_rx_thres.attr,
 601        &dev_attr_dma_op_mode.attr,
 602        NULL,
 603};
 604
 605static const struct attribute_group additional_attr_group = {
 606        .attrs = (struct attribute **)additional_attrs,
 607};
 608
 609/*
 610 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 611 * 730 has only 2 McBSP, and both of them are MPU peripherals.
 612 */
 613static int omap_mcbsp_init(struct platform_device *pdev)
 614{
 615        struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 616        struct resource *res;
 617        int ret = 0;
 618
 619        spin_lock_init(&mcbsp->lock);
 620        mcbsp->free = true;
 621
 622        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
 623        if (!res)
 624                res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 625
 626        mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
 627        if (IS_ERR(mcbsp->io_base))
 628                return PTR_ERR(mcbsp->io_base);
 629
 630        mcbsp->phys_base = res->start;
 631        mcbsp->reg_cache_size = resource_size(res);
 632
 633        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 634        if (!res)
 635                mcbsp->phys_dma_base = mcbsp->phys_base;
 636        else
 637                mcbsp->phys_dma_base = res->start;
 638
 639        /*
 640         * OMAP1, 2 uses two interrupt lines: TX, RX
 641         * OMAP2430, OMAP3 SoC have combined IRQ line as well.
 642         * OMAP4 and newer SoC only have the combined IRQ line.
 643         * Use the combined IRQ if available since it gives better debugging
 644         * possibilities.
 645         */
 646        mcbsp->irq = platform_get_irq_byname(pdev, "common");
 647        if (mcbsp->irq == -ENXIO) {
 648                mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
 649
 650                if (mcbsp->tx_irq == -ENXIO) {
 651                        mcbsp->irq = platform_get_irq(pdev, 0);
 652                        mcbsp->tx_irq = 0;
 653                } else {
 654                        mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
 655                        mcbsp->irq = 0;
 656                }
 657        }
 658
 659        if (!pdev->dev.of_node) {
 660                res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
 661                if (!res) {
 662                        dev_err(&pdev->dev, "invalid tx DMA channel\n");
 663                        return -ENODEV;
 664                }
 665                mcbsp->dma_req[0] = res->start;
 666                mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
 667
 668                res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
 669                if (!res) {
 670                        dev_err(&pdev->dev, "invalid rx DMA channel\n");
 671                        return -ENODEV;
 672                }
 673                mcbsp->dma_req[1] = res->start;
 674                mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
 675        } else {
 676                mcbsp->dma_data[0].filter_data = "tx";
 677                mcbsp->dma_data[1].filter_data = "rx";
 678        }
 679
 680        mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
 681                                                SNDRV_PCM_STREAM_PLAYBACK);
 682        mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
 683                                                SNDRV_PCM_STREAM_CAPTURE);
 684
 685        mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
 686        if (IS_ERR(mcbsp->fclk)) {
 687                ret = PTR_ERR(mcbsp->fclk);
 688                dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
 689                return ret;
 690        }
 691
 692        mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
 693        if (mcbsp->pdata->buffer_size) {
 694                /*
 695                 * Initially configure the maximum thresholds to a safe value.
 696                 * The McBSP FIFO usage with these values should not go under
 697                 * 16 locations.
 698                 * If the whole FIFO without safety buffer is used, than there
 699                 * is a possibility that the DMA will be not able to push the
 700                 * new data on time, causing channel shifts in runtime.
 701                 */
 702                mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
 703                mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
 704
 705                ret = sysfs_create_group(&mcbsp->dev->kobj,
 706                                         &additional_attr_group);
 707                if (ret) {
 708                        dev_err(mcbsp->dev,
 709                                "Unable to create additional controls\n");
 710                        return ret;
 711                }
 712        }
 713
 714        ret = omap_mcbsp_st_init(pdev);
 715        if (ret)
 716                goto err_st;
 717
 718        return 0;
 719
 720err_st:
 721        if (mcbsp->pdata->buffer_size)
 722                sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
 723        return ret;
 724}
 725
 726/*
 727 * Stream DMA parameters. DMA request line and port address are set runtime
 728 * since they are different between OMAP1 and later OMAPs
 729 */
 730static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
 731                unsigned int packet_size)
 732{
 733        struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 734        struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
 735        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 736        int words;
 737
 738        /* No need to proceed further if McBSP does not have FIFO */
 739        if (mcbsp->pdata->buffer_size == 0)
 740                return;
 741
 742        /*
 743         * Configure McBSP threshold based on either:
 744         * packet_size, when the sDMA is in packet mode, or based on the
 745         * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
 746         * for mono streams.
 747         */
 748        if (packet_size)
 749                words = packet_size;
 750        else
 751                words = 1;
 752
 753        /* Configure McBSP internal buffer usage */
 754        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 755                omap_mcbsp_set_tx_threshold(mcbsp, words);
 756        else
 757                omap_mcbsp_set_rx_threshold(mcbsp, words);
 758}
 759
 760static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
 761                                    struct snd_pcm_hw_rule *rule)
 762{
 763        struct snd_interval *buffer_size = hw_param_interval(params,
 764                                        SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 765        struct snd_interval *channels = hw_param_interval(params,
 766                                        SNDRV_PCM_HW_PARAM_CHANNELS);
 767        struct omap_mcbsp *mcbsp = rule->private;
 768        struct snd_interval frames;
 769        int size;
 770
 771        snd_interval_any(&frames);
 772        size = mcbsp->pdata->buffer_size;
 773
 774        frames.min = size / channels->min;
 775        frames.integer = 1;
 776        return snd_interval_refine(buffer_size, &frames);
 777}
 778
 779static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 780                                  struct snd_soc_dai *cpu_dai)
 781{
 782        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 783        int err = 0;
 784
 785        if (!snd_soc_dai_active(cpu_dai))
 786                err = omap_mcbsp_request(mcbsp);
 787
 788        /*
 789         * OMAP3 McBSP FIFO is word structured.
 790         * McBSP2 has 1024 + 256 = 1280 word long buffer,
 791         * McBSP1,3,4,5 has 128 word long buffer
 792         * This means that the size of the FIFO depends on the sample format.
 793         * For example on McBSP3:
 794         * 16bit samples: size is 128 * 2 = 256 bytes
 795         * 32bit samples: size is 128 * 4 = 512 bytes
 796         * It is simpler to place constraint for buffer and period based on
 797         * channels.
 798         * McBSP3 as example again (16 or 32 bit samples):
 799         * 1 channel (mono): size is 128 frames (128 words)
 800         * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 801         * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 802         */
 803        if (mcbsp->pdata->buffer_size) {
 804                /*
 805                * Rule for the buffer size. We should not allow
 806                * smaller buffer than the FIFO size to avoid underruns.
 807                * This applies only for the playback stream.
 808                */
 809                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 810                        snd_pcm_hw_rule_add(substream->runtime, 0,
 811                                            SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 812                                            omap_mcbsp_hwrule_min_buffersize,
 813                                            mcbsp,
 814                                            SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 815
 816                /* Make sure, that the period size is always even */
 817                snd_pcm_hw_constraint_step(substream->runtime, 0,
 818                                           SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 819        }
 820
 821        return err;
 822}
 823
 824static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 825                                    struct snd_soc_dai *cpu_dai)
 826{
 827        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 828        int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 829        int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
 830        int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
 831
 832        if (mcbsp->latency[stream2])
 833                cpu_latency_qos_update_request(&mcbsp->pm_qos_req,
 834                                               mcbsp->latency[stream2]);
 835        else if (mcbsp->latency[stream1])
 836                cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
 837
 838        mcbsp->latency[stream1] = 0;
 839
 840        if (!snd_soc_dai_active(cpu_dai)) {
 841                omap_mcbsp_free(mcbsp);
 842                mcbsp->configured = 0;
 843        }
 844}
 845
 846static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
 847                                  struct snd_soc_dai *cpu_dai)
 848{
 849        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 850        struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
 851        int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 852        int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
 853        int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
 854        int latency = mcbsp->latency[stream2];
 855
 856        /* Prevent omap hardware from hitting off between FIFO fills */
 857        if (!latency || mcbsp->latency[stream1] < latency)
 858                latency = mcbsp->latency[stream1];
 859
 860        if (cpu_latency_qos_request_active(pm_qos_req))
 861                cpu_latency_qos_update_request(pm_qos_req, latency);
 862        else if (latency)
 863                cpu_latency_qos_add_request(pm_qos_req, latency);
 864
 865        return 0;
 866}
 867
 868static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 869                                  struct snd_soc_dai *cpu_dai)
 870{
 871        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 872
 873        switch (cmd) {
 874        case SNDRV_PCM_TRIGGER_START:
 875        case SNDRV_PCM_TRIGGER_RESUME:
 876        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 877                mcbsp->active++;
 878                omap_mcbsp_start(mcbsp, substream->stream);
 879                break;
 880
 881        case SNDRV_PCM_TRIGGER_STOP:
 882        case SNDRV_PCM_TRIGGER_SUSPEND:
 883        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 884                omap_mcbsp_stop(mcbsp, substream->stream);
 885                mcbsp->active--;
 886                break;
 887        default:
 888                return -EINVAL;
 889        }
 890
 891        return 0;
 892}
 893
 894static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 895                        struct snd_pcm_substream *substream,
 896                        struct snd_soc_dai *dai)
 897{
 898        struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 899        struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
 900        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 901        u16 fifo_use;
 902        snd_pcm_sframes_t delay;
 903
 904        /* No need to proceed further if McBSP does not have FIFO */
 905        if (mcbsp->pdata->buffer_size == 0)
 906                return 0;
 907
 908        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 909                fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
 910        else
 911                fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
 912
 913        /*
 914         * Divide the used locations with the channel count to get the
 915         * FIFO usage in samples (don't care about partial samples in the
 916         * buffer).
 917         */
 918        delay = fifo_use / substream->runtime->channels;
 919
 920        return delay;
 921}
 922
 923static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 924                                    struct snd_pcm_hw_params *params,
 925                                    struct snd_soc_dai *cpu_dai)
 926{
 927        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 928        struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 929        struct snd_dmaengine_dai_dma_data *dma_data;
 930        int wlen, channels, wpf;
 931        int pkt_size = 0;
 932        unsigned int format, div, framesize, master;
 933        unsigned int buffer_size = mcbsp->pdata->buffer_size;
 934
 935        dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
 936        channels = params_channels(params);
 937
 938        switch (params_format(params)) {
 939        case SNDRV_PCM_FORMAT_S16_LE:
 940                wlen = 16;
 941                break;
 942        case SNDRV_PCM_FORMAT_S32_LE:
 943                wlen = 32;
 944                break;
 945        default:
 946                return -EINVAL;
 947        }
 948        if (buffer_size) {
 949                int latency;
 950
 951                if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 952                        int period_words, max_thrsh;
 953                        int divider = 0;
 954
 955                        period_words = params_period_bytes(params) / (wlen / 8);
 956                        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 957                                max_thrsh = mcbsp->max_tx_thres;
 958                        else
 959                                max_thrsh = mcbsp->max_rx_thres;
 960                        /*
 961                         * Use sDMA packet mode if McBSP is in threshold mode:
 962                         * If period words less than the FIFO size the packet
 963                         * size is set to the number of period words, otherwise
 964                         * Look for the biggest threshold value which divides
 965                         * the period size evenly.
 966                         */
 967                        divider = period_words / max_thrsh;
 968                        if (period_words % max_thrsh)
 969                                divider++;
 970                        while (period_words % divider &&
 971                                divider < period_words)
 972                                divider++;
 973                        if (divider == period_words)
 974                                return -EINVAL;
 975
 976                        pkt_size = period_words / divider;
 977                } else if (channels > 1) {
 978                        /* Use packet mode for non mono streams */
 979                        pkt_size = channels;
 980                }
 981
 982                latency = (buffer_size - pkt_size) / channels;
 983                latency = latency * USEC_PER_SEC /
 984                          (params->rate_num / params->rate_den);
 985                mcbsp->latency[substream->stream] = latency;
 986
 987                omap_mcbsp_set_threshold(substream, pkt_size);
 988        }
 989
 990        dma_data->maxburst = pkt_size;
 991
 992        if (mcbsp->configured) {
 993                /* McBSP already configured by another stream */
 994                return 0;
 995        }
 996
 997        regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
 998        regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
 999        regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
1000        regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
1001        format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1002        wpf = channels;
1003        if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
1004                              format == SND_SOC_DAIFMT_LEFT_J)) {
1005                /* Use dual-phase frames */
1006                regs->rcr2      |= RPHASE;
1007                regs->xcr2      |= XPHASE;
1008                /* Set 1 word per (McBSP) frame for phase1 and phase2 */
1009                wpf--;
1010                regs->rcr2      |= RFRLEN2(wpf - 1);
1011                regs->xcr2      |= XFRLEN2(wpf - 1);
1012        }
1013
1014        regs->rcr1      |= RFRLEN1(wpf - 1);
1015        regs->xcr1      |= XFRLEN1(wpf - 1);
1016
1017        switch (params_format(params)) {
1018        case SNDRV_PCM_FORMAT_S16_LE:
1019                /* Set word lengths */
1020                regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
1021                regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
1022                regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
1023                regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
1024                break;
1025        case SNDRV_PCM_FORMAT_S32_LE:
1026                /* Set word lengths */
1027                regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
1028                regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
1029                regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
1030                regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
1031                break;
1032        default:
1033                /* Unsupported PCM format */
1034                return -EINVAL;
1035        }
1036
1037        /* In McBSP master modes, FRAME (i.e. sample rate) is generated
1038         * by _counting_ BCLKs. Calculate frame size in BCLKs */
1039        master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
1040        if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
1041                div = mcbsp->clk_div ? mcbsp->clk_div : 1;
1042                framesize = (mcbsp->in_freq / div) / params_rate(params);
1043
1044                if (framesize < wlen * channels) {
1045                        printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
1046                                        "channels\n", __func__);
1047                        return -EINVAL;
1048                }
1049        } else
1050                framesize = wlen * channels;
1051
1052        /* Set FS period and length in terms of bit clock periods */
1053        regs->srgr2     &= ~FPER(0xfff);
1054        regs->srgr1     &= ~FWID(0xff);
1055        switch (format) {
1056        case SND_SOC_DAIFMT_I2S:
1057        case SND_SOC_DAIFMT_LEFT_J:
1058                regs->srgr2     |= FPER(framesize - 1);
1059                regs->srgr1     |= FWID((framesize >> 1) - 1);
1060                break;
1061        case SND_SOC_DAIFMT_DSP_A:
1062        case SND_SOC_DAIFMT_DSP_B:
1063                regs->srgr2     |= FPER(framesize - 1);
1064                regs->srgr1     |= FWID(0);
1065                break;
1066        }
1067
1068        omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
1069        mcbsp->wlen = wlen;
1070        mcbsp->configured = 1;
1071
1072        return 0;
1073}
1074
1075/*
1076 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
1077 * cache is initialized here
1078 */
1079static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
1080                                      unsigned int fmt)
1081{
1082        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1083        struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1084        bool inv_fs = false;
1085
1086        if (mcbsp->configured)
1087                return 0;
1088
1089        mcbsp->fmt = fmt;
1090        memset(regs, 0, sizeof(*regs));
1091        /* Generic McBSP register settings */
1092        regs->spcr2     |= XINTM(3) | FREE;
1093        regs->spcr1     |= RINTM(3);
1094        /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
1095        if (!mcbsp->pdata->has_ccr) {
1096                regs->rcr2      |= RFIG;
1097                regs->xcr2      |= XFIG;
1098        }
1099
1100        /* Configure XCCR/RCCR only for revisions which have ccr registers */
1101        if (mcbsp->pdata->has_ccr) {
1102                regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
1103                regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
1104        }
1105
1106        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1107        case SND_SOC_DAIFMT_I2S:
1108                /* 1-bit data delay */
1109                regs->rcr2      |= RDATDLY(1);
1110                regs->xcr2      |= XDATDLY(1);
1111                break;
1112        case SND_SOC_DAIFMT_LEFT_J:
1113                /* 0-bit data delay */
1114                regs->rcr2      |= RDATDLY(0);
1115                regs->xcr2      |= XDATDLY(0);
1116                regs->spcr1     |= RJUST(2);
1117                /* Invert FS polarity configuration */
1118                inv_fs = true;
1119                break;
1120        case SND_SOC_DAIFMT_DSP_A:
1121                /* 1-bit data delay */
1122                regs->rcr2      |= RDATDLY(1);
1123                regs->xcr2      |= XDATDLY(1);
1124                /* Invert FS polarity configuration */
1125                inv_fs = true;
1126                break;
1127        case SND_SOC_DAIFMT_DSP_B:
1128                /* 0-bit data delay */
1129                regs->rcr2      |= RDATDLY(0);
1130                regs->xcr2      |= XDATDLY(0);
1131                /* Invert FS polarity configuration */
1132                inv_fs = true;
1133                break;
1134        default:
1135                /* Unsupported data format */
1136                return -EINVAL;
1137        }
1138
1139        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1140        case SND_SOC_DAIFMT_CBS_CFS:
1141                /* McBSP master. Set FS and bit clocks as outputs */
1142                regs->pcr0      |= FSXM | FSRM |
1143                                   CLKXM | CLKRM;
1144                /* Sample rate generator drives the FS */
1145                regs->srgr2     |= FSGM;
1146                break;
1147        case SND_SOC_DAIFMT_CBM_CFS:
1148                /* McBSP slave. FS clock as output */
1149                regs->srgr2     |= FSGM;
1150                regs->pcr0      |= FSXM | FSRM;
1151                break;
1152        case SND_SOC_DAIFMT_CBM_CFM:
1153                /* McBSP slave */
1154                break;
1155        default:
1156                /* Unsupported master/slave configuration */
1157                return -EINVAL;
1158        }
1159
1160        /* Set bit clock (CLKX/CLKR) and FS polarities */
1161        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1162        case SND_SOC_DAIFMT_NB_NF:
1163                /*
1164                 * Normal BCLK + FS.
1165                 * FS active low. TX data driven on falling edge of bit clock
1166                 * and RX data sampled on rising edge of bit clock.
1167                 */
1168                regs->pcr0      |= FSXP | FSRP |
1169                                   CLKXP | CLKRP;
1170                break;
1171        case SND_SOC_DAIFMT_NB_IF:
1172                regs->pcr0      |= CLKXP | CLKRP;
1173                break;
1174        case SND_SOC_DAIFMT_IB_NF:
1175                regs->pcr0      |= FSXP | FSRP;
1176                break;
1177        case SND_SOC_DAIFMT_IB_IF:
1178                break;
1179        default:
1180                return -EINVAL;
1181        }
1182        if (inv_fs)
1183                regs->pcr0 ^= FSXP | FSRP;
1184
1185        return 0;
1186}
1187
1188static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
1189                                     int div_id, int div)
1190{
1191        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1192        struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1193
1194        if (div_id != OMAP_MCBSP_CLKGDV)
1195                return -ENODEV;
1196
1197        mcbsp->clk_div = div;
1198        regs->srgr1     &= ~CLKGDV(0xff);
1199        regs->srgr1     |= CLKGDV(div - 1);
1200
1201        return 0;
1202}
1203
1204static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
1205                                         int clk_id, unsigned int freq,
1206                                         int dir)
1207{
1208        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1209        struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1210        int err = 0;
1211
1212        if (mcbsp->active) {
1213                if (freq == mcbsp->in_freq)
1214                        return 0;
1215                else
1216                        return -EBUSY;
1217        }
1218
1219        mcbsp->in_freq = freq;
1220        regs->srgr2 &= ~CLKSM;
1221        regs->pcr0 &= ~SCLKME;
1222
1223        switch (clk_id) {
1224        case OMAP_MCBSP_SYSCLK_CLK:
1225                regs->srgr2     |= CLKSM;
1226                break;
1227        case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
1228                if (mcbsp_omap1()) {
1229                        err = -EINVAL;
1230                        break;
1231                }
1232                err = omap2_mcbsp_set_clks_src(mcbsp,
1233                                               MCBSP_CLKS_PRCM_SRC);
1234                break;
1235        case OMAP_MCBSP_SYSCLK_CLKS_EXT:
1236                if (mcbsp_omap1()) {
1237                        err = 0;
1238                        break;
1239                }
1240                err = omap2_mcbsp_set_clks_src(mcbsp,
1241                                               MCBSP_CLKS_PAD_SRC);
1242                break;
1243
1244        case OMAP_MCBSP_SYSCLK_CLKX_EXT:
1245                regs->srgr2     |= CLKSM;
1246                regs->pcr0      |= SCLKME;
1247                /*
1248                 * If McBSP is master but yet the CLKX/CLKR pin drives the SRG,
1249                 * disable output on those pins. This enables to inject the
1250                 * reference clock through CLKX/CLKR. For this to work
1251                 * set_dai_sysclk() _needs_ to be called after set_dai_fmt().
1252                 */
1253                regs->pcr0      &= ~CLKXM;
1254                break;
1255        case OMAP_MCBSP_SYSCLK_CLKR_EXT:
1256                regs->pcr0      |= SCLKME;
1257                /* Disable ouput on CLKR pin in master mode */
1258                regs->pcr0      &= ~CLKRM;
1259                break;
1260        default:
1261                err = -ENODEV;
1262        }
1263
1264        return err;
1265}
1266
1267static const struct snd_soc_dai_ops mcbsp_dai_ops = {
1268        .startup        = omap_mcbsp_dai_startup,
1269        .shutdown       = omap_mcbsp_dai_shutdown,
1270        .prepare        = omap_mcbsp_dai_prepare,
1271        .trigger        = omap_mcbsp_dai_trigger,
1272        .delay          = omap_mcbsp_dai_delay,
1273        .hw_params      = omap_mcbsp_dai_hw_params,
1274        .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
1275        .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
1276        .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
1277};
1278
1279static int omap_mcbsp_probe(struct snd_soc_dai *dai)
1280{
1281        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1282
1283        pm_runtime_enable(mcbsp->dev);
1284
1285        snd_soc_dai_init_dma_data(dai,
1286                                  &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
1287                                  &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
1288
1289        return 0;
1290}
1291
1292static int omap_mcbsp_remove(struct snd_soc_dai *dai)
1293{
1294        struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1295
1296        pm_runtime_disable(mcbsp->dev);
1297
1298        return 0;
1299}
1300
1301static struct snd_soc_dai_driver omap_mcbsp_dai = {
1302        .probe = omap_mcbsp_probe,
1303        .remove = omap_mcbsp_remove,
1304        .playback = {
1305                .channels_min = 1,
1306                .channels_max = 16,
1307                .rates = OMAP_MCBSP_RATES,
1308                .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1309        },
1310        .capture = {
1311                .channels_min = 1,
1312                .channels_max = 16,
1313                .rates = OMAP_MCBSP_RATES,
1314                .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1315        },
1316        .ops = &mcbsp_dai_ops,
1317};
1318
1319static const struct snd_soc_component_driver omap_mcbsp_component = {
1320        .name           = "omap-mcbsp",
1321};
1322
1323static struct omap_mcbsp_platform_data omap2420_pdata = {
1324        .reg_step = 4,
1325        .reg_size = 2,
1326};
1327
1328static struct omap_mcbsp_platform_data omap2430_pdata = {
1329        .reg_step = 4,
1330        .reg_size = 4,
1331        .has_ccr = true,
1332};
1333
1334static struct omap_mcbsp_platform_data omap3_pdata = {
1335        .reg_step = 4,
1336        .reg_size = 4,
1337        .has_ccr = true,
1338        .has_wakeup = true,
1339};
1340
1341static struct omap_mcbsp_platform_data omap4_pdata = {
1342        .reg_step = 4,
1343        .reg_size = 4,
1344        .has_ccr = true,
1345        .has_wakeup = true,
1346};
1347
1348static const struct of_device_id omap_mcbsp_of_match[] = {
1349        {
1350                .compatible = "ti,omap2420-mcbsp",
1351                .data = &omap2420_pdata,
1352        },
1353        {
1354                .compatible = "ti,omap2430-mcbsp",
1355                .data = &omap2430_pdata,
1356        },
1357        {
1358                .compatible = "ti,omap3-mcbsp",
1359                .data = &omap3_pdata,
1360        },
1361        {
1362                .compatible = "ti,omap4-mcbsp",
1363                .data = &omap4_pdata,
1364        },
1365        { },
1366};
1367MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
1368
1369static int asoc_mcbsp_probe(struct platform_device *pdev)
1370{
1371        struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
1372        struct omap_mcbsp *mcbsp;
1373        const struct of_device_id *match;
1374        int ret;
1375
1376        match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
1377        if (match) {
1378                struct device_node *node = pdev->dev.of_node;
1379                struct omap_mcbsp_platform_data *pdata_quirk = pdata;
1380                int buffer_size;
1381
1382                pdata = devm_kzalloc(&pdev->dev,
1383                                     sizeof(struct omap_mcbsp_platform_data),
1384                                     GFP_KERNEL);
1385                if (!pdata)
1386                        return -ENOMEM;
1387
1388                memcpy(pdata, match->data, sizeof(*pdata));
1389                if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
1390                        pdata->buffer_size = buffer_size;
1391                if (pdata_quirk)
1392                        pdata->force_ick_on = pdata_quirk->force_ick_on;
1393        } else if (!pdata) {
1394                dev_err(&pdev->dev, "missing platform data.\n");
1395                return -EINVAL;
1396        }
1397        mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
1398        if (!mcbsp)
1399                return -ENOMEM;
1400
1401        mcbsp->id = pdev->id;
1402        mcbsp->pdata = pdata;
1403        mcbsp->dev = &pdev->dev;
1404        platform_set_drvdata(pdev, mcbsp);
1405
1406        ret = omap_mcbsp_init(pdev);
1407        if (ret)
1408                return ret;
1409
1410        if (mcbsp->pdata->reg_size == 2) {
1411                omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1412                omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1413        }
1414
1415        ret = devm_snd_soc_register_component(&pdev->dev,
1416                                              &omap_mcbsp_component,
1417                                              &omap_mcbsp_dai, 1);
1418        if (ret)
1419                return ret;
1420
1421        return sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
1422}
1423
1424static int asoc_mcbsp_remove(struct platform_device *pdev)
1425{
1426        struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1427
1428        if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
1429                mcbsp->pdata->ops->free(mcbsp->id);
1430
1431        if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req))
1432                cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
1433
1434        if (mcbsp->pdata->buffer_size)
1435                sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1436
1437        omap_mcbsp_st_cleanup(pdev);
1438
1439        return 0;
1440}
1441
1442static struct platform_driver asoc_mcbsp_driver = {
1443        .driver = {
1444                        .name = "omap-mcbsp",
1445                        .of_match_table = omap_mcbsp_of_match,
1446        },
1447
1448        .probe = asoc_mcbsp_probe,
1449        .remove = asoc_mcbsp_remove,
1450};
1451
1452module_platform_driver(asoc_mcbsp_driver);
1453
1454MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
1455MODULE_DESCRIPTION("OMAP I2S SoC Interface");
1456MODULE_LICENSE("GPL");
1457MODULE_ALIAS("platform:omap-mcbsp");
1458