1
2
3
4
5
6config ARC
7 def_bool y
8 select ARC_TIMERS
9 select ARCH_HAS_CACHE_LINE_SIZE
10 select ARCH_HAS_DEBUG_VM_PGTABLE
11 select ARCH_HAS_DMA_PREP_COHERENT
12 select ARCH_HAS_PTE_SPECIAL
13 select ARCH_HAS_SETUP_DMA_OPS
14 select ARCH_HAS_SYNC_DMA_FOR_CPU
15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17 select ARCH_32BIT_OFF_T
18 select BUILDTIME_TABLE_SORT
19 select CLONE_BACKWARDS
20 select COMMON_CLK
21 select DMA_DIRECT_REMAP
22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23 select GENERIC_FIND_FIRST_BIT
24
25 select GENERIC_IRQ_SHOW
26 select GENERIC_PCI_IOMAP
27 select GENERIC_PENDING_IRQ if SMP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select HAVE_ARCH_KGDB
31 select HAVE_ARCH_TRACEHOOK
32 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
33 select HAVE_DEBUG_STACKOVERFLOW
34 select HAVE_DEBUG_KMEMLEAK
35 select HAVE_FUTEX_CMPXCHG if FUTEX
36 select HAVE_IOREMAP_PROT
37 select HAVE_KERNEL_GZIP
38 select HAVE_KERNEL_LZMA
39 select HAVE_KPROBES
40 select HAVE_KRETPROBES
41 select HAVE_MOD_ARCH_SPECIFIC
42 select HAVE_PERF_EVENTS
43 select HANDLE_DOMAIN_IRQ
44 select IRQ_DOMAIN
45 select MODULES_USE_ELF_RELA
46 select OF
47 select OF_EARLY_FLATTREE
48 select PCI_SYSCALL if PCI
49 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
50 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
51 select SET_FS
52
53config TRACE_IRQFLAGS_SUPPORT
54 def_bool y
55
56config LOCKDEP_SUPPORT
57 def_bool y
58
59config SCHED_OMIT_FRAME_POINTER
60 def_bool y
61
62config GENERIC_CSUM
63 def_bool y
64
65config ARCH_FLATMEM_ENABLE
66 def_bool y
67
68config MMU
69 def_bool y
70
71config NO_IOPORT_MAP
72 def_bool y
73
74config GENERIC_CALIBRATE_DELAY
75 def_bool y
76
77config GENERIC_HWEIGHT
78 def_bool y
79
80config STACKTRACE_SUPPORT
81 def_bool y
82 select STACKTRACE
83
84menu "ARC Architecture Configuration"
85
86menu "ARC Platform/SoC/Board"
87
88source "arch/arc/plat-tb10x/Kconfig"
89source "arch/arc/plat-axs10x/Kconfig"
90source "arch/arc/plat-hsdk/Kconfig"
91
92endmenu
93
94choice
95 prompt "ARC Instruction Set"
96 default ISA_ARCV2
97
98config ISA_ARCOMPACT
99 bool "ARCompact ISA"
100 select CPU_NO_EFFICIENT_FFS
101 help
102 The original ARC ISA of ARC600/700 cores
103
104config ISA_ARCV2
105 bool "ARC ISA v2"
106 select ARC_TIMERS_64BIT
107 help
108 ISA for the Next Generation ARC-HS cores
109
110endchoice
111
112menu "ARC CPU Configuration"
113
114choice
115 prompt "ARC Core"
116 default ARC_CPU_770 if ISA_ARCOMPACT
117 default ARC_CPU_HS if ISA_ARCV2
118
119if ISA_ARCOMPACT
120
121config ARC_CPU_750D
122 bool "ARC750D"
123 select ARC_CANT_LLSC
124 help
125 Support for ARC750 core
126
127config ARC_CPU_770
128 bool "ARC770"
129 select ARC_HAS_SWAPE
130 help
131 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
132 This core has a bunch of cool new features:
133 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
134 Shared Address Spaces (for sharing TLB entries in MMU)
135 -Caches: New Prog Model, Region Flush
136 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
137
138endif
139
140config ARC_CPU_HS
141 bool "ARC-HS"
142 depends on ISA_ARCV2
143 help
144 Support for ARC HS38x Cores based on ARCv2 ISA
145 The notable features are:
146 - SMP configurations of up to 4 cores with coherency
147 - Optional L2 Cache and IO-Coherency
148 - Revised Interrupt Architecture (multiple priorites, reg banks,
149 auto stack switch, auto regfile save/restore)
150 - MMUv4 (PIPT dcache, Huge Pages)
151 - Instructions for
152 * 64bit load/store: LDD, STD
153 * Hardware assisted divide/remainder: DIV, REM
154 * Function prologue/epilogue: ENTER_S, LEAVE_S
155 * IRQ enable/disable: CLRI, SETI
156 * pop count: FFS, FLS
157 * SETcc, BMSKN, XBFU...
158
159endchoice
160
161config ARC_TUNE_MCPU
162 string "Override default -mcpu compiler flag"
163 default ""
164 help
165 Override default -mcpu=xxx compiler flag (which is set depending on
166 the ISA version) with the specified value.
167 NOTE: If specified flag isn't supported by current compiler the
168 ISA default value will be used as a fallback.
169
170config CPU_BIG_ENDIAN
171 bool "Enable Big Endian Mode"
172 help
173 Build kernel for Big Endian Mode of ARC CPU
174
175config SMP
176 bool "Symmetric Multi-Processing"
177 select ARC_MCIP if ISA_ARCV2
178 help
179 This enables support for systems with more than one CPU.
180
181if SMP
182
183config NR_CPUS
184 int "Maximum number of CPUs (2-4096)"
185 range 2 4096
186 default "4"
187
188config ARC_SMP_HALT_ON_RESET
189 bool "Enable Halt-on-reset boot mode"
190 help
191 In SMP configuration cores can be configured as Halt-on-reset
192 or they could all start at same time. For Halt-on-reset, non
193 masters are parked until Master kicks them so they can start off
194 at designated entry point. For other case, all jump to common
195 entry point and spin wait for Master's signal.
196
197endif
198
199config ARC_MCIP
200 bool "ARConnect Multicore IP (MCIP) Support "
201 depends on ISA_ARCV2
202 default y if SMP
203 help
204 This IP block enables SMP in ARC-HS38 cores.
205 It provides for cross-core interrupts, multi-core debug
206 hardware semaphores, shared memory,....
207
208menuconfig ARC_CACHE
209 bool "Enable Cache Support"
210 default y
211
212if ARC_CACHE
213
214config ARC_CACHE_LINE_SHIFT
215 int "Cache Line Length (as power of 2)"
216 range 5 7
217 default "6"
218 help
219 Starting with ARC700 4.9, Cache line length is configurable,
220 This option specifies "N", with Line-len = 2 power N
221 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
222 Linux only supports same line lengths for I and D caches.
223
224config ARC_HAS_ICACHE
225 bool "Use Instruction Cache"
226 default y
227
228config ARC_HAS_DCACHE
229 bool "Use Data Cache"
230 default y
231
232config ARC_CACHE_PAGES
233 bool "Per Page Cache Control"
234 default y
235 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
236 help
237 This can be used to over-ride the global I/D Cache Enable on a
238 per-page basis (but only for pages accessed via MMU such as
239 Kernel Virtual address or User Virtual Address)
240 TLB entries have a per-page Cache Enable Bit.
241 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
242 Global DISABLE + Per Page ENABLE won't work
243
244config ARC_CACHE_VIPT_ALIASING
245 bool "Support VIPT Aliasing D$"
246 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
247
248endif
249
250config ARC_HAS_ICCM
251 bool "Use ICCM"
252 help
253 Single Cycle RAMS to store Fast Path Code
254
255config ARC_ICCM_SZ
256 int "ICCM Size in KB"
257 default "64"
258 depends on ARC_HAS_ICCM
259
260config ARC_HAS_DCCM
261 bool "Use DCCM"
262 help
263 Single Cycle RAMS to store Fast Path Data
264
265config ARC_DCCM_SZ
266 int "DCCM Size in KB"
267 default "64"
268 depends on ARC_HAS_DCCM
269
270config ARC_DCCM_BASE
271 hex "DCCM map address"
272 default "0xA0000000"
273 depends on ARC_HAS_DCCM
274
275choice
276 prompt "MMU Version"
277 default ARC_MMU_V3 if ARC_CPU_770
278 default ARC_MMU_V2 if ARC_CPU_750D
279 default ARC_MMU_V4 if ARC_CPU_HS
280
281if ISA_ARCOMPACT
282
283config ARC_MMU_V1
284 bool "MMU v1"
285 help
286 Orig ARC700 MMU
287
288config ARC_MMU_V2
289 bool "MMU v2"
290 help
291 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
292 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
293
294config ARC_MMU_V3
295 bool "MMU v3"
296 depends on ARC_CPU_770
297 help
298 Introduced with ARC700 4.10: New Features
299 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
300 Shared Address Spaces (SASID)
301
302endif
303
304config ARC_MMU_V4
305 bool "MMU v4"
306 depends on ISA_ARCV2
307
308endchoice
309
310
311choice
312 prompt "MMU Page Size"
313 default ARC_PAGE_SIZE_8K
314
315config ARC_PAGE_SIZE_8K
316 bool "8KB"
317 help
318 Choose between 8k vs 16k
319
320config ARC_PAGE_SIZE_16K
321 bool "16KB"
322 depends on ARC_MMU_V3 || ARC_MMU_V4
323
324config ARC_PAGE_SIZE_4K
325 bool "4KB"
326 depends on ARC_MMU_V3 || ARC_MMU_V4
327
328endchoice
329
330choice
331 prompt "MMU Super Page Size"
332 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
333 default ARC_HUGEPAGE_2M
334
335config ARC_HUGEPAGE_2M
336 bool "2MB"
337
338config ARC_HUGEPAGE_16M
339 bool "16MB"
340
341endchoice
342
343config ARC_COMPACT_IRQ_LEVELS
344 depends on ISA_ARCOMPACT
345 bool "Setup Timer IRQ as high Priority"
346
347 depends on !SMP
348
349config ARC_FPU_SAVE_RESTORE
350 bool "Enable FPU state persistence across context switch"
351 help
352 ARCompact FPU has internal registers to assist with Double precision
353 Floating Point operations. There are control and stauts registers
354 for floating point exceptions and rounding modes. These are
355 preserved across task context switch when enabled.
356
357config ARC_CANT_LLSC
358 def_bool n
359
360config ARC_HAS_LLSC
361 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
362 default y
363 depends on !ARC_CANT_LLSC
364
365config ARC_HAS_SWAPE
366 bool "Insn: SWAPE (endian-swap)"
367 default y
368
369if ISA_ARCV2
370
371config ARC_USE_UNALIGNED_MEM_ACCESS
372 bool "Enable unaligned access in HW"
373 default y
374 select HAVE_EFFICIENT_UNALIGNED_ACCESS
375 help
376 The ARC HS architecture supports unaligned memory access
377 which is disabled by default. Enable unaligned access in
378 hardware and use software to use it
379
380config ARC_HAS_LL64
381 bool "Insn: 64bit LDD/STD"
382 help
383 Enable gcc to generate 64-bit load/store instructions
384 ISA mandates even/odd registers to allow encoding of two
385 dest operands with 2 possible source operands.
386 default y
387
388config ARC_HAS_DIV_REM
389 bool "Insn: div, divu, rem, remu"
390 default y
391
392config ARC_HAS_ACCL_REGS
393 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
394 default y
395 help
396 Depending on the configuration, CPU can contain accumulator reg-pair
397 (also referred to as r58:r59). These can also be used by gcc as GPR so
398 kernel needs to save/restore per process
399
400config ARC_DSP_HANDLED
401 def_bool n
402
403config ARC_DSP_SAVE_RESTORE_REGS
404 def_bool n
405
406choice
407 prompt "DSP support"
408 default ARC_DSP_NONE
409 help
410 Depending on the configuration, CPU can contain DSP registers
411 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
412 Below are options describing how to handle these registers in
413 interrupt entry / exit and in context switch.
414
415config ARC_DSP_NONE
416 bool "No DSP extension presence in HW"
417 help
418 No DSP extension presence in HW
419
420config ARC_DSP_KERNEL
421 bool "DSP extension in HW, no support for userspace"
422 select ARC_HAS_ACCL_REGS
423 select ARC_DSP_HANDLED
424 help
425 DSP extension presence in HW, no support for DSP-enabled userspace
426 applications. We don't save / restore DSP registers and only do
427 some minimal preparations so userspace won't be able to break kernel
428
429config ARC_DSP_USERSPACE
430 bool "Support DSP for userspace apps"
431 select ARC_HAS_ACCL_REGS
432 select ARC_DSP_HANDLED
433 select ARC_DSP_SAVE_RESTORE_REGS
434 help
435 DSP extension presence in HW, support save / restore DSP registers to
436 run DSP-enabled userspace applications
437
438config ARC_DSP_AGU_USERSPACE
439 bool "Support DSP with AGU for userspace apps"
440 select ARC_HAS_ACCL_REGS
441 select ARC_DSP_HANDLED
442 select ARC_DSP_SAVE_RESTORE_REGS
443 help
444 DSP and AGU extensions presence in HW, support save / restore DSP
445 and AGU registers to run DSP-enabled userspace applications
446endchoice
447
448config ARC_IRQ_NO_AUTOSAVE
449 bool "Disable hardware autosave regfile on interrupts"
450 default n
451 help
452 On HS cores, taken interrupt auto saves the regfile on stack.
453 This is programmable and can be optionally disabled in which case
454 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
455
456config ARC_LPB_DISABLE
457 bool "Disable loop buffer (LPB)"
458 help
459 On HS cores, loop buffer (LPB) is programmable in runtime and can
460 be optionally disabled.
461
462endif
463
464endmenu
465
466config LINUX_LINK_BASE
467 hex "Kernel link address"
468 default "0x80000000"
469 help
470 ARC700 divides the 32 bit phy address space into two equal halves
471 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
472 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
473 Typically Linux kernel is linked at the start of untransalted addr,
474 hence the default value of 0x8zs.
475 However some customers have peripherals mapped at this addr, so
476 Linux needs to be scooted a bit.
477 If you don't know what the above means, leave this setting alone.
478 This needs to match memory start address specified in Device Tree
479
480config LINUX_RAM_BASE
481 hex "RAM base address"
482 default LINUX_LINK_BASE
483 help
484 By default Linux is linked at base of RAM. However in some special
485 cases (such as HSDK), Linux can't be linked at start of DDR, hence
486 this option.
487
488config HIGHMEM
489 bool "High Memory Support"
490 select HAVE_ARCH_PFN_VALID
491 select KMAP_LOCAL
492 help
493 With ARC 2G:2G address split, only upper 2G is directly addressable by
494 kernel. Enable this to potentially allow access to rest of 2G and PAE
495 in future
496
497config ARC_HAS_PAE40
498 bool "Support for the 40-bit Physical Address Extension"
499 depends on ISA_ARCV2
500 select HIGHMEM
501 select PHYS_ADDR_T_64BIT
502 help
503 Enable access to physical memory beyond 4G, only supported on
504 ARC cores with 40 bit Physical Addressing support
505
506config ARC_KVADDR_SIZE
507 int "Kernel Virtual Address Space size (MB)"
508 range 0 512
509 default "256"
510 help
511 The kernel address space is carved out of 256MB of translated address
512 space for catering to vmalloc, modules, pkmap, fixmap. This however may
513 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
514 this to be stretched to 512 MB (by extending into the reserved
515 kernel-user gutter)
516
517config ARC_CURR_IN_REG
518 bool "Dedicate Register r25 for current_task pointer"
519 default y
520 help
521 This reserved Register R25 to point to Current Task in
522 kernel mode. This saves memory access for each such access
523
524
525config ARC_EMUL_UNALIGNED
526 bool "Emulate unaligned memory access (userspace only)"
527 select SYSCTL_ARCH_UNALIGN_NO_WARN
528 select SYSCTL_ARCH_UNALIGN_ALLOW
529 depends on ISA_ARCOMPACT
530 help
531 This enables misaligned 16 & 32 bit memory access from user space.
532 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
533 potential bugs in code
534
535config HZ
536 int "Timer Frequency"
537 default 100
538
539config ARC_METAWARE_HLINK
540 bool "Support for Metaware debugger assisted Host access"
541 help
542 This options allows a Linux userland apps to directly access
543 host file system (open/creat/read/write etc) with help from
544 Metaware Debugger. This can come in handy for Linux-host communication
545 when there is no real usable peripheral such as EMAC.
546
547menuconfig ARC_DBG
548 bool "ARC debugging"
549 default y
550
551if ARC_DBG
552
553config ARC_DW2_UNWIND
554 bool "Enable DWARF specific kernel stack unwind"
555 default y
556 select KALLSYMS
557 help
558 Compiles the kernel with DWARF unwind information and can be used
559 to get stack backtraces.
560
561 If you say Y here the resulting kernel image will be slightly larger
562 but not slower, and it will give very useful debugging information.
563 If you don't debug the kernel, you can say N, but we may not be able
564 to solve problems without frame unwind information
565
566config ARC_DBG_TLB_PARANOIA
567 bool "Paranoia Checks in Low Level TLB Handlers"
568
569config ARC_DBG_JUMP_LABEL
570 bool "Paranoid checks in Static Keys (jump labels) code"
571 depends on JUMP_LABEL
572 default y if STATIC_KEYS_SELFTEST
573 help
574 Enable paranoid checks and self-test of both ARC-specific and generic
575 part of static keys (jump labels) related code.
576endif
577
578config ARC_BUILTIN_DTB_NAME
579 string "Built in DTB"
580 help
581 Set the name of the DTB to embed in the vmlinux binary
582 Leaving it blank selects the minimal "skeleton" dtb
583
584endmenu
585
586config FORCE_MAX_ZONEORDER
587 int "Maximum zone order"
588 default "12" if ARC_HUGEPAGE_16M
589 default "11"
590
591source "kernel/power/Kconfig"
592
