1
2config ARM
3 bool
4 default y
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_KEEPINITRD
12 select ARCH_HAS_KCOV
13 select ARCH_HAS_MEMBARRIER_SYNC_CORE
14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
16 select ARCH_HAS_PHYS_TO_DMA
17 select ARCH_HAS_SETUP_DMA_OPS
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
20 select ARCH_HAS_STRICT_MODULE_RWX if MMU
21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
25 select ARCH_HAVE_CUSTOM_GPIO_H
26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
35 select ARCH_USE_BUILTIN_BSWAP
36 select ARCH_USE_CMPXCHG_LOCKREF
37 select ARCH_USE_MEMTEST
38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
39 select ARCH_WANT_IPC_PARSE_VERSION
40 select ARCH_WANT_LD_ORPHAN_WARN
41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
42 select BUILDTIME_TABLE_SORT if MMU
43 select CLONE_BACKWARDS
44 select CPU_PM if SUSPEND || CPU_IDLE
45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
46 select DMA_DECLARE_COHERENT
47 select DMA_OPS
48 select DMA_REMAP if MMU
49 select EDAC_SUPPORT
50 select EDAC_ATOMIC_SCRUB
51 select GENERIC_ALLOCATOR
52 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
53 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
54 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
55 select GENERIC_IRQ_IPI if SMP
56 select GENERIC_CPU_AUTOPROBE
57 select GENERIC_EARLY_IOREMAP
58 select GENERIC_IDLE_POLL_SETUP
59 select GENERIC_IRQ_PROBE
60 select GENERIC_IRQ_SHOW
61 select GENERIC_IRQ_SHOW_LEVEL
62 select GENERIC_LIB_DEVMEM_IS_ALLOWED
63 select GENERIC_PCI_IOMAP
64 select GENERIC_SCHED_CLOCK
65 select GENERIC_SMP_IDLE_THREAD
66 select GENERIC_STRNCPY_FROM_USER
67 select GENERIC_STRNLEN_USER
68 select HANDLE_DOMAIN_IRQ
69 select HARDIRQS_SW_RESEND
70 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
71 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
72 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
73 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
74 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
75 select HAVE_ARCH_MMAP_RND_BITS if MMU
76 select HAVE_ARCH_PFN_VALID
77 select HAVE_ARCH_SECCOMP
78 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
79 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
80 select HAVE_ARCH_TRACEHOOK
81 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
82 select HAVE_ARM_SMCCC if CPU_V7
83 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
84 select HAVE_CONTEXT_TRACKING
85 select HAVE_C_RECORDMCOUNT
86 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
87 select HAVE_DMA_CONTIGUOUS if MMU
88 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
89 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
90 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
91 select HAVE_EXIT_THREAD
92 select HAVE_FAST_GUP if ARM_LPAE
93 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
94 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
95 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
96 select HAVE_GCC_PLUGINS
97 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
98 select HAVE_IRQ_TIME_ACCOUNTING
99 select HAVE_KERNEL_GZIP
100 select HAVE_KERNEL_LZ4
101 select HAVE_KERNEL_LZMA
102 select HAVE_KERNEL_LZO
103 select HAVE_KERNEL_XZ
104 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
105 select HAVE_KRETPROBES if HAVE_KPROBES
106 select HAVE_MOD_ARCH_SPECIFIC
107 select HAVE_NMI
108 select HAVE_OPTPROBES if !THUMB2_KERNEL
109 select HAVE_PERF_EVENTS
110 select HAVE_PERF_REGS
111 select HAVE_PERF_USER_STACK_DUMP
112 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
113 select HAVE_REGS_AND_STACK_ACCESS_API
114 select HAVE_RSEQ
115 select HAVE_STACKPROTECTOR
116 select HAVE_SYSCALL_TRACEPOINTS
117 select HAVE_UID16
118 select HAVE_VIRT_CPU_ACCOUNTING_GEN
119 select IRQ_FORCED_THREADING
120 select MODULES_USE_ELF_REL
121 select NEED_DMA_MAP_STATE
122 select OF_EARLY_FLATTREE if OF
123 select OLD_SIGACTION
124 select OLD_SIGSUSPEND3
125 select PCI_SYSCALL if PCI
126 select PERF_USE_VMALLOC
127 select RTC_LIB
128 select SET_FS
129 select SYS_SUPPORTS_APM_EMULATION
130
131
132 help
133 The ARM series is a line of low-power-consumption RISC chip designs
134 licensed by ARM Ltd and targeted at embedded applications and
135 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
136 manufactured, but legacy ARM-based PC hardware remains popular in
137 Europe. There is an ARM Linux project with a web page at
138 <http://www.arm.linux.org.uk/>.
139
140config ARM_HAS_SG_CHAIN
141 bool
142
143config ARM_DMA_USE_IOMMU
144 bool
145 select ARM_HAS_SG_CHAIN
146 select NEED_SG_DMA_LENGTH
147
148if ARM_DMA_USE_IOMMU
149
150config ARM_DMA_IOMMU_ALIGNMENT
151 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
152 range 4 9
153 default 8
154 help
155 DMA mapping framework by default aligns all buffers to the smallest
156 PAGE_SIZE order which is greater than or equal to the requested buffer
157 size. This works well for buffers up to a few hundreds kilobytes, but
158 for larger buffers it just a waste of address space. Drivers which has
159 relatively small addressing window (like 64Mib) might run out of
160 virtual space with just a few allocations.
161
162 With this parameter you can specify the maximum PAGE_SIZE order for
163 DMA IOMMU buffers. Larger buffers will be aligned only to this
164 specified order. The order is expressed as a power of two multiplied
165 by the PAGE_SIZE.
166
167endif
168
169config SYS_SUPPORTS_APM_EMULATION
170 bool
171
172config HAVE_TCM
173 bool
174 select GENERIC_ALLOCATOR
175
176config HAVE_PROC_CPU
177 bool
178
179config NO_IOPORT_MAP
180 bool
181
182config SBUS
183 bool
184
185config STACKTRACE_SUPPORT
186 bool
187 default y
188
189config LOCKDEP_SUPPORT
190 bool
191 default y
192
193config TRACE_IRQFLAGS_SUPPORT
194 bool
195 default !CPU_V7M
196
197config ARCH_HAS_ILOG2_U32
198 bool
199
200config ARCH_HAS_ILOG2_U64
201 bool
202
203config ARCH_HAS_BANDGAP
204 bool
205
206config FIX_EARLYCON_MEM
207 def_bool y if MMU
208
209config GENERIC_HWEIGHT
210 bool
211 default y
212
213config GENERIC_CALIBRATE_DELAY
214 bool
215 default y
216
217config ARCH_MAY_HAVE_PC_FDC
218 bool
219
220config ARCH_SUPPORTS_UPROBES
221 def_bool y
222
223config ARCH_HAS_DMA_SET_COHERENT_MASK
224 bool
225
226config GENERIC_ISA_DMA
227 bool
228
229config FIQ
230 bool
231
232config NEED_RET_TO_USER
233 bool
234
235config ARCH_MTD_XIP
236 bool
237
238config ARM_PATCH_PHYS_VIRT
239 bool "Patch physical to virtual translations at runtime" if EMBEDDED
240 default y
241 depends on !XIP_KERNEL && MMU
242 help
243 Patch phys-to-virt and virt-to-phys translation functions at
244 boot and module load time according to the position of the
245 kernel in system memory.
246
247 This can only be used with non-XIP MMU kernels where the base
248 of physical memory is at a 2 MiB boundary.
249
250 Only disable this option if you know that you do not require
251 this feature (eg, building a kernel for a single machine) and
252 you need to shrink the kernel to the minimal size.
253
254config NEED_MACH_IO_H
255 bool
256 help
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
260
261config NEED_MACH_MEMORY_H
262 bool
263 help
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
267
268config PHYS_OFFSET
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT
271 default DRAM_BASE if !MMU
272 default 0x00000000 if ARCH_FOOTBRIDGE
273 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
274 default 0x20000000 if ARCH_S5PV210
275 default 0xc0000000 if ARCH_SA1100
276 help
277 Please provide the physical address corresponding to the
278 location of main memory in your system.
279
280config GENERIC_BUG
281 def_bool y
282 depends on BUG
283
284config PGTABLE_LEVELS
285 int
286 default 3 if ARM_LPAE
287 default 2
288
289menu "System Type"
290
291config MMU
292 bool "MMU-based Paged Memory Management Support"
293 default y
294 help
295 Select if you want MMU-based virtualised addressing space
296 support by paged memory management. If unsure, say 'Y'.
297
298config ARCH_MMAP_RND_BITS_MIN
299 default 8
300
301config ARCH_MMAP_RND_BITS_MAX
302 default 14 if PAGE_OFFSET=0x40000000
303 default 15 if PAGE_OFFSET=0x80000000
304 default 16
305
306
307
308
309
310choice
311 prompt "ARM system type"
312 default ARM_SINGLE_ARMV7M if !MMU
313 default ARCH_MULTIPLATFORM if MMU
314
315config ARCH_MULTIPLATFORM
316 bool "Allow multiple platforms to be selected"
317 depends on MMU
318 select ARCH_FLATMEM_ENABLE
319 select ARCH_SPARSEMEM_ENABLE
320 select ARCH_SELECT_MEMORY_MODEL
321 select ARM_HAS_SG_CHAIN
322 select ARM_PATCH_PHYS_VIRT
323 select AUTO_ZRELADDR
324 select TIMER_OF
325 select COMMON_CLK
326 select GENERIC_IRQ_MULTI_HANDLER
327 select HAVE_PCI
328 select PCI_DOMAINS_GENERIC if PCI
329 select SPARSE_IRQ
330 select USE_OF
331
332config ARM_SINGLE_ARMV7M
333 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
334 depends on !MMU
335 select ARM_NVIC
336 select AUTO_ZRELADDR
337 select TIMER_OF
338 select COMMON_CLK
339 select CPU_V7M
340 select NO_IOPORT_MAP
341 select SPARSE_IRQ
342 select USE_OF
343
344config ARCH_EP93XX
345 bool "EP93xx-based"
346 select ARCH_SPARSEMEM_ENABLE
347 select ARM_AMBA
348 imply ARM_PATCH_PHYS_VIRT
349 select ARM_VIC
350 select GENERIC_IRQ_MULTI_HANDLER
351 select AUTO_ZRELADDR
352 select CLKSRC_MMIO
353 select CPU_ARM920T
354 select GPIOLIB
355 select HAVE_LEGACY_CLK
356 help
357 This enables support for the Cirrus EP93xx series of CPUs.
358
359config ARCH_FOOTBRIDGE
360 bool "FootBridge"
361 select CPU_SA110
362 select FOOTBRIDGE
363 select NEED_MACH_IO_H if !MMU
364 select NEED_MACH_MEMORY_H
365 help
366 Support for systems based on the DC21285 companion chip
367 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
368
369config ARCH_IOP32X
370 bool "IOP32x-based"
371 depends on MMU
372 select CPU_XSCALE
373 select GPIO_IOP
374 select GPIOLIB
375 select NEED_RET_TO_USER
376 select FORCE_PCI
377 select PLAT_IOP
378 help
379 Support for Intel's 80219 and IOP32X (XScale) family of
380 processors.
381
382config ARCH_IXP4XX
383 bool "IXP4xx-based"
384 depends on MMU
385 select ARCH_HAS_DMA_SET_COHERENT_MASK
386 select ARCH_SUPPORTS_BIG_ENDIAN
387 select CPU_XSCALE
388 select DMABOUNCE if PCI
389 select GENERIC_IRQ_MULTI_HANDLER
390 select GPIO_IXP4XX
391 select GPIOLIB
392 select HAVE_PCI
393 select IXP4XX_IRQ
394 select IXP4XX_TIMER
395
396 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY
397 select USB_EHCI_BIG_ENDIAN_DESC
398 select USB_EHCI_BIG_ENDIAN_MMIO
399 help
400 Support for Intel's IXP4XX (XScale) family of processors.
401
402config ARCH_DOVE
403 bool "Marvell Dove"
404 select CPU_PJ4
405 select GENERIC_IRQ_MULTI_HANDLER
406 select GPIOLIB
407 select HAVE_PCI
408 select MVEBU_MBUS
409 select PINCTRL
410 select PINCTRL_DOVE
411 select PLAT_ORION_LEGACY
412 select SPARSE_IRQ
413 select PM_GENERIC_DOMAINS if PM
414 help
415 Support for the Marvell Dove SoC 88AP510
416
417config ARCH_PXA
418 bool "PXA2xx/PXA3xx-based"
419 depends on MMU
420 select ARCH_MTD_XIP
421 select ARM_CPU_SUSPEND if PM
422 select AUTO_ZRELADDR
423 select COMMON_CLK
424 select CLKSRC_PXA
425 select CLKSRC_MMIO
426 select TIMER_OF
427 select CPU_XSCALE if !CPU_XSC3
428 select GENERIC_IRQ_MULTI_HANDLER
429 select GPIO_PXA
430 select GPIOLIB
431 select IRQ_DOMAIN
432 select PLAT_PXA
433 select SPARSE_IRQ
434 help
435 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
436
437config ARCH_RPC
438 bool "RiscPC"
439 depends on MMU
440 select ARCH_ACORN
441 select ARCH_MAY_HAVE_PC_FDC
442 select ARCH_SPARSEMEM_ENABLE
443 select ARM_HAS_SG_CHAIN
444 select CPU_SA110
445 select FIQ
446 select HAVE_PATA_PLATFORM
447 select ISA_DMA_API
448 select LEGACY_TIMER_TICK
449 select NEED_MACH_IO_H
450 select NEED_MACH_MEMORY_H
451 select NO_IOPORT_MAP
452 help
453 On the Acorn Risc-PC, Linux can support the internal IDE disk and
454 CD-ROM interface, serial and parallel port, and the floppy drive.
455
456config ARCH_SA1100
457 bool "SA1100-based"
458 select ARCH_MTD_XIP
459 select ARCH_SPARSEMEM_ENABLE
460 select CLKSRC_MMIO
461 select CLKSRC_PXA
462 select TIMER_OF if OF
463 select COMMON_CLK
464 select CPU_FREQ
465 select CPU_SA1100
466 select GENERIC_IRQ_MULTI_HANDLER
467 select GPIOLIB
468 select IRQ_DOMAIN
469 select ISA
470 select NEED_MACH_MEMORY_H
471 select SPARSE_IRQ
472 help
473 Support for StrongARM 11x0 based boards.
474
475config ARCH_S3C24XX
476 bool "Samsung S3C24XX SoCs"
477 select ATAGS
478 select CLKSRC_SAMSUNG_PWM
479 select GPIO_SAMSUNG
480 select GPIOLIB
481 select GENERIC_IRQ_MULTI_HANDLER
482 select HAVE_S3C2410_I2C if I2C
483 select HAVE_S3C_RTC if RTC_CLASS
484 select NEED_MACH_IO_H
485 select S3C2410_WATCHDOG
486 select SAMSUNG_ATAGS
487 select USE_OF
488 select WATCHDOG
489 help
490 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
491 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
492 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
493 Samsung SMDK2410 development board (and derivatives).
494
495config ARCH_OMAP1
496 bool "TI OMAP1"
497 depends on MMU
498 select ARCH_OMAP
499 select CLKSRC_MMIO
500 select GENERIC_IRQ_CHIP
501 select GENERIC_IRQ_MULTI_HANDLER
502 select GPIOLIB
503 select HAVE_LEGACY_CLK
504 select IRQ_DOMAIN
505 select NEED_MACH_IO_H if PCCARD
506 select NEED_MACH_MEMORY_H
507 select SPARSE_IRQ
508 help
509 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
510
511endchoice
512
513menu "Multiple platform selection"
514 depends on ARCH_MULTIPLATFORM
515
516comment "CPU Core family selection"
517
518config ARCH_MULTI_V4
519 bool "ARMv4 based platforms (FA526)"
520 depends on !ARCH_MULTI_V6_V7
521 select ARCH_MULTI_V4_V5
522 select CPU_FA526
523
524config ARCH_MULTI_V4T
525 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
526 depends on !ARCH_MULTI_V6_V7
527 select ARCH_MULTI_V4_V5
528 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
529 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
530 CPU_ARM925T || CPU_ARM940T)
531
532config ARCH_MULTI_V5
533 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
534 depends on !ARCH_MULTI_V6_V7
535 select ARCH_MULTI_V4_V5
536 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
537 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
538 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
539
540config ARCH_MULTI_V4_V5
541 bool
542
543config ARCH_MULTI_V6
544 bool "ARMv6 based platforms (ARM11)"
545 select ARCH_MULTI_V6_V7
546 select CPU_V6K
547
548config ARCH_MULTI_V7
549 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
550 default y
551 select ARCH_MULTI_V6_V7
552 select CPU_V7
553 select HAVE_SMP
554
555config ARCH_MULTI_V6_V7
556 bool
557 select MIGHT_HAVE_CACHE_L2X0
558
559config ARCH_MULTI_CPU_AUTO
560 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
561 select ARCH_MULTI_V5
562
563endmenu
564
565config ARCH_VIRT
566 bool "Dummy Virtual Machine"
567 depends on ARCH_MULTI_V7
568 select ARM_AMBA
569 select ARM_GIC
570 select ARM_GIC_V2M if PCI
571 select ARM_GIC_V3
572 select ARM_GIC_V3_ITS if PCI
573 select ARM_PSCI
574 select HAVE_ARM_ARCH_TIMER
575 select ARCH_SUPPORTS_BIG_ENDIAN
576
577
578
579
580
581
582source "arch/arm/mach-actions/Kconfig"
583
584source "arch/arm/mach-alpine/Kconfig"
585
586source "arch/arm/mach-artpec/Kconfig"
587
588source "arch/arm/mach-asm9260/Kconfig"
589
590source "arch/arm/mach-aspeed/Kconfig"
591
592source "arch/arm/mach-at91/Kconfig"
593
594source "arch/arm/mach-axxia/Kconfig"
595
596source "arch/arm/mach-bcm/Kconfig"
597
598source "arch/arm/mach-berlin/Kconfig"
599
600source "arch/arm/mach-clps711x/Kconfig"
601
602source "arch/arm/mach-cns3xxx/Kconfig"
603
604source "arch/arm/mach-davinci/Kconfig"
605
606source "arch/arm/mach-digicolor/Kconfig"
607
608source "arch/arm/mach-dove/Kconfig"
609
610source "arch/arm/mach-ep93xx/Kconfig"
611
612source "arch/arm/mach-exynos/Kconfig"
613
614source "arch/arm/mach-footbridge/Kconfig"
615
616source "arch/arm/mach-gemini/Kconfig"
617
618source "arch/arm/mach-highbank/Kconfig"
619
620source "arch/arm/mach-hisi/Kconfig"
621
622source "arch/arm/mach-imx/Kconfig"
623
624source "arch/arm/mach-integrator/Kconfig"
625
626source "arch/arm/mach-iop32x/Kconfig"
627
628source "arch/arm/mach-ixp4xx/Kconfig"
629
630source "arch/arm/mach-keystone/Kconfig"
631
632source "arch/arm/mach-lpc32xx/Kconfig"
633
634source "arch/arm/mach-mediatek/Kconfig"
635
636source "arch/arm/mach-meson/Kconfig"
637
638source "arch/arm/mach-milbeaut/Kconfig"
639
640source "arch/arm/mach-mmp/Kconfig"
641
642source "arch/arm/mach-moxart/Kconfig"
643
644source "arch/arm/mach-mstar/Kconfig"
645
646source "arch/arm/mach-mv78xx0/Kconfig"
647
648source "arch/arm/mach-mvebu/Kconfig"
649
650source "arch/arm/mach-mxs/Kconfig"
651
652source "arch/arm/mach-nomadik/Kconfig"
653
654source "arch/arm/mach-npcm/Kconfig"
655
656source "arch/arm/mach-nspire/Kconfig"
657
658source "arch/arm/plat-omap/Kconfig"
659
660source "arch/arm/mach-omap1/Kconfig"
661
662source "arch/arm/mach-omap2/Kconfig"
663
664source "arch/arm/mach-orion5x/Kconfig"
665
666source "arch/arm/mach-oxnas/Kconfig"
667
668source "arch/arm/mach-pxa/Kconfig"
669source "arch/arm/plat-pxa/Kconfig"
670
671source "arch/arm/mach-qcom/Kconfig"
672
673source "arch/arm/mach-rda/Kconfig"
674
675source "arch/arm/mach-realtek/Kconfig"
676
677source "arch/arm/mach-realview/Kconfig"
678
679source "arch/arm/mach-rockchip/Kconfig"
680
681source "arch/arm/mach-s3c/Kconfig"
682
683source "arch/arm/mach-s5pv210/Kconfig"
684
685source "arch/arm/mach-sa1100/Kconfig"
686
687source "arch/arm/mach-shmobile/Kconfig"
688
689source "arch/arm/mach-socfpga/Kconfig"
690
691source "arch/arm/mach-spear/Kconfig"
692
693source "arch/arm/mach-sti/Kconfig"
694
695source "arch/arm/mach-stm32/Kconfig"
696
697source "arch/arm/mach-sunxi/Kconfig"
698
699source "arch/arm/mach-tegra/Kconfig"
700
701source "arch/arm/mach-uniphier/Kconfig"
702
703source "arch/arm/mach-ux500/Kconfig"
704
705source "arch/arm/mach-versatile/Kconfig"
706
707source "arch/arm/mach-vexpress/Kconfig"
708
709source "arch/arm/mach-vt8500/Kconfig"
710
711source "arch/arm/mach-zynq/Kconfig"
712
713
714config ARCH_LPC18XX
715 bool "NXP LPC18xx/LPC43xx"
716 depends on ARM_SINGLE_ARMV7M
717 select ARCH_HAS_RESET_CONTROLLER
718 select ARM_AMBA
719 select CLKSRC_LPC32XX
720 select PINCTRL
721 help
722 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
723 high performance microcontrollers.
724
725config ARCH_MPS2
726 bool "ARM MPS2 platform"
727 depends on ARM_SINGLE_ARMV7M
728 select ARM_AMBA
729 select CLKSRC_MPS2
730 help
731 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
732 with a range of available cores like Cortex-M3/M4/M7.
733
734 Please, note that depends which Application Note is used memory map
735 for the platform may vary, so adjustment of RAM base might be needed.
736
737
738config ARCH_ACORN
739 bool
740
741config PLAT_IOP
742 bool
743
744config PLAT_ORION
745 bool
746 select CLKSRC_MMIO
747 select COMMON_CLK
748 select GENERIC_IRQ_CHIP
749 select IRQ_DOMAIN
750
751config PLAT_ORION_LEGACY
752 bool
753 select PLAT_ORION
754
755config PLAT_PXA
756 bool
757
758config PLAT_VERSATILE
759 bool
760
761source "arch/arm/mm/Kconfig"
762
763config IWMMXT
764 bool "Enable iWMMXt support"
765 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
766 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
767 help
768 Enable support for iWMMXt context switching at run time if
769 running on a CPU that supports it.
770
771if !MMU
772source "arch/arm/Kconfig-nommu"
773endif
774
775config PJ4B_ERRATA_4742
776 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
777 depends on CPU_PJ4B && MACH_ARMADA_370
778 default y
779 help
780 When coming out of either a Wait for Interrupt (WFI) or a Wait for
781 Event (WFE) IDLE states, a specific timing sensitivity exists between
782 the retiring WFI/WFE instructions and the newly issued subsequent
783 instructions. This sensitivity can result in a CPU hang scenario.
784 Workaround:
785 The software must insert either a Data Synchronization Barrier (DSB)
786 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
787 instruction
788
789config ARM_ERRATA_326103
790 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
791 depends on CPU_V6
792 help
793 Executing a SWP instruction to read-only memory does not set bit 11
794 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
795 treat the access as a read, preventing a COW from occurring and
796 causing the faulting task to livelock.
797
798config ARM_ERRATA_411920
799 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
800 depends on CPU_V6 || CPU_V6K
801 help
802 Invalidation of the Instruction Cache operation can
803 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
804 It does not affect the MPCore. This option enables the ARM Ltd.
805 recommended workaround.
806
807config ARM_ERRATA_430973
808 bool "ARM errata: Stale prediction on replaced interworking branch"
809 depends on CPU_V7
810 help
811 This option enables the workaround for the 430973 Cortex-A8
812 r1p* erratum. If a code sequence containing an ARM/Thumb
813 interworking branch is replaced with another code sequence at the
814 same virtual address, whether due to self-modifying code or virtual
815 to physical address re-mapping, Cortex-A8 does not recover from the
816 stale interworking branch prediction. This results in Cortex-A8
817 executing the new code sequence in the incorrect ARM or Thumb state.
818 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
819 and also flushes the branch target cache at every context switch.
820 Note that setting specific bits in the ACTLR register may not be
821 available in non-secure mode.
822
823config ARM_ERRATA_458693
824 bool "ARM errata: Processor deadlock when a false hazard is created"
825 depends on CPU_V7
826 depends on !ARCH_MULTIPLATFORM
827 help
828 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
829 erratum. For very specific sequences of memory operations, it is
830 possible for a hazard condition intended for a cache line to instead
831 be incorrectly associated with a different cache line. This false
832 hazard might then cause a processor deadlock. The workaround enables
833 the L1 caching of the NEON accesses and disables the PLD instruction
834 in the ACTLR register. Note that setting specific bits in the ACTLR
835 register may not be available in non-secure mode.
836
837config ARM_ERRATA_460075
838 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
839 depends on CPU_V7
840 depends on !ARCH_MULTIPLATFORM
841 help
842 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
843 erratum. Any asynchronous access to the L2 cache may encounter a
844 situation in which recent store transactions to the L2 cache are lost
845 and overwritten with stale memory contents from external memory. The
846 workaround disables the write-allocate mode for the L2 cache via the
847 ACTLR register. Note that setting specific bits in the ACTLR register
848 may not be available in non-secure mode.
849
850config ARM_ERRATA_742230
851 bool "ARM errata: DMB operation may be faulty"
852 depends on CPU_V7 && SMP
853 depends on !ARCH_MULTIPLATFORM
854 help
855 This option enables the workaround for the 742230 Cortex-A9
856 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
857 between two write operations may not ensure the correct visibility
858 ordering of the two writes. This workaround sets a specific bit in
859 the diagnostic register of the Cortex-A9 which causes the DMB
860 instruction to behave as a DSB, ensuring the correct behaviour of
861 the two writes.
862
863config ARM_ERRATA_742231
864 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
865 depends on CPU_V7 && SMP
866 depends on !ARCH_MULTIPLATFORM
867 help
868 This option enables the workaround for the 742231 Cortex-A9
869 (r2p0..r2p2) erratum. Under certain conditions, specific to the
870 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
871 accessing some data located in the same cache line, may get corrupted
872 data due to bad handling of the address hazard when the line gets
873 replaced from one of the CPUs at the same time as another CPU is
874 accessing it. This workaround sets specific bits in the diagnostic
875 register of the Cortex-A9 which reduces the linefill issuing
876 capabilities of the processor.
877
878config ARM_ERRATA_643719
879 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
880 depends on CPU_V7 && SMP
881 default y
882 help
883 This option enables the workaround for the 643719 Cortex-A9 (prior to
884 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
885 register returns zero when it should return one. The workaround
886 corrects this value, ensuring cache maintenance operations which use
887 it behave as intended and avoiding data corruption.
888
889config ARM_ERRATA_720789
890 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
891 depends on CPU_V7
892 help
893 This option enables the workaround for the 720789 Cortex-A9 (prior to
894 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
895 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
896 As a consequence of this erratum, some TLB entries which should be
897 invalidated are not, resulting in an incoherency in the system page
898 tables. The workaround changes the TLB flushing routines to invalidate
899 entries regardless of the ASID.
900
901config ARM_ERRATA_743622
902 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
903 depends on CPU_V7
904 depends on !ARCH_MULTIPLATFORM
905 help
906 This option enables the workaround for the 743622 Cortex-A9
907 (r2p*) erratum. Under very rare conditions, a faulty
908 optimisation in the Cortex-A9 Store Buffer may lead to data
909 corruption. This workaround sets a specific bit in the diagnostic
910 register of the Cortex-A9 which disables the Store Buffer
911 optimisation, preventing the defect from occurring. This has no
912 visible impact on the overall performance or power consumption of the
913 processor.
914
915config ARM_ERRATA_751472
916 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
917 depends on CPU_V7
918 depends on !ARCH_MULTIPLATFORM
919 help
920 This option enables the workaround for the 751472 Cortex-A9 (prior
921 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
922 completion of a following broadcasted operation if the second
923 operation is received by a CPU before the ICIALLUIS has completed,
924 potentially leading to corrupted entries in the cache or TLB.
925
926config ARM_ERRATA_754322
927 bool "ARM errata: possible faulty MMU translations following an ASID switch"
928 depends on CPU_V7
929 help
930 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
931 r3p*) erratum. A speculative memory access may cause a page table walk
932 which starts prior to an ASID switch but completes afterwards. This
933 can populate the micro-TLB with a stale entry which may be hit with
934 the new ASID. This workaround places two dsb instructions in the mm
935 switching code so that no page table walks can cross the ASID switch.
936
937config ARM_ERRATA_754327
938 bool "ARM errata: no automatic Store Buffer drain"
939 depends on CPU_V7 && SMP
940 help
941 This option enables the workaround for the 754327 Cortex-A9 (prior to
942 r2p0) erratum. The Store Buffer does not have any automatic draining
943 mechanism and therefore a livelock may occur if an external agent
944 continuously polls a memory location waiting to observe an update.
945 This workaround defines cpu_relax() as smp_mb(), preventing correctly
946 written polling loops from denying visibility of updates to memory.
947
948config ARM_ERRATA_364296
949 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
950 depends on CPU_V6
951 help
952 This options enables the workaround for the 364296 ARM1136
953 r0p2 erratum (possible cache data corruption with
954 hit-under-miss enabled). It sets the undocumented bit 31 in
955 the auxiliary control register and the FI bit in the control
956 register, thus disabling hit-under-miss without putting the
957 processor into full low interrupt latency mode. ARM11MPCore
958 is not affected.
959
960config ARM_ERRATA_764369
961 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
962 depends on CPU_V7 && SMP
963 help
964 This option enables the workaround for erratum 764369
965 affecting Cortex-A9 MPCore with two or more processors (all
966 current revisions). Under certain timing circumstances, a data
967 cache line maintenance operation by MVA targeting an Inner
968 Shareable memory region may fail to proceed up to either the
969 Point of Coherency or to the Point of Unification of the
970 system. This workaround adds a DSB instruction before the
971 relevant cache maintenance functions and sets a specific bit
972 in the diagnostic control register of the SCU.
973
974config ARM_ERRATA_775420
975 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
976 depends on CPU_V7
977 help
978 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
979 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
980 operation aborts with MMU exception, it might cause the processor
981 to deadlock. This workaround puts DSB before executing ISB if
982 an abort may occur on cache maintenance.
983
984config ARM_ERRATA_798181
985 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
986 depends on CPU_V7 && SMP
987 help
988 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
989 adequately shooting down all use of the old entries. This
990 option enables the Linux kernel workaround for this erratum
991 which sends an IPI to the CPUs that are running the same ASID
992 as the one being invalidated.
993
994config ARM_ERRATA_773022
995 bool "ARM errata: incorrect instructions may be executed from loop buffer"
996 depends on CPU_V7
997 help
998 This option enables the workaround for the 773022 Cortex-A15
999 (up to r0p4) erratum. In certain rare sequences of code, the
1000 loop buffer may deliver incorrect instructions. This
1001 workaround disables the loop buffer to avoid the erratum.
1002
1003config ARM_ERRATA_818325_852422
1004 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1005 depends on CPU_V7
1006 help
1007 This option enables the workaround for:
1008 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1009 instruction might deadlock. Fixed in r0p1.
1010 - Cortex-A12 852422: Execution of a sequence of instructions might
1011 lead to either a data corruption or a CPU deadlock. Not fixed in
1012 any Cortex-A12 cores yet.
1013 This workaround for all both errata involves setting bit[12] of the
1014 Feature Register. This bit disables an optimisation applied to a
1015 sequence of 2 instructions that use opposing condition codes.
1016
1017config ARM_ERRATA_821420
1018 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1019 depends on CPU_V7
1020 help
1021 This option enables the workaround for the 821420 Cortex-A12
1022 (all revs) erratum. In very rare timing conditions, a sequence
1023 of VMOV to Core registers instructions, for which the second
1024 one is in the shadow of a branch or abort, can lead to a
1025 deadlock when the VMOV instructions are issued out-of-order.
1026
1027config ARM_ERRATA_825619
1028 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1029 depends on CPU_V7
1030 help
1031 This option enables the workaround for the 825619 Cortex-A12
1032 (all revs) erratum. Within rare timing constraints, executing a
1033 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1034 and Device/Strongly-Ordered loads and stores might cause deadlock
1035
1036config ARM_ERRATA_857271
1037 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1038 depends on CPU_V7
1039 help
1040 This option enables the workaround for the 857271 Cortex-A12
1041 (all revs) erratum. Under very rare timing conditions, the CPU might
1042 hang. The workaround is expected to have a < 1% performance impact.
1043
1044config ARM_ERRATA_852421
1045 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1046 depends on CPU_V7
1047 help
1048 This option enables the workaround for the 852421 Cortex-A17
1049 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1050 execution of a DMB ST instruction might fail to properly order
1051 stores from GroupA and stores from GroupB.
1052
1053config ARM_ERRATA_852423
1054 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1055 depends on CPU_V7
1056 help
1057 This option enables the workaround for:
1058 - Cortex-A17 852423: Execution of a sequence of instructions might
1059 lead to either a data corruption or a CPU deadlock. Not fixed in
1060 any Cortex-A17 cores yet.
1061 This is identical to Cortex-A12 erratum 852422. It is a separate
1062 config option from the A12 erratum due to the way errata are checked
1063 for and handled.
1064
1065config ARM_ERRATA_857272
1066 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1067 depends on CPU_V7
1068 help
1069 This option enables the workaround for the 857272 Cortex-A17 erratum.
1070 This erratum is not known to be fixed in any A17 revision.
1071 This is identical to Cortex-A12 erratum 857271. It is a separate
1072 config option from the A12 erratum due to the way errata are checked
1073 for and handled.
1074
1075endmenu
1076
1077source "arch/arm/common/Kconfig"
1078
1079menu "Bus support"
1080
1081config ISA
1082 bool
1083 help
1084 Find out whether you have ISA slots on your motherboard. ISA is the
1085 name of a bus system, i.e. the way the CPU talks to the other stuff
1086 inside your box. Other bus systems are PCI, EISA, MicroChannel
1087 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1088 newer boards don't support it. If you have ISA, say Y, otherwise N.
1089
1090
1091config ISA_DMA
1092 bool
1093 select ISA_DMA_API
1094
1095
1096config ISA_DMA_API
1097 bool
1098
1099config PCI_NANOENGINE
1100 bool "BSE nanoEngine PCI support"
1101 depends on SA1100_NANOENGINE
1102 help
1103 Enable PCI on the BSE nanoEngine board.
1104
1105config ARM_ERRATA_814220
1106 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1107 depends on CPU_V7
1108 help
1109 The v7 ARM states that all cache and branch predictor maintenance
1110 operations that do not specify an address execute, relative to
1111 each other, in program order.
1112 However, because of this erratum, an L2 set/way cache maintenance
1113 operation can overtake an L1 set/way cache maintenance operation.
1114 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1115 r0p4, r0p5.
1116
1117endmenu
1118
1119menu "Kernel Features"
1120
1121config HAVE_SMP
1122 bool
1123 help
1124 This option should be selected by machines which have an SMP-
1125 capable CPU.
1126
1127 The only effect of this option is to make the SMP-related
1128 options available to the user for configuration.
1129
1130config SMP
1131 bool "Symmetric Multi-Processing"
1132 depends on CPU_V6K || CPU_V7
1133 depends on HAVE_SMP
1134 depends on MMU || ARM_MPU
1135 select IRQ_WORK
1136 help
1137 This enables support for systems with more than one CPU. If you have
1138 a system with only one CPU, say N. If you have a system with more
1139 than one CPU, say Y.
1140
1141 If you say N here, the kernel will run on uni- and multiprocessor
1142 machines, but will use only one CPU of a multiprocessor machine. If
1143 you say Y here, the kernel will run on many, but not all,
1144 uniprocessor machines. On a uniprocessor machine, the kernel
1145 will run faster if you say N here.
1146
1147 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1148 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1149 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1150
1151 If you don't know what to do here, say N.
1152
1153config SMP_ON_UP
1154 bool "Allow booting SMP kernel on uniprocessor systems"
1155 depends on SMP && !XIP_KERNEL && MMU
1156 default y
1157 help
1158 SMP kernels contain instructions which fail on non-SMP processors.
1159 Enabling this option allows the kernel to modify itself to make
1160 these instructions safe. Disabling it allows about 1K of space
1161 savings.
1162
1163 If you don't know what to do here, say Y.
1164
1165config ARM_CPU_TOPOLOGY
1166 bool "Support cpu topology definition"
1167 depends on SMP && CPU_V7
1168 default y
1169 help
1170 Support ARM cpu topology definition. The MPIDR register defines
1171 affinity between processors which is then used to describe the cpu
1172 topology of an ARM System.
1173
1174config SCHED_MC
1175 bool "Multi-core scheduler support"
1176 depends on ARM_CPU_TOPOLOGY
1177 help
1178 Multi-core scheduler support improves the CPU scheduler's decision
1179 making when dealing with multi-core CPU chips at a cost of slightly
1180 increased overhead in some places. If unsure say N here.
1181
1182config SCHED_SMT
1183 bool "SMT scheduler support"
1184 depends on ARM_CPU_TOPOLOGY
1185 help
1186 Improves the CPU scheduler's decision making when dealing with
1187 MultiThreading at a cost of slightly increased overhead in some
1188 places. If unsure say N here.
1189
1190config HAVE_ARM_SCU
1191 bool
1192 help
1193 This option enables support for the ARM snoop control unit
1194
1195config HAVE_ARM_ARCH_TIMER
1196 bool "Architected timer support"
1197 depends on CPU_V7
1198 select ARM_ARCH_TIMER
1199 help
1200 This option enables support for the ARM architected timer
1201
1202config HAVE_ARM_TWD
1203 bool
1204 help
1205 This options enables support for the ARM timer and watchdog unit
1206
1207config MCPM
1208 bool "Multi-Cluster Power Management"
1209 depends on CPU_V7 && SMP
1210 help
1211 This option provides the common power management infrastructure
1212 for (multi-)cluster based systems, such as big.LITTLE based
1213 systems.
1214
1215config MCPM_QUAD_CLUSTER
1216 bool
1217 depends on MCPM
1218 help
1219 To avoid wasting resources unnecessarily, MCPM only supports up
1220 to 2 clusters by default.
1221 Platforms with 3 or 4 clusters that use MCPM must select this
1222 option to allow the additional clusters to be managed.
1223
1224config BIG_LITTLE
1225 bool "big.LITTLE support (Experimental)"
1226 depends on CPU_V7 && SMP
1227 select MCPM
1228 help
1229 This option enables support selections for the big.LITTLE
1230 system architecture.
1231
1232config BL_SWITCHER
1233 bool "big.LITTLE switcher support"
1234 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1235 select CPU_PM
1236 help
1237 The big.LITTLE "switcher" provides the core functionality to
1238 transparently handle transition between a cluster of A15's
1239 and a cluster of A7's in a big.LITTLE system.
1240
1241config BL_SWITCHER_DUMMY_IF
1242 tristate "Simple big.LITTLE switcher user interface"
1243 depends on BL_SWITCHER && DEBUG_KERNEL
1244 help
1245 This is a simple and dummy char dev interface to control
1246 the big.LITTLE switcher core code. It is meant for
1247 debugging purposes only.
1248
1249choice
1250 prompt "Memory split"
1251 depends on MMU
1252 default VMSPLIT_3G
1253 help
1254 Select the desired split between kernel and user memory.
1255
1256 If you are not absolutely sure what you are doing, leave this
1257 option alone!
1258
1259 config VMSPLIT_3G
1260 bool "3G/1G user/kernel split"
1261 config VMSPLIT_3G_OPT
1262 depends on !ARM_LPAE
1263 bool "3G/1G user/kernel split (for full 1G low memory)"
1264 config VMSPLIT_2G
1265 bool "2G/2G user/kernel split"
1266 config VMSPLIT_1G
1267 bool "1G/3G user/kernel split"
1268endchoice
1269
1270config PAGE_OFFSET
1271 hex
1272 default PHYS_OFFSET if !MMU
1273 default 0x40000000 if VMSPLIT_1G
1274 default 0x80000000 if VMSPLIT_2G
1275 default 0xB0000000 if VMSPLIT_3G_OPT
1276 default 0xC0000000
1277
1278config KASAN_SHADOW_OFFSET
1279 hex
1280 depends on KASAN
1281 default 0x1f000000 if PAGE_OFFSET=0x40000000
1282 default 0x5f000000 if PAGE_OFFSET=0x80000000
1283 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1284 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1285 default 0xffffffff
1286
1287config NR_CPUS
1288 int "Maximum number of CPUs (2-32)"
1289 range 2 16 if DEBUG_KMAP_LOCAL
1290 range 2 32 if !DEBUG_KMAP_LOCAL
1291 depends on SMP
1292 default "4"
1293 help
1294 The maximum number of CPUs that the kernel can support.
1295 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1296 debugging is enabled, which uses half of the per-CPU fixmap
1297 slots as guard regions.
1298
1299config HOTPLUG_CPU
1300 bool "Support for hot-pluggable CPUs"
1301 depends on SMP
1302 select GENERIC_IRQ_MIGRATION
1303 help
1304 Say Y here to experiment with turning CPUs off and on. CPUs
1305 can be controlled through /sys/devices/system/cpu.
1306
1307config ARM_PSCI
1308 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1309 depends on HAVE_ARM_SMCCC
1310 select ARM_PSCI_FW
1311 help
1312 Say Y here if you want Linux to communicate with system firmware
1313 implementing the PSCI specification for CPU-centric power
1314 management operations described in ARM document number ARM DEN
1315 0022A ("Power State Coordination Interface System Software on
1316 ARM processors").
1317
1318
1319
1320
1321config ARCH_NR_GPIO
1322 int
1323 default 2048 if ARCH_INTEL_SOCFPGA
1324 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1325 ARCH_ZYNQ || ARCH_ASPEED
1326 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1327 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1328 default 416 if ARCH_SUNXI
1329 default 392 if ARCH_U8500
1330 default 352 if ARCH_VT8500
1331 default 288 if ARCH_ROCKCHIP
1332 default 264 if MACH_H4700
1333 default 0
1334 help
1335 Maximum number of GPIOs in the system.
1336
1337 If unsure, leave the default value.
1338
1339config HZ_FIXED
1340 int
1341 default 128 if SOC_AT91RM9200
1342 default 0
1343
1344choice
1345 depends on HZ_FIXED = 0
1346 prompt "Timer frequency"
1347
1348config HZ_100
1349 bool "100 Hz"
1350
1351config HZ_200
1352 bool "200 Hz"
1353
1354config HZ_250
1355 bool "250 Hz"
1356
1357config HZ_300
1358 bool "300 Hz"
1359
1360config HZ_500
1361 bool "500 Hz"
1362
1363config HZ_1000
1364 bool "1000 Hz"
1365
1366endchoice
1367
1368config HZ
1369 int
1370 default HZ_FIXED if HZ_FIXED != 0
1371 default 100 if HZ_100
1372 default 200 if HZ_200
1373 default 250 if HZ_250
1374 default 300 if HZ_300
1375 default 500 if HZ_500
1376 default 1000
1377
1378config SCHED_HRTICK
1379 def_bool HIGH_RES_TIMERS
1380
1381config THUMB2_KERNEL
1382 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1383 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1384 default y if CPU_THUMBONLY
1385 select ARM_UNWIND
1386 help
1387 By enabling this option, the kernel will be compiled in
1388 Thumb-2 mode.
1389
1390 If unsure, say N.
1391
1392config ARM_PATCH_IDIV
1393 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1394 depends on CPU_32v7 && !XIP_KERNEL
1395 default y
1396 help
1397 The ARM compiler inserts calls to __aeabi_idiv() and
1398 __aeabi_uidiv() when it needs to perform division on signed
1399 and unsigned integers. Some v7 CPUs have support for the sdiv
1400 and udiv instructions that can be used to implement those
1401 functions.
1402
1403 Enabling this option allows the kernel to modify itself to
1404 replace the first two instructions of these library functions
1405 with the sdiv or udiv plus "bx lr" instructions when the CPU
1406 it is running on supports them. Typically this will be faster
1407 and less power intensive than running the original library
1408 code to do integer division.
1409
1410config AEABI
1411 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1412 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1413 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1414 help
1415 This option allows for the kernel to be compiled using the latest
1416 ARM ABI (aka EABI). This is only useful if you are using a user
1417 space environment that is also compiled with EABI.
1418
1419 Since there are major incompatibilities between the legacy ABI and
1420 EABI, especially with regard to structure member alignment, this
1421 option also changes the kernel syscall calling convention to
1422 disambiguate both ABIs and allow for backward compatibility support
1423 (selected with CONFIG_OABI_COMPAT).
1424
1425 To use this you need GCC version 4.0.0 or later.
1426
1427config OABI_COMPAT
1428 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1429 depends on AEABI && !THUMB2_KERNEL
1430 help
1431 This option preserves the old syscall interface along with the
1432 new (ARM EABI) one. It also provides a compatibility layer to
1433 intercept syscalls that have structure arguments which layout
1434 in memory differs between the legacy ABI and the new ARM EABI
1435 (only for non "thumb" binaries). This option adds a tiny
1436 overhead to all syscalls and produces a slightly larger kernel.
1437
1438 The seccomp filter system will not be available when this is
1439 selected, since there is no way yet to sensibly distinguish
1440 between calling conventions during filtering.
1441
1442 If you know you'll be using only pure EABI user space then you
1443 can say N here. If this option is not selected and you attempt
1444 to execute a legacy ABI binary then the result will be
1445 UNPREDICTABLE (in fact it can be predicted that it won't work
1446 at all). If in doubt say N.
1447
1448config ARCH_SELECT_MEMORY_MODEL
1449 bool
1450
1451config ARCH_FLATMEM_ENABLE
1452 bool
1453
1454config ARCH_SPARSEMEM_ENABLE
1455 bool
1456 select SPARSEMEM_STATIC if SPARSEMEM
1457
1458config HIGHMEM
1459 bool "High Memory Support"
1460 depends on MMU
1461 select KMAP_LOCAL
1462 help
1463 The address space of ARM processors is only 4 Gigabytes large
1464 and it has to accommodate user address space, kernel address
1465 space as well as some memory mapped IO. That means that, if you
1466 have a large amount of physical memory and/or IO, not all of the
1467 memory can be "permanently mapped" by the kernel. The physical
1468 memory that is not permanently mapped is called "high memory".
1469
1470 Depending on the selected kernel/user memory split, minimum
1471 vmalloc space and actual amount of RAM, you may not need this
1472 option which should result in a slightly faster kernel.
1473
1474 If unsure, say n.
1475
1476config HIGHPTE
1477 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1478 depends on HIGHMEM
1479 default y
1480 help
1481 The VM uses one page of physical memory for each page table.
1482 For systems with a lot of processes, this can use a lot of
1483 precious low memory, eventually leading to low memory being
1484 consumed by page tables. Setting this option will allow
1485 user-space 2nd level page tables to reside in high memory.
1486
1487config CPU_SW_DOMAIN_PAN
1488 bool "Enable use of CPU domains to implement privileged no-access"
1489 depends on MMU && !ARM_LPAE
1490 default y
1491 help
1492 Increase kernel security by ensuring that normal kernel accesses
1493 are unable to access userspace addresses. This can help prevent
1494 use-after-free bugs becoming an exploitable privilege escalation
1495 by ensuring that magic values (such as LIST_POISON) will always
1496 fault when dereferenced.
1497
1498 CPUs with low-vector mappings use a best-efforts implementation.
1499 Their lower 1MB needs to remain accessible for the vectors, but
1500 the remainder of userspace will become appropriately inaccessible.
1501
1502config HW_PERF_EVENTS
1503 def_bool y
1504 depends on ARM_PMU
1505
1506config ARCH_WANT_GENERAL_HUGETLB
1507 def_bool y
1508
1509config ARM_MODULE_PLTS
1510 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1511 depends on MODULES
1512 default y
1513 help
1514 Allocate PLTs when loading modules so that jumps and calls whose
1515 targets are too far away for their relative offsets to be encoded
1516 in the instructions themselves can be bounced via veneers in the
1517 module's PLT. This allows modules to be allocated in the generic
1518 vmalloc area after the dedicated module memory area has been
1519 exhausted. The modules will use slightly more memory, but after
1520 rounding up to page size, the actual memory footprint is usually
1521 the same.
1522
1523 Disabling this is usually safe for small single-platform
1524 configurations. If unsure, say y.
1525
1526config FORCE_MAX_ZONEORDER
1527 int "Maximum zone order"
1528 default "12" if SOC_AM33XX
1529 default "9" if SA1111
1530 default "11"
1531 help
1532 The kernel memory allocator divides physically contiguous memory
1533 blocks into "zones", where each zone is a power of two number of
1534 pages. This option selects the largest power of two that the kernel
1535 keeps in the memory allocator. If you need to allocate very large
1536 blocks of physically contiguous memory, then you may need to
1537 increase this value.
1538
1539 This config option is actually maximum order plus one. For example,
1540 a value of 11 means that the largest free memory block is 2^10 pages.
1541
1542config ALIGNMENT_TRAP
1543 def_bool CPU_CP15_MMU
1544 select HAVE_PROC_CPU if PROC_FS
1545 help
1546 ARM processors cannot fetch/store information which is not
1547 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1548 address divisible by 4. On 32-bit ARM processors, these non-aligned
1549 fetch/store instructions will be emulated in software if you say
1550 here, which has a severe performance impact. This is necessary for
1551 correct operation of some network protocols. With an IP-only
1552 configuration it is safe to say N, otherwise say Y.
1553
1554config UACCESS_WITH_MEMCPY
1555 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1556 depends on MMU
1557 default y if CPU_FEROCEON
1558 help
1559 Implement faster copy_to_user and clear_user methods for CPU
1560 cores where a 8-word STM instruction give significantly higher
1561 memory write throughput than a sequence of individual 32bit stores.
1562
1563 A possible side effect is a slight increase in scheduling latency
1564 between threads sharing the same address space if they invoke
1565 such copy operations with large buffers.
1566
1567 However, if the CPU data cache is using a write-allocate mode,
1568 this option is unlikely to provide any performance gain.
1569
1570config PARAVIRT
1571 bool "Enable paravirtualization code"
1572 help
1573 This changes the kernel so it can modify itself when it is run
1574 under a hypervisor, potentially improving performance significantly
1575 over full virtualization.
1576
1577config PARAVIRT_TIME_ACCOUNTING
1578 bool "Paravirtual steal time accounting"
1579 select PARAVIRT
1580 help
1581 Select this option to enable fine granularity task steal time
1582 accounting. Time spent executing other tasks in parallel with
1583 the current vCPU is discounted from the vCPU power. To account for
1584 that, there can be a small performance impact.
1585
1586 If in doubt, say N here.
1587
1588config XEN_DOM0
1589 def_bool y
1590 depends on XEN
1591
1592config XEN
1593 bool "Xen guest support on ARM"
1594 depends on ARM && AEABI && OF
1595 depends on CPU_V7 && !CPU_V6
1596 depends on !GENERIC_ATOMIC64
1597 depends on MMU
1598 select ARCH_DMA_ADDR_T_64BIT
1599 select ARM_PSCI
1600 select SWIOTLB
1601 select SWIOTLB_XEN
1602 select PARAVIRT
1603 help
1604 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1605
1606config STACKPROTECTOR_PER_TASK
1607 bool "Use a unique stack canary value for each task"
1608 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1609 select GCC_PLUGIN_ARM_SSP_PER_TASK
1610 default y
1611 help
1612 Due to the fact that GCC uses an ordinary symbol reference from
1613 which to load the value of the stack canary, this value can only
1614 change at reboot time on SMP systems, and all tasks running in the
1615 kernel's address space are forced to use the same canary value for
1616 the entire duration that the system is up.
1617
1618 Enable this option to switch to a different method that uses a
1619 different canary value for each task.
1620
1621endmenu
1622
1623menu "Boot options"
1624
1625config USE_OF
1626 bool "Flattened Device Tree support"
1627 select IRQ_DOMAIN
1628 select OF
1629 help
1630 Include support for flattened device tree machine descriptions.
1631
1632config ATAGS
1633 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1634 default y
1635 help
1636 This is the traditional way of passing data to the kernel at boot
1637 time. If you are solely relying on the flattened device tree (or
1638 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1639 to remove ATAGS support from your kernel binary. If unsure,
1640 leave this to y.
1641
1642config DEPRECATED_PARAM_STRUCT
1643 bool "Provide old way to pass kernel parameters"
1644 depends on ATAGS
1645 help
1646 This was deprecated in 2001 and announced to live on for 5 years.
1647 Some old boot loaders still use this way.
1648
1649
1650
1651config ZBOOT_ROM_TEXT
1652 hex "Compressed ROM boot loader base address"
1653 default 0x0
1654 help
1655 The physical address at which the ROM-able zImage is to be
1656 placed in the target. Platforms which normally make use of
1657 ROM-able zImage formats normally set this to a suitable
1658 value in their defconfig file.
1659
1660 If ZBOOT_ROM is not enabled, this has no effect.
1661
1662config ZBOOT_ROM_BSS
1663 hex "Compressed ROM boot loader BSS address"
1664 default 0x0
1665 help
1666 The base address of an area of read/write memory in the target
1667 for the ROM-able zImage which must be available while the
1668 decompressor is running. It must be large enough to hold the
1669 entire decompressed kernel plus an additional 128 KiB.
1670 Platforms which normally make use of ROM-able zImage formats
1671 normally set this to a suitable value in their defconfig file.
1672
1673 If ZBOOT_ROM is not enabled, this has no effect.
1674
1675config ZBOOT_ROM
1676 bool "Compressed boot loader in ROM/flash"
1677 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1678 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1679 help
1680 Say Y here if you intend to execute your compressed kernel image
1681 (zImage) directly from ROM or flash. If unsure, say N.
1682
1683config ARM_APPENDED_DTB
1684 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1685 depends on OF
1686 help
1687 With this option, the boot code will look for a device tree binary
1688 (DTB) appended to zImage
1689 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1690
1691 This is meant as a backward compatibility convenience for those
1692 systems with a bootloader that can't be upgraded to accommodate
1693 the documented boot protocol using a device tree.
1694
1695 Beware that there is very little in terms of protection against
1696 this option being confused by leftover garbage in memory that might
1697 look like a DTB header after a reboot if no actual DTB is appended
1698 to zImage. Do not leave this option active in a production kernel
1699 if you don't intend to always append a DTB. Proper passing of the
1700 location into r2 of a bootloader provided DTB is always preferable
1701 to this option.
1702
1703config ARM_ATAG_DTB_COMPAT
1704 bool "Supplement the appended DTB with traditional ATAG information"
1705 depends on ARM_APPENDED_DTB
1706 help
1707 Some old bootloaders can't be updated to a DTB capable one, yet
1708 they provide ATAGs with memory configuration, the ramdisk address,
1709 the kernel cmdline string, etc. Such information is dynamically
1710 provided by the bootloader and can't always be stored in a static
1711 DTB. To allow a device tree enabled kernel to be used with such
1712 bootloaders, this option allows zImage to extract the information
1713 from the ATAG list and store it at run time into the appended DTB.
1714
1715choice
1716 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1717 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1718
1719config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1720 bool "Use bootloader kernel arguments if available"
1721 help
1722 Uses the command-line options passed by the boot loader instead of
1723 the device tree bootargs property. If the boot loader doesn't provide
1724 any, the device tree bootargs property will be used.
1725
1726config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1727 bool "Extend with bootloader kernel arguments"
1728 help
1729 The command-line arguments provided by the boot loader will be
1730 appended to the the device tree bootargs property.
1731
1732endchoice
1733
1734config CMDLINE
1735 string "Default kernel command string"
1736 default ""
1737 help
1738 On some architectures (e.g. CATS), there is currently no way
1739 for the boot loader to pass arguments to the kernel. For these
1740 architectures, you should supply some command-line options at build
1741 time by entering them here. As a minimum, you should specify the
1742 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1743
1744choice
1745 prompt "Kernel command line type" if CMDLINE != ""
1746 default CMDLINE_FROM_BOOTLOADER
1747 depends on ATAGS
1748
1749config CMDLINE_FROM_BOOTLOADER
1750 bool "Use bootloader kernel arguments if available"
1751 help
1752 Uses the command-line options passed by the boot loader. If
1753 the boot loader doesn't provide any, the default kernel command
1754 string provided in CMDLINE will be used.
1755
1756config CMDLINE_EXTEND
1757 bool "Extend bootloader kernel arguments"
1758 help
1759 The command-line arguments provided by the boot loader will be
1760 appended to the default kernel command string.
1761
1762config CMDLINE_FORCE
1763 bool "Always use the default kernel command string"
1764 help
1765 Always use the default kernel command string, even if the boot
1766 loader passes other arguments to the kernel.
1767 This is useful if you cannot or don't want to change the
1768 command-line options your boot loader passes to the kernel.
1769endchoice
1770
1771config XIP_KERNEL
1772 bool "Kernel Execute-In-Place from ROM"
1773 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1774 help
1775 Execute-In-Place allows the kernel to run from non-volatile storage
1776 directly addressable by the CPU, such as NOR flash. This saves RAM
1777 space since the text section of the kernel is not loaded from flash
1778 to RAM. Read-write sections, such as the data section and stack,
1779 are still copied to RAM. The XIP kernel is not compressed since
1780 it has to run directly from flash, so it will take more space to
1781 store it. The flash address used to link the kernel object files,
1782 and for storing it, is configuration dependent. Therefore, if you
1783 say Y here, you must know the proper physical address where to
1784 store the kernel image depending on your own flash memory usage.
1785
1786 Also note that the make target becomes "make xipImage" rather than
1787 "make zImage" or "make Image". The final kernel binary to put in
1788 ROM memory will be arch/arm/boot/xipImage.
1789
1790 If unsure, say N.
1791
1792config XIP_PHYS_ADDR
1793 hex "XIP Kernel Physical Location"
1794 depends on XIP_KERNEL
1795 default "0x00080000"
1796 help
1797 This is the physical address in your flash memory the kernel will
1798 be linked for and stored to. This address is dependent on your
1799 own flash usage.
1800
1801config XIP_DEFLATED_DATA
1802 bool "Store kernel .data section compressed in ROM"
1803 depends on XIP_KERNEL
1804 select ZLIB_INFLATE
1805 help
1806 Before the kernel is actually executed, its .data section has to be
1807 copied to RAM from ROM. This option allows for storing that data
1808 in compressed form and decompressed to RAM rather than merely being
1809 copied, saving some precious ROM space. A possible drawback is a
1810 slightly longer boot delay.
1811
1812config KEXEC
1813 bool "Kexec system call (EXPERIMENTAL)"
1814 depends on (!SMP || PM_SLEEP_SMP)
1815 depends on MMU
1816 select KEXEC_CORE
1817 help
1818 kexec is a system call that implements the ability to shutdown your
1819 current kernel, and to start another kernel. It is like a reboot
1820 but it is independent of the system firmware. And like a reboot
1821 you can start any kernel with it, not just Linux.
1822
1823 It is an ongoing process to be certain the hardware in a machine
1824 is properly shutdown, so do not be surprised if this code does not
1825 initially work for you.
1826
1827config ATAGS_PROC
1828 bool "Export atags in procfs"
1829 depends on ATAGS && KEXEC
1830 default y
1831 help
1832 Should the atags used to boot the kernel be exported in an "atags"
1833 file in procfs. Useful with kexec.
1834
1835config CRASH_DUMP
1836 bool "Build kdump crash kernel (EXPERIMENTAL)"
1837 help
1838 Generate crash dump after being started by kexec. This should
1839 be normally only set in special crash dump kernels which are
1840 loaded in the main kernel with kexec-tools into a specially
1841 reserved region and then later executed after a crash by
1842 kdump/kexec. The crash dump kernel must be compiled to a
1843 memory address not used by the main kernel
1844
1845 For more details see Documentation/admin-guide/kdump/kdump.rst
1846
1847config AUTO_ZRELADDR
1848 bool "Auto calculation of the decompressed kernel image address"
1849 help
1850 ZRELADDR is the physical address where the decompressed kernel
1851 image will be placed. If AUTO_ZRELADDR is selected, the address
1852 will be determined at run-time, either by masking the current IP
1853 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1854 This assumes the zImage being placed in the first 128MB from
1855 start of memory.
1856
1857config EFI_STUB
1858 bool
1859
1860config EFI
1861 bool "UEFI runtime support"
1862 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1863 select UCS2_STRING
1864 select EFI_PARAMS_FROM_FDT
1865 select EFI_STUB
1866 select EFI_GENERIC_STUB
1867 select EFI_RUNTIME_WRAPPERS
1868 help
1869 This option provides support for runtime services provided
1870 by UEFI firmware (such as non-volatile variables, realtime
1871 clock, and platform reset). A UEFI stub is also provided to
1872 allow the kernel to be booted as an EFI application. This
1873 is only useful for kernels that may run on systems that have
1874 UEFI firmware.
1875
1876config DMI
1877 bool "Enable support for SMBIOS (DMI) tables"
1878 depends on EFI
1879 default y
1880 help
1881 This enables SMBIOS/DMI feature for systems.
1882
1883 This option is only useful on systems that have UEFI firmware.
1884 However, even with this option, the resultant kernel should
1885 continue to boot on existing non-UEFI platforms.
1886
1887 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1888 i.e., the the practice of identifying the platform via DMI to
1889 decide whether certain workarounds for buggy hardware and/or
1890 firmware need to be enabled. This would require the DMI subsystem
1891 to be enabled much earlier than we do on ARM, which is non-trivial.
1892
1893endmenu
1894
1895menu "CPU Power Management"
1896
1897source "drivers/cpufreq/Kconfig"
1898
1899source "drivers/cpuidle/Kconfig"
1900
1901endmenu
1902
1903menu "Floating point emulation"
1904
1905comment "At least one emulation must be selected"
1906
1907config FPE_NWFPE
1908 bool "NWFPE math emulation"
1909 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1910 help
1911 Say Y to include the NWFPE floating point emulator in the kernel.
1912 This is necessary to run most binaries. Linux does not currently
1913 support floating point hardware so you need to say Y here even if
1914 your machine has an FPA or floating point co-processor podule.
1915
1916 You may say N here if you are going to load the Acorn FPEmulator
1917 early in the bootup.
1918
1919config FPE_NWFPE_XP
1920 bool "Support extended precision"
1921 depends on FPE_NWFPE
1922 help
1923 Say Y to include 80-bit support in the kernel floating-point
1924 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1925 Note that gcc does not generate 80-bit operations by default,
1926 so in most cases this option only enlarges the size of the
1927 floating point emulator without any good reason.
1928
1929 You almost surely want to say N here.
1930
1931config FPE_FASTFPE
1932 bool "FastFPE math emulation (EXPERIMENTAL)"
1933 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1934 help
1935 Say Y here to include the FAST floating point emulator in the kernel.
1936 This is an experimental much faster emulator which now also has full
1937 precision for the mantissa. It does not support any exceptions.
1938 It is very simple, and approximately 3-6 times faster than NWFPE.
1939
1940 It should be sufficient for most programs. It may be not suitable
1941 for scientific calculations, but you have to check this for yourself.
1942 If you do not feel you need a faster FP emulation you should better
1943 choose NWFPE.
1944
1945config VFP
1946 bool "VFP-format floating point maths"
1947 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1948 help
1949 Say Y to include VFP support code in the kernel. This is needed
1950 if your hardware includes a VFP unit.
1951
1952 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1953 release notes and additional status information.
1954
1955 Say N if your target does not have VFP hardware.
1956
1957config VFPv3
1958 bool
1959 depends on VFP
1960 default y if CPU_V7
1961
1962config NEON
1963 bool "Advanced SIMD (NEON) Extension support"
1964 depends on VFPv3 && CPU_V7
1965 help
1966 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1967 Extension.
1968
1969config KERNEL_MODE_NEON
1970 bool "Support for NEON in kernel mode"
1971 depends on NEON && AEABI
1972 help
1973 Say Y to include support for NEON in kernel mode.
1974
1975endmenu
1976
1977menu "Power management options"
1978
1979source "kernel/power/Kconfig"
1980
1981config ARCH_SUSPEND_POSSIBLE
1982 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1983 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1984 def_bool y
1985
1986config ARM_CPU_SUSPEND
1987 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1988 depends on ARCH_SUSPEND_POSSIBLE
1989
1990config ARCH_HIBERNATION_POSSIBLE
1991 bool
1992 depends on MMU
1993 default y if ARCH_SUSPEND_POSSIBLE
1994
1995endmenu
1996
1997source "drivers/firmware/Kconfig"
1998
1999if CRYPTO
2000source "arch/arm/crypto/Kconfig"
2001endif
2002
2003source "arch/arm/Kconfig.assembler"
2004