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4
5#ifndef __ASM_CPUTYPE_H
6#define __ASM_CPUTYPE_H
7
8#define INVALID_HWID ULONG_MAX
9
10#define MPIDR_UP_BITMASK (0x1 << 30)
11#define MPIDR_MT_BITMASK (0x1 << 24)
12#define MPIDR_HWID_BITMASK UL(0xff00ffffff)
13
14#define MPIDR_LEVEL_BITS_SHIFT 3
15#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
16#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
17
18#define MPIDR_LEVEL_SHIFT(level) \
19 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
20
21#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
22 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
23
24#define MIDR_REVISION_MASK 0xf
25#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
26#define MIDR_PARTNUM_SHIFT 4
27#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
28#define MIDR_PARTNUM(midr) \
29 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
30#define MIDR_ARCHITECTURE_SHIFT 16
31#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
32#define MIDR_ARCHITECTURE(midr) \
33 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
34#define MIDR_VARIANT_SHIFT 20
35#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
36#define MIDR_VARIANT(midr) \
37 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
38#define MIDR_IMPLEMENTOR_SHIFT 24
39#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
40#define MIDR_IMPLEMENTOR(midr) \
41 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
42
43#define MIDR_CPU_MODEL(imp, partnum) \
44 (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
45 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
46 ((partnum) << MIDR_PARTNUM_SHIFT))
47
48#define MIDR_CPU_VAR_REV(var, rev) \
49 (((var) << MIDR_VARIANT_SHIFT) | (rev))
50
51#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
52 MIDR_ARCHITECTURE_MASK)
53
54#define ARM_CPU_IMP_ARM 0x41
55#define ARM_CPU_IMP_APM 0x50
56#define ARM_CPU_IMP_CAVIUM 0x43
57#define ARM_CPU_IMP_BRCM 0x42
58#define ARM_CPU_IMP_QCOM 0x51
59#define ARM_CPU_IMP_NVIDIA 0x4E
60#define ARM_CPU_IMP_FUJITSU 0x46
61#define ARM_CPU_IMP_HISI 0x48
62#define ARM_CPU_IMP_APPLE 0x61
63
64#define ARM_CPU_PART_AEM_V8 0xD0F
65#define ARM_CPU_PART_FOUNDATION 0xD00
66#define ARM_CPU_PART_CORTEX_A57 0xD07
67#define ARM_CPU_PART_CORTEX_A72 0xD08
68#define ARM_CPU_PART_CORTEX_A53 0xD03
69#define ARM_CPU_PART_CORTEX_A73 0xD09
70#define ARM_CPU_PART_CORTEX_A75 0xD0A
71#define ARM_CPU_PART_CORTEX_A35 0xD04
72#define ARM_CPU_PART_CORTEX_A55 0xD05
73#define ARM_CPU_PART_CORTEX_A76 0xD0B
74#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
75#define ARM_CPU_PART_CORTEX_A77 0xD0D
76
77#define APM_CPU_PART_POTENZA 0x000
78
79#define CAVIUM_CPU_PART_THUNDERX 0x0A1
80#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
81#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
82#define CAVIUM_CPU_PART_THUNDERX2 0x0AF
83
84#define BRCM_CPU_PART_BRAHMA_B53 0x100
85#define BRCM_CPU_PART_VULCAN 0x516
86
87#define QCOM_CPU_PART_FALKOR_V1 0x800
88#define QCOM_CPU_PART_FALKOR 0xC00
89#define QCOM_CPU_PART_KRYO 0x200
90#define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
91#define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
92#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
93#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
94#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
95
96#define NVIDIA_CPU_PART_DENVER 0x003
97#define NVIDIA_CPU_PART_CARMEL 0x004
98
99#define FUJITSU_CPU_PART_A64FX 0x001
100
101#define HISI_CPU_PART_TSV110 0xD01
102
103#define APPLE_CPU_PART_M1_ICESTORM 0x022
104#define APPLE_CPU_PART_M1_FIRESTORM 0x023
105
106#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
107#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
108#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
109#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
110#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
111#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
112#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
113#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
114#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
115#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
116#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
117#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
118#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
119#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
120#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
121#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
122#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
123#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
124#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
125#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
126#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
127#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
128#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
129#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
130#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
131#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
132#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
133#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
134#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
135#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
136
137
138#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
139#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
140#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
141
142#ifndef __ASSEMBLY__
143
144#include <asm/sysreg.h>
145
146#define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
147
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155
156
157struct midr_range {
158 u32 model;
159 u32 rv_min;
160 u32 rv_max;
161};
162
163#define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
164 { \
165 .model = m, \
166 .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
167 .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
168 }
169
170#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
171#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
172#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
173
174static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
175 u32 rv_max)
176{
177 u32 _model = midr & MIDR_CPU_MODEL_MASK;
178 u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);
179
180 return _model == model && rv >= rv_min && rv <= rv_max;
181}
182
183static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
184{
185 return midr_is_cpu_model_range(midr, range->model,
186 range->rv_min, range->rv_max);
187}
188
189static inline bool
190is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
191{
192 while (ranges->model)
193 if (is_midr_in_range(midr, ranges++))
194 return true;
195 return false;
196}
197
198
199
200
201
202
203static inline u32 __attribute_const__ read_cpuid_id(void)
204{
205 return read_cpuid(MIDR_EL1);
206}
207
208static inline u64 __attribute_const__ read_cpuid_mpidr(void)
209{
210 return read_cpuid(MPIDR_EL1);
211}
212
213static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
214{
215 return MIDR_IMPLEMENTOR(read_cpuid_id());
216}
217
218static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
219{
220 return MIDR_PARTNUM(read_cpuid_id());
221}
222
223static inline u32 __attribute_const__ read_cpuid_cachetype(void)
224{
225 return read_cpuid(CTR_EL0);
226}
227#endif
228
229#endif
230
