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6
7config OPENRISC
8 def_bool y
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_DMA_SET_UNCACHED
11 select ARCH_HAS_DMA_CLEAR_UNCACHED
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
13 select OF
14 select OF_EARLY_FLATTREE
15 select IRQ_DOMAIN
16 select HANDLE_DOMAIN_IRQ
17 select GPIOLIB
18 select HAVE_ARCH_TRACEHOOK
19 select SPARSE_IRQ
20 select GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW
23 select GENERIC_IOMAP
24 select GENERIC_CPU_DEVICES
25 select HAVE_UID16
26 select GENERIC_ATOMIC64
27 select GENERIC_CLOCKEVENTS_BROADCAST
28 select GENERIC_STRNCPY_FROM_USER
29 select GENERIC_STRNLEN_USER
30 select GENERIC_SMP_IDLE_THREAD
31 select MODULES_USE_ELF_RELA
32 select HAVE_DEBUG_STACKOVERFLOW
33 select OR1K_PIC
34 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
35 select ARCH_USE_QUEUED_SPINLOCKS
36 select ARCH_USE_QUEUED_RWLOCKS
37 select OMPIC if SMP
38 select ARCH_WANT_FRAME_POINTERS
39 select GENERIC_IRQ_MULTI_HANDLER
40 select MMU_GATHER_NO_RANGE if MMU
41 select SET_FS
42
43config CPU_BIG_ENDIAN
44 def_bool y
45
46config MMU
47 def_bool y
48
49config GENERIC_HWEIGHT
50 def_bool y
51
52config NO_IOPORT_MAP
53 def_bool y
54
55config TRACE_IRQFLAGS_SUPPORT
56 def_bool y
57
58
59
60config GENERIC_CSUM
61 def_bool y
62
63config STACKTRACE_SUPPORT
64 def_bool y
65
66config LOCKDEP_SUPPORT
67 def_bool y
68
69menu "Processor type and features"
70
71choice
72 prompt "Subarchitecture"
73 default OR1K_1200
74
75config OR1K_1200
76 bool "OR1200"
77 help
78 Generic OpenRISC 1200 architecture
79
80endchoice
81
82config DCACHE_WRITETHROUGH
83 bool "Have write through data caches"
84 default n
85 help
86 Select this if your implementation features write through data caches.
87 Selecting 'N' here will allow the kernel to force flushing of data
88 caches at relevant times. Most OpenRISC implementations support write-
89 through data caches.
90
91 If unsure say N here
92
93config OPENRISC_BUILTIN_DTB
94 string "Builtin DTB"
95 default ""
96
97menu "Class II Instructions"
98
99config OPENRISC_HAVE_INST_FF1
100 bool "Have instruction l.ff1"
101 default y
102 help
103 Select this if your implementation has the Class II instruction l.ff1
104
105config OPENRISC_HAVE_INST_FL1
106 bool "Have instruction l.fl1"
107 default y
108 help
109 Select this if your implementation has the Class II instruction l.fl1
110
111config OPENRISC_HAVE_INST_MUL
112 bool "Have instruction l.mul for hardware multiply"
113 default y
114 help
115 Select this if your implementation has a hardware multiply instruction
116
117config OPENRISC_HAVE_INST_DIV
118 bool "Have instruction l.div for hardware divide"
119 default y
120 help
121 Select this if your implementation has a hardware divide instruction
122endmenu
123
124config NR_CPUS
125 int "Maximum number of CPUs (2-32)"
126 range 2 32
127 depends on SMP
128 default "2"
129
130config SMP
131 bool "Symmetric Multi-Processing support"
132 help
133 This enables support for systems with more than one CPU. If you have
134 a system with only one CPU, say N. If you have a system with more
135 than one CPU, say Y.
136
137 If you don't know what to do here, say N.
138
139source "kernel/Kconfig.hz"
140
141config OPENRISC_NO_SPR_SR_DSX
142 bool "use SPR_SR_DSX software emulation" if OR1K_1200
143 default y
144 help
145 SPR_SR_DSX bit is status register bit indicating whether
146 the last exception has happened in delay slot.
147
148 OpenRISC architecture makes it optional to have it implemented
149 in hardware and the OR1200 does not have it.
150
151 Say N here if you know that your OpenRISC processor has
152 SPR_SR_DSX bit implemented. Say Y if you are unsure.
153
154config OPENRISC_HAVE_SHADOW_GPRS
155 bool "Support for shadow gpr files" if !SMP
156 default y if SMP
157 help
158 Say Y here if your OpenRISC processor features shadowed
159 register files. They will in such case be used as a
160 scratch reg storage on exception entry.
161
162 On SMP systems, this feature is mandatory.
163 On a unicore system it's safe to say N here if you are unsure.
164
165config CMDLINE
166 string "Default kernel command string"
167 default ""
168 help
169 On some architectures there is currently no way for the boot loader
170 to pass arguments to the kernel. For these architectures, you should
171 supply some command-line options at build time by entering them
172 here.
173
174menu "Debugging options"
175
176config JUMP_UPON_UNHANDLED_EXCEPTION
177 bool "Try to die gracefully"
178 default y
179 help
180 Now this puts kernel into infinite loop after first oops. Till
181 your kernel crashes this doesn't have any influence.
182
183 Say Y if you are unsure.
184
185config OPENRISC_ESR_EXCEPTION_BUG_CHECK
186 bool "Check for possible ESR exception bug"
187 default n
188 help
189 This option enables some checks that might expose some problems
190 in kernel.
191
192 Say N if you are unsure.
193
194endmenu
195
196endmenu
197
