LXR linux/arch/powerpc/include/asm/cell-pmu.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Cell Broadband Engine Performance Monitor
   4 *
   5 * (C) Copyright IBM Corporation 2006
   6 *
   7 * Author:
   8 *   David Erb (djerb@us.ibm.com)
   9 *   Kevin Corry (kevcorry@us.ibm.com)
  10 */
  11
  12#ifndef __ASM_CELL_PMU_H__
  13#define __ASM_CELL_PMU_H__
  14
  15/* The Cell PMU has four hardware performance counters, which can be
  16 * configured as four 32-bit counters or eight 16-bit counters.
  17 */
  18#define NR_PHYS_CTRS 4
  19#define NR_CTRS      (NR_PHYS_CTRS * 2)
  20
  21/* Macros for the pm_control register. */
  22#define CBE_PM_16BIT_CTR(ctr)              (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
  23#define CBE_PM_ENABLE_PERF_MON             0x80000000
  24#define CBE_PM_STOP_AT_MAX                 0x40000000
  25#define CBE_PM_TRACE_MODE_GET(pm_control)  (((pm_control) >> 28) & 0x3)
  26#define CBE_PM_TRACE_MODE_SET(mode)        (((mode)  & 0x3) << 28)
  27#define CBE_PM_TRACE_BUF_OVFLW(bit)        (((bit) & 0x1) << 17)
  28#define CBE_PM_COUNT_MODE_SET(count)       (((count) & 0x3) << 18)
  29#define CBE_PM_FREEZE_ALL_CTRS             0x00100000
  30#define CBE_PM_ENABLE_EXT_TRACE            0x00008000
  31#define CBE_PM_SPU_ADDR_TRACE_SET(msk)     (((msk) & 0x3) << 9)
  32
  33/* Macros for the trace_address register. */
  34#define CBE_PM_TRACE_BUF_FULL              0x00000800
  35#define CBE_PM_TRACE_BUF_EMPTY             0x00000400
  36#define CBE_PM_TRACE_BUF_DATA_COUNT(ta)    ((ta) & 0x3ff)
  37#define CBE_PM_TRACE_BUF_MAX_COUNT         0x400
  38
  39/* Macros for the pm07_control registers. */
  40#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
  41#define CBE_PM_CTR_INPUT_CONTROL           0x02000000
  42#define CBE_PM_CTR_POLARITY                0x01000000
  43#define CBE_PM_CTR_COUNT_CYCLES            0x00800000
  44#define CBE_PM_CTR_ENABLE                  0x00400000
  45#define PM07_CTR_INPUT_MUX(x)              (((x) & 0x3F) << 26)
  46#define PM07_CTR_INPUT_CONTROL(x)          (((x) & 1) << 25)
  47#define PM07_CTR_POLARITY(x)               (((x) & 1) << 24)
  48#define PM07_CTR_COUNT_CYCLES(x)           (((x) & 1) << 23)
  49#define PM07_CTR_ENABLE(x)                 (((x) & 1) << 22)
  50
  51/* Macros for the pm_status register. */
  52#define CBE_PM_CTR_OVERFLOW_INTR(ctr)      (1 << (31 - ((ctr) & 7)))
  53
  54enum pm_reg_name {
  55        group_control,
  56        debug_bus_control,
  57        trace_address,
  58        ext_tr_timer,
  59        pm_status,
  60        pm_control,
  61        pm_interval,
  62        pm_start_stop,
  63};
  64
  65/* Routines for reading/writing the PMU registers. */
  66extern u32  cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
  67extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
  68extern u32  cbe_read_ctr(u32 cpu, u32 ctr);
  69extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
  70
  71extern u32  cbe_read_pm07_control(u32 cpu, u32 ctr);
  72extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
  73extern u32  cbe_read_pm(u32 cpu, enum pm_reg_name reg);
  74extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
  75
  76extern u32  cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
  77extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
  78
  79extern void cbe_enable_pm(u32 cpu);
  80extern void cbe_disable_pm(u32 cpu);
  81
  82extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
  83
  84extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
  85extern void cbe_disable_pm_interrupts(u32 cpu);
  86extern u32  cbe_get_and_clear_pm_interrupts(u32 cpu);
  87extern void cbe_sync_irq(int node);
  88
  89#define CBE_COUNT_SUPERVISOR_MODE       0
  90#define CBE_COUNT_HYPERVISOR_MODE       1
  91#define CBE_COUNT_PROBLEM_MODE          2
  92#define CBE_COUNT_ALL_MODES             3
  93
  94#endif /* __ASM_CELL_PMU_H__ */
  95