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8
9#ifdef __KERNEL__
10#ifndef _ASM_DBDMA_H_
11#define _ASM_DBDMA_H_
12
13
14
15struct dbdma_regs {
16 unsigned int control;
17 unsigned int status;
18 unsigned int cmdptr_hi;
19 unsigned int cmdptr;
20 unsigned int intr_sel;
21 unsigned int br_sel;
22 unsigned int wait_sel;
23 unsigned int xfer_mode;
24 unsigned int data2ptr_hi;
25 unsigned int data2ptr;
26 unsigned int res1;
27 unsigned int address_hi;
28 unsigned int br_addr_hi;
29 unsigned int res2[3];
30};
31
32
33#define RUN 0x8000
34#define PAUSE 0x4000
35#define FLUSH 0x2000
36#define WAKE 0x1000
37#define DEAD 0x0800
38#define ACTIVE 0x0400
39#define BT 0x0100
40#define DEVSTAT 0x00ff
41
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43
44
45struct dbdma_cmd {
46 __le16 req_count;
47 __le16 command;
48 __le32 phy_addr;
49 __le32 cmd_dep;
50 __le16 res_count;
51 __le16 xfer_status;
52};
53
54
55#define OUTPUT_MORE 0
56#define OUTPUT_LAST 0x1000
57#define INPUT_MORE 0x2000
58#define INPUT_LAST 0x3000
59#define STORE_WORD 0x4000
60#define LOAD_WORD 0x5000
61#define DBDMA_NOP 0x6000
62#define DBDMA_STOP 0x7000
63
64
65#define KEY_STREAM0 0
66#define KEY_STREAM1 0x100
67#define KEY_STREAM2 0x200
68#define KEY_STREAM3 0x300
69#define KEY_REGS 0x500
70#define KEY_SYSTEM 0x600
71#define KEY_DEVICE 0x700
72
73
74#define INTR_NEVER 0
75#define INTR_IFSET 0x10
76#define INTR_IFCLR 0x20
77#define INTR_ALWAYS 0x30
78
79
80#define BR_NEVER 0
81#define BR_IFSET 0x4
82#define BR_IFCLR 0x8
83#define BR_ALWAYS 0xc
84
85
86#define WAIT_NEVER 0
87#define WAIT_IFSET 1
88#define WAIT_IFCLR 2
89#define WAIT_ALWAYS 3
90
91
92#define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
93 & -sizeof(struct dbdma_cmd))
94
95
96#define DBDMA_DO_STOP(regs) do { \
97 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
98 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
99 ; \
100} while(0)
101
102#define DBDMA_DO_RESET(regs) do { \
103 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
104 while(in_le32(&((regs)->status)) & (RUN)) \
105 ; \
106} while(0)
107
108#endif
109#endif
110