1
2#ifndef _ASM_POWERPC_IO_H
3#define _ASM_POWERPC_IO_H
4#ifdef __KERNEL__
5
6#define ARCH_HAS_IOREMAP_WC
7#ifdef CONFIG_PPC32
8#define ARCH_HAS_IOREMAP_WT
9#endif
10
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14
15extern int check_legacy_ioport(unsigned long base_port);
16#define I8042_DATA_REG 0x60
17#define FDC_BASE 0x3f0
18
19#if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20extern struct pci_dev *isa_bridge_pcidev;
21
22
23
24#define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
25#endif
26
27#include <linux/device.h>
28#include <linux/compiler.h>
29#include <linux/mm.h>
30#include <asm/page.h>
31#include <asm/byteorder.h>
32#include <asm/synch.h>
33#include <asm/delay.h>
34#include <asm/mmiowb.h>
35#include <asm/mmu.h>
36#include <asm/ppc_asm.h>
37
38#define SIO_CONFIG_RA 0x398
39#define SIO_CONFIG_RD 0x399
40
41#define SLOW_DOWN_IO
42
43
44
45
46
47#ifndef CONFIG_PCI
48#define _IO_BASE 0
49#define _ISA_MEM_BASE 0
50#define PCI_DRAM_OFFSET 0
51#elif defined(CONFIG_PPC32)
52#define _IO_BASE isa_io_base
53#define _ISA_MEM_BASE isa_mem_base
54#define PCI_DRAM_OFFSET pci_dram_offset
55#else
56#define _IO_BASE pci_io_base
57#define _ISA_MEM_BASE isa_mem_base
58#define PCI_DRAM_OFFSET 0
59#endif
60
61extern unsigned long isa_io_base;
62extern unsigned long pci_io_base;
63extern unsigned long pci_dram_offset;
64
65extern resource_size_t isa_mem_base;
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72
73extern bool isa_io_special;
74
75#ifdef CONFIG_PPC32
76#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
77#error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
78#endif
79#endif
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103#define DEF_MMIO_IN_X(name, size, insn) \
104static inline u##size name(const volatile u##size __iomem *addr) \
105{ \
106 u##size ret; \
107 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
108 : "=r" (ret) : "Z" (*addr) : "memory"); \
109 return ret; \
110}
111
112#define DEF_MMIO_OUT_X(name, size, insn) \
113static inline void name(volatile u##size __iomem *addr, u##size val) \
114{ \
115 __asm__ __volatile__("sync;"#insn" %1,%y0" \
116 : "=Z" (*addr) : "r" (val) : "memory"); \
117 mmiowb_set_pending(); \
118}
119
120#define DEF_MMIO_IN_D(name, size, insn) \
121static inline u##size name(const volatile u##size __iomem *addr) \
122{ \
123 u##size ret; \
124 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
125 : "=r" (ret) : "m"UPD_CONSTR (*addr) : "memory"); \
126 return ret; \
127}
128
129#define DEF_MMIO_OUT_D(name, size, insn) \
130static inline void name(volatile u##size __iomem *addr, u##size val) \
131{ \
132 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
133 : "=m"UPD_CONSTR (*addr) : "r" (val) : "memory"); \
134 mmiowb_set_pending(); \
135}
136
137DEF_MMIO_IN_D(in_8, 8, lbz);
138DEF_MMIO_OUT_D(out_8, 8, stb);
139
140#ifdef __BIG_ENDIAN__
141DEF_MMIO_IN_D(in_be16, 16, lhz);
142DEF_MMIO_IN_D(in_be32, 32, lwz);
143DEF_MMIO_IN_X(in_le16, 16, lhbrx);
144DEF_MMIO_IN_X(in_le32, 32, lwbrx);
145
146DEF_MMIO_OUT_D(out_be16, 16, sth);
147DEF_MMIO_OUT_D(out_be32, 32, stw);
148DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
149DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
150#else
151DEF_MMIO_IN_X(in_be16, 16, lhbrx);
152DEF_MMIO_IN_X(in_be32, 32, lwbrx);
153DEF_MMIO_IN_D(in_le16, 16, lhz);
154DEF_MMIO_IN_D(in_le32, 32, lwz);
155
156DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
157DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
158DEF_MMIO_OUT_D(out_le16, 16, sth);
159DEF_MMIO_OUT_D(out_le32, 32, stw);
160
161#endif
162
163#ifdef __powerpc64__
164
165#ifdef __BIG_ENDIAN__
166DEF_MMIO_OUT_D(out_be64, 64, std);
167DEF_MMIO_IN_D(in_be64, 64, ld);
168
169
170static inline u64 in_le64(const volatile u64 __iomem *addr)
171{
172 return swab64(in_be64(addr));
173}
174
175static inline void out_le64(volatile u64 __iomem *addr, u64 val)
176{
177 out_be64(addr, swab64(val));
178}
179#else
180DEF_MMIO_OUT_D(out_le64, 64, std);
181DEF_MMIO_IN_D(in_le64, 64, ld);
182
183
184static inline u64 in_be64(const volatile u64 __iomem *addr)
185{
186 return swab64(in_le64(addr));
187}
188
189static inline void out_be64(volatile u64 __iomem *addr, u64 val)
190{
191 out_le64(addr, swab64(val));
192}
193
194#endif
195#endif
196
197
198
199
200extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
201extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
202extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
203extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
204extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
205extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
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210#define _insw _insw_ns
211#define _insl _insl_ns
212#define _outsw _outsw_ns
213#define _outsl _outsl_ns
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220extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
221extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
222 unsigned long n);
223extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
224 unsigned long n);
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244#ifdef CONFIG_EEH
245#include <asm/eeh.h>
246#endif
247
248
249#define PCI_IO_ADDR volatile void __iomem *
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277#ifdef CONFIG_PPC_INDIRECT_MMIO
278#define PCI_IO_IND_TOKEN_SHIFT 52
279#define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
280#define PCI_FIX_ADDR(addr) \
281 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
282#define PCI_GET_ADDR_TOKEN(addr) \
283 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
284 PCI_IO_IND_TOKEN_SHIFT)
285#define PCI_SET_ADDR_TOKEN(addr, token) \
286do { \
287 unsigned long __a = (unsigned long)(addr); \
288 __a &= ~PCI_IO_IND_TOKEN_MASK; \
289 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
290 (addr) = (void __iomem *)__a; \
291} while(0)
292#else
293#define PCI_FIX_ADDR(addr) (addr)
294#endif
295
296
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298
299
300
301static inline unsigned char __raw_readb(const volatile void __iomem *addr)
302{
303 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
304}
305#define __raw_readb __raw_readb
306
307static inline unsigned short __raw_readw(const volatile void __iomem *addr)
308{
309 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
310}
311#define __raw_readw __raw_readw
312
313static inline unsigned int __raw_readl(const volatile void __iomem *addr)
314{
315 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
316}
317#define __raw_readl __raw_readl
318
319static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
320{
321 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
322}
323#define __raw_writeb __raw_writeb
324
325static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
326{
327 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
328}
329#define __raw_writew __raw_writew
330
331static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
332{
333 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
334}
335#define __raw_writel __raw_writel
336
337#ifdef __powerpc64__
338static inline unsigned long __raw_readq(const volatile void __iomem *addr)
339{
340 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
341}
342#define __raw_readq __raw_readq
343
344static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
345{
346 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
347}
348#define __raw_writeq __raw_writeq
349
350static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
351{
352 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
353}
354#define __raw_writeq_be __raw_writeq_be
355
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359
360static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
361{
362 __asm__ __volatile__("stbcix %0,0,%1"
363 : : "r" (val), "r" (paddr) : "memory");
364}
365
366static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
367{
368 __asm__ __volatile__("sthcix %0,0,%1"
369 : : "r" (val), "r" (paddr) : "memory");
370}
371
372static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
373{
374 __asm__ __volatile__("stwcix %0,0,%1"
375 : : "r" (val), "r" (paddr) : "memory");
376}
377
378static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
379{
380 __asm__ __volatile__("stdcix %0,0,%1"
381 : : "r" (val), "r" (paddr) : "memory");
382}
383
384static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
385{
386 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
387}
388
389static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
390{
391 u8 ret;
392 __asm__ __volatile__("lbzcix %0,0, %1"
393 : "=r" (ret) : "r" (paddr) : "memory");
394 return ret;
395}
396
397static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
398{
399 u16 ret;
400 __asm__ __volatile__("lhzcix %0,0, %1"
401 : "=r" (ret) : "r" (paddr) : "memory");
402 return ret;
403}
404
405static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
406{
407 u32 ret;
408 __asm__ __volatile__("lwzcix %0,0, %1"
409 : "=r" (ret) : "r" (paddr) : "memory");
410 return ret;
411}
412
413static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
414{
415 u64 ret;
416 __asm__ __volatile__("ldcix %0,0, %1"
417 : "=r" (ret) : "r" (paddr) : "memory");
418 return ret;
419}
420#endif
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435
436#ifdef CONFIG_PPC32
437
438#define __do_in_asm(name, op) \
439static inline unsigned int name(unsigned int port) \
440{ \
441 unsigned int x; \
442 __asm__ __volatile__( \
443 "sync\n" \
444 "0:" op " %0,0,%1\n" \
445 "1: twi 0,%0,0\n" \
446 "2: isync\n" \
447 "3: nop\n" \
448 "4:\n" \
449 ".section .fixup,\"ax\"\n" \
450 "5: li %0,-1\n" \
451 " b 4b\n" \
452 ".previous\n" \
453 EX_TABLE(0b, 5b) \
454 EX_TABLE(1b, 5b) \
455 EX_TABLE(2b, 5b) \
456 EX_TABLE(3b, 5b) \
457 : "=&r" (x) \
458 : "r" (port + _IO_BASE) \
459 : "memory"); \
460 return x; \
461}
462
463#define __do_out_asm(name, op) \
464static inline void name(unsigned int val, unsigned int port) \
465{ \
466 __asm__ __volatile__( \
467 "sync\n" \
468 "0:" op " %0,0,%1\n" \
469 "1: sync\n" \
470 "2:\n" \
471 EX_TABLE(0b, 2b) \
472 EX_TABLE(1b, 2b) \
473 : : "r" (val), "r" (port + _IO_BASE) \
474 : "memory"); \
475}
476
477__do_in_asm(_rec_inb, "lbzx")
478__do_in_asm(_rec_inw, "lhbrx")
479__do_in_asm(_rec_inl, "lwbrx")
480__do_out_asm(_rec_outb, "stbx")
481__do_out_asm(_rec_outw, "sthbrx")
482__do_out_asm(_rec_outl, "stwbrx")
483
484#endif
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501#define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
502#define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
503#define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
504#define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
505#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
506#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
507#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
508
509#ifdef CONFIG_EEH
510#define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
511#define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
512#define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
513#define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
514#define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
515#define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
516#define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
517#else
518#define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
519#define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
520#define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
521#define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
522#define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
523#define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
524#define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
525#endif
526
527#ifdef CONFIG_PPC32
528#define __do_outb(val, port) _rec_outb(val, port)
529#define __do_outw(val, port) _rec_outw(val, port)
530#define __do_outl(val, port) _rec_outl(val, port)
531#define __do_inb(port) _rec_inb(port)
532#define __do_inw(port) _rec_inw(port)
533#define __do_inl(port) _rec_inl(port)
534#else
535#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
536#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
537#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
538#define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
539#define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
540#define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
541#endif
542
543#ifdef CONFIG_EEH
544#define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
545#define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
546#define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
547#else
548#define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
549#define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
550#define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
551#endif
552#define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
553#define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
554#define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
555
556#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
557#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
558#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
559#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
560#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
561#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
562
563#define __do_memset_io(addr, c, n) \
564 _memset_io(PCI_FIX_ADDR(addr), c, n)
565#define __do_memcpy_toio(dst, src, n) \
566 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
567
568#ifdef CONFIG_EEH
569#define __do_memcpy_fromio(dst, src, n) \
570 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
571#else
572#define __do_memcpy_fromio(dst, src, n) \
573 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
574#endif
575
576#ifdef CONFIG_PPC_INDIRECT_PIO
577#define DEF_PCI_HOOK_pio(x) x
578#else
579#define DEF_PCI_HOOK_pio(x) NULL
580#endif
581
582#ifdef CONFIG_PPC_INDIRECT_MMIO
583#define DEF_PCI_HOOK_mem(x) x
584#else
585#define DEF_PCI_HOOK_mem(x) NULL
586#endif
587
588
589extern struct ppc_pci_io {
590
591#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
592#define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
593
594#include <asm/io-defs.h>
595
596#undef DEF_PCI_AC_RET
597#undef DEF_PCI_AC_NORET
598
599} ppc_pci_io;
600
601
602#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
603static inline ret name at \
604{ \
605 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
606 return ppc_pci_io.name al; \
607 return __do_##name al; \
608}
609
610#define DEF_PCI_AC_NORET(name, at, al, space, aa) \
611static inline void name at \
612{ \
613 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
614 ppc_pci_io.name al; \
615 else \
616 __do_##name al; \
617}
618
619#include <asm/io-defs.h>
620
621#undef DEF_PCI_AC_RET
622#undef DEF_PCI_AC_NORET
623
624
625
626
627#define readb readb
628#define readw readw
629#define readl readl
630#define writeb writeb
631#define writew writew
632#define writel writel
633#define readsb readsb
634#define readsw readsw
635#define readsl readsl
636#define writesb writesb
637#define writesw writesw
638#define writesl writesl
639#define inb inb
640#define inw inw
641#define inl inl
642#define outb outb
643#define outw outw
644#define outl outl
645#define insb insb
646#define insw insw
647#define insl insl
648#define outsb outsb
649#define outsw outsw
650#define outsl outsl
651#ifdef __powerpc64__
652#define readq readq
653#define writeq writeq
654#endif
655#define memset_io memset_io
656#define memcpy_fromio memcpy_fromio
657#define memcpy_toio memcpy_toio
658
659
660
661
662
663#define xlate_dev_mem_ptr(p) __va(p)
664
665
666
667
668#define readb_relaxed(addr) readb(addr)
669#define readw_relaxed(addr) readw(addr)
670#define readl_relaxed(addr) readl(addr)
671#define readq_relaxed(addr) readq(addr)
672#define writeb_relaxed(v, addr) writeb(v, addr)
673#define writew_relaxed(v, addr) writew(v, addr)
674#define writel_relaxed(v, addr) writel(v, addr)
675#define writeq_relaxed(v, addr) writeq(v, addr)
676
677#ifdef CONFIG_GENERIC_IOMAP
678#include <asm-generic/iomap.h>
679#else
680
681
682
683static inline unsigned int ioread16be(const void __iomem *addr)
684{
685 return readw_be(addr);
686}
687#define ioread16be ioread16be
688
689static inline unsigned int ioread32be(const void __iomem *addr)
690{
691 return readl_be(addr);
692}
693#define ioread32be ioread32be
694
695#ifdef __powerpc64__
696static inline u64 ioread64_lo_hi(const void __iomem *addr)
697{
698 return readq(addr);
699}
700#define ioread64_lo_hi ioread64_lo_hi
701
702static inline u64 ioread64_hi_lo(const void __iomem *addr)
703{
704 return readq(addr);
705}
706#define ioread64_hi_lo ioread64_hi_lo
707
708static inline u64 ioread64be(const void __iomem *addr)
709{
710 return readq_be(addr);
711}
712#define ioread64be ioread64be
713
714static inline u64 ioread64be_lo_hi(const void __iomem *addr)
715{
716 return readq_be(addr);
717}
718#define ioread64be_lo_hi ioread64be_lo_hi
719
720static inline u64 ioread64be_hi_lo(const void __iomem *addr)
721{
722 return readq_be(addr);
723}
724#define ioread64be_hi_lo ioread64be_hi_lo
725#endif
726
727static inline void iowrite16be(u16 val, void __iomem *addr)
728{
729 writew_be(val, addr);
730}
731#define iowrite16be iowrite16be
732
733static inline void iowrite32be(u32 val, void __iomem *addr)
734{
735 writel_be(val, addr);
736}
737#define iowrite32be iowrite32be
738
739#ifdef __powerpc64__
740static inline void iowrite64_lo_hi(u64 val, void __iomem *addr)
741{
742 writeq(val, addr);
743}
744#define iowrite64_lo_hi iowrite64_lo_hi
745
746static inline void iowrite64_hi_lo(u64 val, void __iomem *addr)
747{
748 writeq(val, addr);
749}
750#define iowrite64_hi_lo iowrite64_hi_lo
751
752static inline void iowrite64be(u64 val, void __iomem *addr)
753{
754 writeq_be(val, addr);
755}
756#define iowrite64be iowrite64be
757
758static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr)
759{
760 writeq_be(val, addr);
761}
762#define iowrite64be_lo_hi iowrite64be_lo_hi
763
764static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr)
765{
766 writeq_be(val, addr);
767}
768#define iowrite64be_hi_lo iowrite64be_hi_lo
769#endif
770
771struct pci_dev;
772void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
773#define pci_iounmap pci_iounmap
774void __iomem *ioport_map(unsigned long port, unsigned int len);
775#define ioport_map ioport_map
776#endif
777
778static inline void iosync(void)
779{
780 __asm__ __volatile__ ("sync" : : : "memory");
781}
782
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789
790#define iobarrier_rw() eieio()
791#define iobarrier_r() eieio()
792#define iobarrier_w() eieio()
793
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798
799#define inb_p(port) inb(port)
800#define outb_p(val, port) (udelay(1), outb((val), (port)))
801#define inw_p(port) inw(port)
802#define outw_p(val, port) (udelay(1), outw((val), (port)))
803#define inl_p(port) inl(port)
804#define outl_p(val, port) (udelay(1), outl((val), (port)))
805
806
807#define IO_SPACE_LIMIT ~(0UL)
808
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840extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
841extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
842 unsigned long flags);
843extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
844#define ioremap_wc ioremap_wc
845
846#ifdef CONFIG_PPC32
847void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
848#define ioremap_wt ioremap_wt
849#endif
850
851void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
852#define ioremap_uc(addr, size) ioremap((addr), (size))
853#define ioremap_cache(addr, size) \
854 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
855
856extern void iounmap(volatile void __iomem *addr);
857
858void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
859
860int early_ioremap_range(unsigned long ea, phys_addr_t pa,
861 unsigned long size, pgprot_t prot);
862void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
863 pgprot_t prot, void *caller);
864
865extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
866 pgprot_t prot, void *caller);
867
868
869
870
871
872
873
874#define HAVE_ARCH_PIO_SIZE 1
875#define PIO_OFFSET 0x00000000UL
876#define PIO_MASK (FULL_IO_SIZE - 1)
877#define PIO_RESERVED (FULL_IO_SIZE)
878
879#define mmio_read16be(addr) readw_be(addr)
880#define mmio_read32be(addr) readl_be(addr)
881#define mmio_read64be(addr) readq_be(addr)
882#define mmio_write16be(val, addr) writew_be(val, addr)
883#define mmio_write32be(val, addr) writel_be(val, addr)
884#define mmio_write64be(val, addr) writeq_be(val, addr)
885#define mmio_insb(addr, dst, count) readsb(addr, dst, count)
886#define mmio_insw(addr, dst, count) readsw(addr, dst, count)
887#define mmio_insl(addr, dst, count) readsl(addr, dst, count)
888#define mmio_outsb(addr, src, count) writesb(addr, src, count)
889#define mmio_outsw(addr, src, count) writesw(addr, src, count)
890#define mmio_outsl(addr, src, count) writesl(addr, src, count)
891
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904static inline unsigned long virt_to_phys(volatile void * address)
905{
906 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
907
908 return __pa((unsigned long)address);
909}
910#define virt_to_phys virt_to_phys
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924static inline void * phys_to_virt(unsigned long address)
925{
926 return (void *)__va(address);
927}
928#define phys_to_virt phys_to_virt
929
930
931
932
933static inline phys_addr_t page_to_phys(struct page *page)
934{
935 unsigned long pfn = page_to_pfn(page);
936
937 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
938
939 return PFN_PHYS(pfn);
940}
941
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947
948#ifdef CONFIG_PPC32
949
950static inline unsigned long virt_to_bus(volatile void * address)
951{
952 if (address == NULL)
953 return 0;
954 return __pa(address) + PCI_DRAM_OFFSET;
955}
956#define virt_to_bus virt_to_bus
957
958static inline void * bus_to_virt(unsigned long address)
959{
960 if (address == 0)
961 return NULL;
962 return __va(address - PCI_DRAM_OFFSET);
963}
964#define bus_to_virt bus_to_virt
965
966#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
967
968#endif
969
970
971#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
972#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
973
974#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
975#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
976
977#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
978#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
979
980
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986
987#define clrsetbits(type, addr, clear, set) \
988 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
989
990#ifdef __powerpc64__
991#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
992#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
993#endif
994
995#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
996#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
997
998#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
999#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
1000
1001#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
1002
1003#include <asm-generic/io.h>
1004
1005#endif
1006
1007#endif
1008