LXR linux/arch/powerpc/include/asm/pnv-ocxl.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2// Copyright 2017 IBM Corp.
   3#ifndef _ASM_PNV_OCXL_H
   4#define _ASM_PNV_OCXL_H
   5
   6#include <linux/bitfield.h>
   7#include <linux/pci.h>
   8
   9#define PNV_OCXL_TL_MAX_TEMPLATE        63
  10#define PNV_OCXL_TL_BITS_PER_RATE       4
  11#define PNV_OCXL_TL_RATE_BUF_SIZE       ((PNV_OCXL_TL_MAX_TEMPLATE+1) * PNV_OCXL_TL_BITS_PER_RATE / 8)
  12
  13#define PNV_OCXL_ATSD_TIMEOUT           1
  14
  15/* TLB Management Instructions */
  16#define PNV_OCXL_ATSD_LNCH              0x00
  17/* Radix Invalidate */
  18#define   PNV_OCXL_ATSD_LNCH_R          PPC_BIT(0)
  19/* Radix Invalidation Control
  20 * 0b00 Just invalidate TLB.
  21 * 0b01 Invalidate just Page Walk Cache.
  22 * 0b10 Invalidate TLB, Page Walk Cache, and any
  23 * caching of Partition and Process Table Entries.
  24 */
  25#define   PNV_OCXL_ATSD_LNCH_RIC        PPC_BITMASK(1, 2)
  26/* Number and Page Size of translations to be invalidated */
  27#define   PNV_OCXL_ATSD_LNCH_LP         PPC_BITMASK(3, 10)
  28/* Invalidation Criteria
  29 * 0b00 Invalidate just the target VA.
  30 * 0b01 Invalidate matching PID.
  31 */
  32#define   PNV_OCXL_ATSD_LNCH_IS         PPC_BITMASK(11, 12)
  33/* 0b1: Process Scope, 0b0: Partition Scope */
  34#define   PNV_OCXL_ATSD_LNCH_PRS        PPC_BIT(13)
  35/* Invalidation Flag */
  36#define   PNV_OCXL_ATSD_LNCH_B          PPC_BIT(14)
  37/* Actual Page Size to be invalidated
  38 * 000 4KB
  39 * 101 64KB
  40 * 001 2MB
  41 * 010 1GB
  42 */
  43#define   PNV_OCXL_ATSD_LNCH_AP         PPC_BITMASK(15, 17)
  44/* Defines the large page select
  45 * L=0b0 for 4KB pages
  46 * L=0b1 for large pages)
  47 */
  48#define   PNV_OCXL_ATSD_LNCH_L          PPC_BIT(18)
  49/* Process ID */
  50#define   PNV_OCXL_ATSD_LNCH_PID        PPC_BITMASK(19, 38)
  51/* NoFlush – Assumed to be 0b0 */
  52#define   PNV_OCXL_ATSD_LNCH_F          PPC_BIT(39)
  53#define   PNV_OCXL_ATSD_LNCH_OCAPI_SLBI PPC_BIT(40)
  54#define   PNV_OCXL_ATSD_LNCH_OCAPI_SINGLETON    PPC_BIT(41)
  55#define PNV_OCXL_ATSD_AVA               0x08
  56#define   PNV_OCXL_ATSD_AVA_AVA         PPC_BITMASK(0, 51)
  57#define PNV_OCXL_ATSD_STAT              0x10
  58
  59int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled, u16 *supported);
  60int pnv_ocxl_get_pasid_count(struct pci_dev *dev, int *count);
  61
  62int pnv_ocxl_get_tl_cap(struct pci_dev *dev, long *cap,
  63                        char *rate_buf, int rate_buf_size);
  64int pnv_ocxl_set_tl_conf(struct pci_dev *dev, long cap,
  65                         uint64_t rate_buf_phys, int rate_buf_size);
  66
  67int pnv_ocxl_get_xsl_irq(struct pci_dev *dev, int *hwirq);
  68void pnv_ocxl_unmap_xsl_regs(void __iomem *dsisr, void __iomem *dar,
  69                             void __iomem *tfc, void __iomem *pe_handle);
  70int pnv_ocxl_map_xsl_regs(struct pci_dev *dev, void __iomem **dsisr,
  71                          void __iomem **dar, void __iomem **tfc,
  72                          void __iomem **pe_handle);
  73
  74int pnv_ocxl_spa_setup(struct pci_dev *dev, void *spa_mem, int PE_mask, void **platform_data);
  75void pnv_ocxl_spa_release(void *platform_data);
  76int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle);
  77
  78int pnv_ocxl_map_lpar(struct pci_dev *dev, uint64_t lparid,
  79                      uint64_t lpcr, void __iomem **arva);
  80void pnv_ocxl_unmap_lpar(void __iomem *arva);
  81void pnv_ocxl_tlb_invalidate(void __iomem *arva,
  82                             unsigned long pid,
  83                             unsigned long addr,
  84                             unsigned long page_size);
  85#endif /* _ASM_PNV_OCXL_H */
  86