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10#ifndef _ASM_POWERPC_REG_H
11#define _ASM_POWERPC_REG_H
12#ifdef __KERNEL__
13
14#include <linux/stringify.h>
15#include <linux/const.h>
16#include <asm/cputable.h>
17#include <asm/asm-const.h>
18#include <asm/feature-fixups.h>
19
20
21#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
22#include <asm/reg_booke.h>
23#endif
24
25#ifdef CONFIG_FSL_EMB_PERFMON
26#include <asm/reg_fsl_emb.h>
27#endif
28
29#include <asm/reg_8xx.h>
30
31#define MSR_SF_LG 63
32#define MSR_HV_LG 60
33#define MSR_TS_T_LG 34
34#define MSR_TS_S_LG 33
35#define MSR_TS_LG 33
36#define MSR_TM_LG 32
37#define MSR_VEC_LG 25
38#define MSR_VSX_LG 23
39#define MSR_S_LG 22
40#define MSR_POW_LG 18
41#define MSR_WE_LG 18
42#define MSR_TGPR_LG 17
43#define MSR_CE_LG 17
44#define MSR_ILE_LG 16
45#define MSR_EE_LG 15
46#define MSR_PR_LG 14
47#define MSR_FP_LG 13
48#define MSR_ME_LG 12
49#define MSR_FE0_LG 11
50#define MSR_SE_LG 10
51#define MSR_BE_LG 9
52#define MSR_DE_LG 9
53#define MSR_FE1_LG 8
54#define MSR_IP_LG 6
55#define MSR_IR_LG 5
56#define MSR_DR_LG 4
57#define MSR_PE_LG 3
58#define MSR_PX_LG 2
59#define MSR_PMM_LG 2
60#define MSR_RI_LG 1
61#define MSR_LE_LG 0
62
63#ifdef __ASSEMBLY__
64#define __MASK(X) (1<<(X))
65#else
66#define __MASK(X) (1UL<<(X))
67#endif
68
69#ifdef CONFIG_PPC64
70#define MSR_SF __MASK(MSR_SF_LG)
71#define MSR_HV __MASK(MSR_HV_LG)
72#define MSR_S __MASK(MSR_S_LG)
73#else
74
75#define MSR_SF 0
76#define MSR_HV 0
77#define MSR_S 0
78#endif
79
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83
84#ifndef MSR_SPE
85#define MSR_SPE 0
86#endif
87
88#define MSR_VEC __MASK(MSR_VEC_LG)
89#define MSR_VSX __MASK(MSR_VSX_LG)
90#define MSR_POW __MASK(MSR_POW_LG)
91#define MSR_WE __MASK(MSR_WE_LG)
92#define MSR_TGPR __MASK(MSR_TGPR_LG)
93#define MSR_CE __MASK(MSR_CE_LG)
94#define MSR_ILE __MASK(MSR_ILE_LG)
95#define MSR_EE __MASK(MSR_EE_LG)
96#define MSR_PR __MASK(MSR_PR_LG)
97#define MSR_FP __MASK(MSR_FP_LG)
98#define MSR_ME __MASK(MSR_ME_LG)
99#define MSR_FE0 __MASK(MSR_FE0_LG)
100#define MSR_SE __MASK(MSR_SE_LG)
101#define MSR_BE __MASK(MSR_BE_LG)
102#define MSR_DE __MASK(MSR_DE_LG)
103#define MSR_FE1 __MASK(MSR_FE1_LG)
104#define MSR_IP __MASK(MSR_IP_LG)
105#define MSR_IR __MASK(MSR_IR_LG)
106#define MSR_DR __MASK(MSR_DR_LG)
107#define MSR_PE __MASK(MSR_PE_LG)
108#define MSR_PX __MASK(MSR_PX_LG)
109#ifndef MSR_PMM
110#define MSR_PMM __MASK(MSR_PMM_LG)
111#endif
112#define MSR_RI __MASK(MSR_RI_LG)
113#define MSR_LE __MASK(MSR_LE_LG)
114
115#define MSR_TM __MASK(MSR_TM_LG)
116#define MSR_TS_N 0
117#define MSR_TS_S __MASK(MSR_TS_S_LG)
118#define MSR_TS_T __MASK(MSR_TS_T_LG)
119#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S)
120#define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK)
121#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
122#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
123
124#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
125#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0)
126#else
127#define MSR_TM_ACTIVE(x) ((void)(x), 0)
128#endif
129
130#if defined(CONFIG_PPC_BOOK3S_64)
131#define MSR_64BIT MSR_SF
132
133
134#define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_HV)
135#ifdef __BIG_ENDIAN__
136#define MSR_ __MSR
137#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
138#else
139#define MSR_ (__MSR | MSR_LE)
140#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
141#endif
142#define MSR_KERNEL (MSR_ | MSR_64BIT)
143#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
144#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
145#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
146
147#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
148#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
149#endif
150
151#ifndef MSR_64BIT
152#define MSR_64BIT 0
153#endif
154
155
156#define CR0_SHIFT 28
157#define CR0_MASK 0xF
158#define CR0_TBEGIN_FAILURE (0x2 << 28)
159
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161
162#define PSSCR_RL_MASK 0x0000000F
163#define PSSCR_MTL_MASK 0x000000F0
164#define PSSCR_TR_MASK 0x00000300
165#define PSSCR_PSLL_MASK 0x000F0000
166#define PSSCR_EC 0x00100000
167#define PSSCR_ESL 0x00200000
168#define PSSCR_SD 0x00400000
169#define PSSCR_PLS 0xf000000000000000
170#define PSSCR_PLS_SHIFT 60
171#define PSSCR_GUEST_VIS 0xf0000000000003ffUL
172#define PSSCR_FAKE_SUSPEND 0x00000400
173#define PSSCR_FAKE_SUSPEND_LG 10
174
175
176#define FPSCR_FX 0x80000000
177#define FPSCR_FEX 0x40000000
178#define FPSCR_VX 0x20000000
179#define FPSCR_OX 0x10000000
180#define FPSCR_UX 0x08000000
181#define FPSCR_ZX 0x04000000
182#define FPSCR_XX 0x02000000
183#define FPSCR_VXSNAN 0x01000000
184#define FPSCR_VXISI 0x00800000
185#define FPSCR_VXIDI 0x00400000
186#define FPSCR_VXZDZ 0x00200000
187#define FPSCR_VXIMZ 0x00100000
188#define FPSCR_VXVC 0x00080000
189#define FPSCR_FR 0x00040000
190#define FPSCR_FI 0x00020000
191#define FPSCR_FPRF 0x0001f000
192#define FPSCR_FPCC 0x0000f000
193#define FPSCR_VXSOFT 0x00000400
194#define FPSCR_VXSQRT 0x00000200
195#define FPSCR_VXCVI 0x00000100
196#define FPSCR_VE 0x00000080
197#define FPSCR_OE 0x00000040
198#define FPSCR_UE 0x00000020
199#define FPSCR_ZE 0x00000010
200#define FPSCR_XE 0x00000008
201#define FPSCR_NI 0x00000004
202#define FPSCR_RN 0x00000003
203
204
205#define SPEFSCR_SOVH 0x80000000
206#define SPEFSCR_OVH 0x40000000
207#define SPEFSCR_FGH 0x20000000
208#define SPEFSCR_FXH 0x10000000
209#define SPEFSCR_FINVH 0x08000000
210#define SPEFSCR_FDBZH 0x04000000
211#define SPEFSCR_FUNFH 0x02000000
212#define SPEFSCR_FOVFH 0x01000000
213#define SPEFSCR_FINXS 0x00200000
214#define SPEFSCR_FINVS 0x00100000
215#define SPEFSCR_FDBZS 0x00080000
216#define SPEFSCR_FUNFS 0x00040000
217#define SPEFSCR_FOVFS 0x00020000
218#define SPEFSCR_MODE 0x00010000
219#define SPEFSCR_SOV 0x00008000
220#define SPEFSCR_OV 0x00004000
221#define SPEFSCR_FG 0x00002000
222#define SPEFSCR_FX 0x00001000
223#define SPEFSCR_FINV 0x00000800
224#define SPEFSCR_FDBZ 0x00000400
225#define SPEFSCR_FUNF 0x00000200
226#define SPEFSCR_FOVF 0x00000100
227#define SPEFSCR_FINXE 0x00000040
228#define SPEFSCR_FINVE 0x00000020
229#define SPEFSCR_FDBZE 0x00000010
230#define SPEFSCR_FUNFE 0x00000008
231#define SPEFSCR_FOVFE 0x00000004
232#define SPEFSCR_FRMC 0x00000003
233
234
235
236#ifdef CONFIG_40x
237#define SPRN_PID 0x3B1
238#else
239#define SPRN_PID 0x030
240#ifdef CONFIG_BOOKE
241#define SPRN_PID0 SPRN_PID
242#endif
243#endif
244
245#define SPRN_CTR 0x009
246#define SPRN_DSCR 0x11
247#define SPRN_CFAR 0x1c
248#define SPRN_AMR 0x1d
249#define SPRN_UAMOR 0x9d
250#define SPRN_AMOR 0x15d
251#define SPRN_ACOP 0x1F
252#define SPRN_TFIAR 0x81
253#define SPRN_TEXASR 0x82
254#define SPRN_TEXASRU 0x83
255
256#define TEXASR_FC_LG (63 - 7)
257#define TEXASR_AB_LG (63 - 31)
258#define TEXASR_SU_LG (63 - 32)
259#define TEXASR_HV_LG (63 - 34)
260#define TEXASR_PR_LG (63 - 35)
261#define TEXASR_FS_LG (63 - 36)
262#define TEXASR_EX_LG (63 - 37)
263#define TEXASR_ROT_LG (63 - 38)
264
265#define TEXASR_ABORT __MASK(TEXASR_AB_LG)
266#define TEXASR_SUSP __MASK(TEXASR_SU_LG)
267#define TEXASR_HV __MASK(TEXASR_HV_LG)
268#define TEXASR_PR __MASK(TEXASR_PR_LG)
269#define TEXASR_FS __MASK(TEXASR_FS_LG)
270#define TEXASR_EXACT __MASK(TEXASR_EX_LG)
271#define TEXASR_ROT __MASK(TEXASR_ROT_LG)
272#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG)
273
274#define SPRN_TFHAR 0x80
275
276#define SPRN_TIDR 144
277#define SPRN_CTRLF 0x088
278#define SPRN_CTRLT 0x098
279#define CTRL_CT 0xc0000000
280#define CTRL_CT0 0x80000000
281#define CTRL_CT1 0x40000000
282#define CTRL_TE 0x00c00000
283#define CTRL_RUNLATCH 0x1
284#define SPRN_DAWR0 0xB4
285#define SPRN_DAWR1 0xB5
286#define SPRN_RPR 0xBA
287#define SPRN_CIABR 0xBB
288#define CIABR_PRIV 0x3
289#define CIABR_PRIV_USER 1
290#define CIABR_PRIV_SUPER 2
291#define CIABR_PRIV_HYPER 3
292#define SPRN_DAWRX0 0xBC
293#define SPRN_DAWRX1 0xBD
294#define DAWRX_USER __MASK(0)
295#define DAWRX_KERNEL __MASK(1)
296#define DAWRX_HYP __MASK(2)
297#define DAWRX_WTI __MASK(3)
298#define DAWRX_WT __MASK(4)
299#define DAWRX_DR __MASK(5)
300#define DAWRX_DW __MASK(6)
301#define SPRN_DABR 0x3F5
302#define SPRN_DABR2 0x13D
303#define SPRN_DABRX 0x3F7
304#define DABRX_USER __MASK(0)
305#define DABRX_KERNEL __MASK(1)
306#define DABRX_HYP __MASK(2)
307#define DABRX_BTI __MASK(3)
308#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
309#define SPRN_DAR 0x013
310#define SPRN_DBCR 0x136
311#define SPRN_DSISR 0x012
312#define DSISR_BAD_DIRECT_ST 0x80000000
313#define DSISR_NOHPTE 0x40000000
314#define DSISR_ATTR_CONFLICT 0x20000000
315#define DSISR_NOEXEC_OR_G 0x10000000
316#define DSISR_PROTFAULT 0x08000000
317#define DSISR_BADACCESS 0x04000000
318#define DSISR_ISSTORE 0x02000000
319#define DSISR_DABRMATCH 0x00400000
320#define DSISR_NOSEGMENT 0x00200000
321#define DSISR_KEYFAULT 0x00200000
322#define DSISR_BAD_EXT_CTRL 0x00100000
323#define DSISR_UNSUPP_MMU 0x00080000
324#define DSISR_SET_RC 0x00040000
325#define DSISR_PRTABLE_FAULT 0x00020000
326#define DSISR_ICSWX_NO_CT 0x00004000
327#define DSISR_BAD_COPYPASTE 0x00000008
328#define DSISR_BAD_AMO 0x00000004
329#define DSISR_BAD_CI_LDST 0x00000002
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345
346#define DSISR_BAD_FAULT_32S (DSISR_BAD_DIRECT_ST | \
347 DSISR_BADACCESS | \
348 DSISR_BAD_EXT_CTRL)
349#define DSISR_BAD_FAULT_64S (DSISR_BAD_FAULT_32S | \
350 DSISR_ATTR_CONFLICT | \
351 DSISR_UNSUPP_MMU | \
352 DSISR_PRTABLE_FAULT | \
353 DSISR_ICSWX_NO_CT | \
354 DSISR_BAD_COPYPASTE | \
355 DSISR_BAD_AMO | \
356 DSISR_BAD_CI_LDST)
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360
361#define DSISR_SRR1_MATCH_32S (DSISR_NOHPTE | \
362 DSISR_NOEXEC_OR_G | \
363 DSISR_PROTFAULT)
364#define DSISR_SRR1_MATCH_64S (DSISR_SRR1_MATCH_32S | \
365 DSISR_KEYFAULT | \
366 DSISR_UNSUPP_MMU | \
367 DSISR_SET_RC | \
368 DSISR_PRTABLE_FAULT)
369
370#define SPRN_TBRL 0x10C
371#define SPRN_TBRU 0x10D
372#define SPRN_CIR 0x11B
373#define SPRN_TBWL 0x11C
374#define SPRN_TBWU 0x11D
375#define SPRN_TBU40 0x11E
376#define SPRN_SPURR 0x134
377#define SPRN_HSPRG0 0x130
378#define SPRN_HSPRG1 0x131
379#define SPRN_HDSISR 0x132
380#define SPRN_HDAR 0x133
381#define SPRN_HDEC 0x136
382#define SPRN_HIOR 0x137
383#define SPRN_RMOR 0x138
384#define SPRN_HRMOR 0x139
385#define SPRN_HSRR0 0x13A
386#define SPRN_HSRR1 0x13B
387#define SPRN_ASDR 0x330
388#define SPRN_IC 0x350
389#define SPRN_VTB 0x351
390#define SPRN_LDBAR 0x352
391#define SPRN_PMICR 0x354
392#define SPRN_PMSR 0x355
393#define SPRN_PMMAR 0x356
394#define SPRN_PSSCR 0x357
395#define SPRN_PSSCR_PR 0x337
396#define SPRN_TRIG2 0x372
397#define SPRN_PMCR 0x374
398#define SPRN_RWMR 0x375
399
400
401#define FSCR_PREFIX_LG 13
402#define FSCR_SCV_LG 12
403#define FSCR_MSGP_LG 10
404#define FSCR_TAR_LG 8
405#define FSCR_EBB_LG 7
406#define FSCR_TM_LG 5
407#define FSCR_BHRB_LG 4
408#define FSCR_PM_LG 3
409#define FSCR_DSCR_LG 2
410#define FSCR_VECVSX_LG 1
411#define FSCR_FP_LG 0
412#define SPRN_FSCR 0x099
413#define FSCR_PREFIX __MASK(FSCR_PREFIX_LG)
414#define FSCR_SCV __MASK(FSCR_SCV_LG)
415#define FSCR_TAR __MASK(FSCR_TAR_LG)
416#define FSCR_EBB __MASK(FSCR_EBB_LG)
417#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
418#define SPRN_HFSCR 0xbe
419#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
420#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
421#define HFSCR_TAR __MASK(FSCR_TAR_LG)
422#define HFSCR_EBB __MASK(FSCR_EBB_LG)
423#define HFSCR_TM __MASK(FSCR_TM_LG)
424#define HFSCR_PM __MASK(FSCR_PM_LG)
425#define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
426#define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
427#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
428#define HFSCR_FP __MASK(FSCR_FP_LG)
429#define HFSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56)
430#define SPRN_TAR 0x32f
431#define SPRN_LPCR 0x13E
432#define LPCR_VPM0 ASM_CONST(0x8000000000000000)
433#define LPCR_VPM1 ASM_CONST(0x4000000000000000)
434#define LPCR_ISL ASM_CONST(0x2000000000000000)
435#define LPCR_VC_SH 61
436#define LPCR_DPFD_SH 52
437#define LPCR_DPFD (ASM_CONST(7) << LPCR_DPFD_SH)
438#define LPCR_VRMASD_SH 47
439#define LPCR_VRMASD (ASM_CONST(0x1f) << LPCR_VRMASD_SH)
440#define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
441#define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
442#define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
443#define LPCR_RMLS 0x1C000000
444#define LPCR_RMLS_SH 26
445#define LPCR_HAIL ASM_CONST(0x0000000004000000)
446#define LPCR_ILE ASM_CONST(0x0000000002000000)
447#define LPCR_AIL ASM_CONST(0x0000000001800000)
448#define LPCR_AIL_0 ASM_CONST(0x0000000000000000)
449#define LPCR_AIL_3 ASM_CONST(0x0000000001800000)
450#define LPCR_ONL ASM_CONST(0x0000000000040000)
451#define LPCR_LD ASM_CONST(0x0000000000020000)
452#define LPCR_PECE ASM_CONST(0x000000000001f000)
453#define LPCR_PECEDP ASM_CONST(0x0000000000010000)
454#define LPCR_PECEDH ASM_CONST(0x0000000000008000)
455#define LPCR_PECE0 ASM_CONST(0x0000000000004000)
456#define LPCR_PECE1 ASM_CONST(0x0000000000002000)
457#define LPCR_PECE2 ASM_CONST(0x0000000000001000)
458#define LPCR_PECE_HVEE ASM_CONST(0x0000400000000000)
459#define LPCR_MER ASM_CONST(0x0000000000000800)
460#define LPCR_MER_SH 11
461#define LPCR_GTSE ASM_CONST(0x0000000000000400)
462#define LPCR_TC ASM_CONST(0x0000000000000200)
463#define LPCR_HEIC ASM_CONST(0x0000000000000010)
464#define LPCR_LPES 0x0000000c
465#define LPCR_LPES0 ASM_CONST(0x0000000000000008)
466#define LPCR_LPES1 ASM_CONST(0x0000000000000004)
467#define LPCR_LPES_SH 2
468#define LPCR_RMI ASM_CONST(0x0000000000000002)
469#define LPCR_HVICE ASM_CONST(0x0000000000000002)
470#define LPCR_HDICE ASM_CONST(0x0000000000000001)
471#define LPCR_UPRT ASM_CONST(0x0000000000400000)
472#define LPCR_HR ASM_CONST(0x0000000000100000)
473#ifndef SPRN_LPID
474#define SPRN_LPID 0x13F
475#endif
476#define LPID_RSVD_POWER7 0x3ff
477#define LPID_RSVD 0xfff
478#define SPRN_HMER 0x150
479#define HMER_DEBUG_TRIG (1ul << (63 - 17))
480#define SPRN_HMEER 0x151
481#define SPRN_PCR 0x152
482#define PCR_VEC_DIS (__MASK(63-0))
483#define PCR_VSX_DIS (__MASK(63-1))
484#define PCR_TM_DIS (__MASK(63-2))
485#define PCR_MMA_DIS (__MASK(63-3))
486#define PCR_HIGH_BITS (PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
487
488
489
490
491
492#define PCR_ARCH_300 0x10
493#define PCR_ARCH_207 0x8
494#define PCR_ARCH_206 0x4
495#define PCR_ARCH_205 0x2
496#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 | PCR_ARCH_300)
497#define PCR_MASK ~(PCR_HIGH_BITS | PCR_LOW_BITS)
498#define SPRN_HEIR 0x153
499#define SPRN_TLBINDEXR 0x154
500#define SPRN_TLBVPNR 0x155
501#define SPRN_TLBRPNR 0x156
502#define SPRN_TLBLPIDR 0x157
503#define SPRN_DBAT0L 0x219
504#define SPRN_DBAT0U 0x218
505#define SPRN_DBAT1L 0x21B
506#define SPRN_DBAT1U 0x21A
507#define SPRN_DBAT2L 0x21D
508#define SPRN_DBAT2U 0x21C
509#define SPRN_DBAT3L 0x21F
510#define SPRN_DBAT3U 0x21E
511#define SPRN_DBAT4L 0x239
512#define SPRN_DBAT4U 0x238
513#define SPRN_DBAT5L 0x23B
514#define SPRN_DBAT5U 0x23A
515#define SPRN_DBAT6L 0x23D
516#define SPRN_DBAT6U 0x23C
517#define SPRN_DBAT7L 0x23F
518#define SPRN_DBAT7U 0x23E
519#define SPRN_PPR 0x380
520#define SPRN_TSCR 0x399
521
522#define SPRN_DEC 0x016
523#define SPRN_PIT 0x3DB
524
525#define SPRN_DER 0x095
526#define DER_RSTE 0x40000000
527#define DER_CHSTPE 0x20000000
528#define DER_MCIE 0x10000000
529#define DER_EXTIE 0x02000000
530#define DER_ALIE 0x01000000
531#define DER_PRIE 0x00800000
532#define DER_FPUVIE 0x00400000
533#define DER_DECIE 0x00200000
534#define DER_SYSIE 0x00040000
535#define DER_TRE 0x00020000
536#define DER_SEIE 0x00004000
537#define DER_ITLBMSE 0x00002000
538#define DER_ITLBERE 0x00001000
539#define DER_DTLBMSE 0x00000800
540#define DER_DTLBERE 0x00000400
541#define DER_LBRKE 0x00000008
542#define DER_IBRKE 0x00000004
543#define DER_EBRKE 0x00000002
544#define DER_DPIE 0x00000001
545#define SPRN_DMISS 0x3D0
546#define SPRN_DHDES 0x0B1
547#define SPRN_DPDES 0x0B0
548#define SPRN_EAR 0x11A
549#define SPRN_HASH1 0x3D2
550#define SPRN_HASH2 0x3D3
551#define SPRN_HID0 0x3F0
552#define HID0_HDICE_SH (63 - 23)
553#define HID0_EMCP (1<<31)
554#define HID0_EBA (1<<29)
555#define HID0_EBD (1<<28)
556#define HID0_SBCLK (1<<27)
557#define HID0_EICE (1<<26)
558#define HID0_TBEN (1<<26)
559#define HID0_ECLK (1<<25)
560#define HID0_PAR (1<<24)
561#define HID0_STEN (1<<24)
562#define HID0_HIGH_BAT (1<<23)
563#define HID0_DOZE (1<<23)
564#define HID0_NAP (1<<22)
565#define HID0_SLEEP (1<<21)
566#define HID0_DPM (1<<20)
567#define HID0_BHTCLR (1<<18)
568#define HID0_XAEN (1<<17)
569#define HID0_NHR (1<<16)
570#define HID0_ICE (1<<15)
571#define HID0_DCE (1<<14)
572#define HID0_ILOCK (1<<13)
573#define HID0_DLOCK (1<<12)
574#define HID0_ICFI (1<<11)
575#define HID0_DCI (1<<10)
576#define HID0_SPD (1<<9)
577#define HID0_DAPUEN (1<<8)
578#define HID0_SGE (1<<7)
579#define HID0_SIED (1<<7)
580#define HID0_DCFA (1<<6)
581#define HID0_LRSTK (1<<4)
582#define HID0_BTIC (1<<5)
583#define HID0_ABE (1<<3)
584#define HID0_FOLD (1<<3)
585#define HID0_BHTE (1<<2)
586#define HID0_BTCD (1<<1)
587#define HID0_NOPDST (1<<1)
588#define HID0_NOPTI (1<<0)
589
590#define HID0_POWER8_4LPARMODE __MASK(61)
591#define HID0_POWER8_2LPARMODE __MASK(57)
592#define HID0_POWER8_1TO2LPAR __MASK(52)
593#define HID0_POWER8_1TO4LPAR __MASK(51)
594#define HID0_POWER8_DYNLPARDIS __MASK(48)
595
596
597#define HID0_POWER9_RADIX __MASK(63 - 8)
598
599#define SPRN_HID1 0x3F1
600#ifdef CONFIG_PPC_BOOK3S_32
601#define HID1_EMCP (1<<31)
602#define HID1_DFS (1<<22)
603#define HID1_PC0 (1<<16)
604#define HID1_PC1 (1<<15)
605#define HID1_PC2 (1<<14)
606#define HID1_PC3 (1<<13)
607#define HID1_SYNCBE (1<<11)
608#define HID1_ABE (1<<10)
609#define HID1_PS (1<<16)
610#endif
611#define SPRN_HID2 0x3F8
612#define SPRN_HID2_GEKKO 0x398
613#define SPRN_IABR 0x3F2
614#define SPRN_IABR2 0x3FA
615#define SPRN_IBCR 0x135
616#define SPRN_IAMR 0x03D
617#define SPRN_HID4 0x3F4
618#define HID4_LPES0 (1ul << (63-0))
619#define HID4_RMLS2_SH (63 - 2)
620#define HID4_LPID5_SH (63 - 6)
621#define HID4_RMOR_SH (63 - 22)
622#define HID4_RMOR (0xFFFFul << HID4_RMOR_SH)
623#define HID4_LPES1 (1 << (63-57))
624#define HID4_RMLS0_SH (63 - 58)
625#define HID4_LPID1_SH 0
626#define SPRN_HID4_GEKKO 0x3F3
627#define SPRN_HID5 0x3F6
628#define SPRN_HID6 0x3F9
629#define HID6_LB (0x0F<<12)
630#define HID6_DLP (1<<20)
631#define SPRN_TSC_CELL 0x399
632#define TSC_CELL_DEC_ENABLE_0 0x400000
633#define TSC_CELL_DEC_ENABLE_1 0x200000
634#define TSC_CELL_EE_ENABLE 0x100000
635#define TSC_CELL_EE_BOOST 0x080000
636#define SPRN_TSC 0x3FD
637#define SPRN_TST 0x3FC
638#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
639#define SPRN_IAC1 0x3F4
640#define SPRN_IAC2 0x3F5
641#endif
642#define SPRN_IBAT0L 0x211
643#define SPRN_IBAT0U 0x210
644#define SPRN_IBAT1L 0x213
645#define SPRN_IBAT1U 0x212
646#define SPRN_IBAT2L 0x215
647#define SPRN_IBAT2U 0x214
648#define SPRN_IBAT3L 0x217
649#define SPRN_IBAT3U 0x216
650#define SPRN_IBAT4L 0x231
651#define SPRN_IBAT4U 0x230
652#define SPRN_IBAT5L 0x233
653#define SPRN_IBAT5U 0x232
654#define SPRN_IBAT6L 0x235
655#define SPRN_IBAT6U 0x234
656#define SPRN_IBAT7L 0x237
657#define SPRN_IBAT7U 0x236
658#define SPRN_ICMP 0x3D5
659#define SPRN_ICTC 0x3FB
660#ifndef SPRN_ICTRL
661#define SPRN_ICTRL 0x3F3
662#endif
663#define ICTRL_EICE 0x08000000
664#define ICTRL_EDC 0x04000000
665#define ICTRL_EICP 0x00000100
666#define SPRN_IMISS 0x3D4
667#define SPRN_IMMR 0x27E
668#define SPRN_L2CR 0x3F9
669#define SPRN_L2CR2 0x3f8
670#define L2CR_L2E 0x80000000
671#define L2CR_L2PE 0x40000000
672#define L2CR_L2SIZ_MASK 0x30000000
673#define L2CR_L2SIZ_256KB 0x10000000
674#define L2CR_L2SIZ_512KB 0x20000000
675#define L2CR_L2SIZ_1MB 0x30000000
676#define L2CR_L2CLK_MASK 0x0e000000
677#define L2CR_L2CLK_DISABLED 0x00000000
678#define L2CR_L2CLK_DIV1 0x02000000
679#define L2CR_L2CLK_DIV1_5 0x04000000
680#define L2CR_L2CLK_DIV2 0x08000000
681#define L2CR_L2CLK_DIV2_5 0x0a000000
682#define L2CR_L2CLK_DIV3 0x0c000000
683#define L2CR_L2RAM_MASK 0x01800000
684#define L2CR_L2RAM_FLOW 0x00000000
685#define L2CR_L2RAM_PIPE 0x01000000
686#define L2CR_L2RAM_PIPE_LW 0x01800000
687#define L2CR_L2DO 0x00400000
688#define L2CR_L2I 0x00200000
689#define L2CR_L2CTL 0x00100000
690#define L2CR_L2WT 0x00080000
691#define L2CR_L2TS 0x00040000
692#define L2CR_L2OH_MASK 0x00030000
693#define L2CR_L2OH_0_5 0x00000000
694#define L2CR_L2OH_1_0 0x00010000
695#define L2CR_L2SL 0x00008000
696#define L2CR_L2DF 0x00004000
697#define L2CR_L2BYP 0x00002000
698#define L2CR_L2IP 0x00000001
699#define L2CR_L2IO_745x 0x00100000
700#define L2CR_L2DO_745x 0x00010000
701#define L2CR_L2REP_745x 0x00001000
702#define L2CR_L2HWF_745x 0x00000800
703#define SPRN_L3CR 0x3FA
704#define L3CR_L3E 0x80000000
705#define L3CR_L3PE 0x40000000
706#define L3CR_L3APE 0x20000000
707#define L3CR_L3SIZ 0x10000000
708#define L3CR_L3CLKEN 0x08000000
709#define L3CR_L3RES 0x04000000
710#define L3CR_L3CLKDIV 0x03800000
711#define L3CR_L3IO 0x00400000
712#define L3CR_L3SPO 0x00040000
713#define L3CR_L3CKSP 0x00030000
714#define L3CR_L3PSP 0x0000e000
715#define L3CR_L3REP 0x00001000
716#define L3CR_L3HWF 0x00000800
717#define L3CR_L3I 0x00000400
718#define L3CR_L3RT 0x00000300
719#define L3CR_L3NIRCA 0x00000080
720#define L3CR_L3DO 0x00000040
721#define L3CR_PMEN 0x00000004
722#define L3CR_PMSIZ 0x00000001
723
724#define SPRN_MSSCR0 0x3f6
725#define SPRN_MSSSR0 0x3f7
726#define SPRN_LDSTCR 0x3f8
727#define SPRN_LDSTDB 0x3f4
728#define SPRN_LR 0x008
729#ifndef SPRN_PIR
730#define SPRN_PIR 0x3FF
731#endif
732#define SPRN_TIR 0x1BE
733#define SPRN_PTCR 0x1D0
734#define SPRN_PSPB 0x09F
735#define SPRN_PTEHI 0x3D5
736#define SPRN_PTELO 0x3D6
737#define SPRN_PURR 0x135
738#define SPRN_PVR 0x11F
739#define SPRN_RPA 0x3D6
740#define SPRN_SDA 0x3BF
741#define SPRN_SDR1 0x019
742#define SPRN_ASR 0x118
743#define SPRN_SIA 0x3BB
744#define SPRN_SPRG0 0x110
745#define SPRN_SPRG1 0x111
746#define SPRN_SPRG2 0x112
747#define SPRN_SPRG3 0x113
748#define SPRN_USPRG3 0x103
749#define SPRN_SPRG4 0x114
750#define SPRN_USPRG4 0x104
751#define SPRN_SPRG5 0x115
752#define SPRN_USPRG5 0x105
753#define SPRN_SPRG6 0x116
754#define SPRN_USPRG6 0x106
755#define SPRN_SPRG7 0x117
756#define SPRN_USPRG7 0x107
757#define SPRN_SRR0 0x01A
758#define SPRN_SRR1 0x01B
759
760#ifdef CONFIG_PPC_BOOK3S
761
762
763
764
765
766
767
768#define SRR1_MSR_BITS (~0x783f0000UL)
769#endif
770
771#define SRR1_ISI_NOPT 0x40000000
772#define SRR1_ISI_N_G_OR_CIP 0x10000000
773#define SRR1_ISI_PROT 0x08000000
774#define SRR1_WAKEMASK 0x00380000
775#define SRR1_WAKEMASK_P8 0x003c0000
776#define SRR1_WAKEMCE_RESVD 0x003c0000
777#define SRR1_WAKESYSERR 0x00300000
778#define SRR1_WAKEEE 0x00200000
779#define SRR1_WAKEHVI 0x00240000
780#define SRR1_WAKEMT 0x00280000
781#define SRR1_WAKEHMI 0x00280000
782#define SRR1_WAKEDEC 0x00180000
783#define SRR1_WAKEDBELL 0x00140000
784#define SRR1_WAKETHERM 0x00100000
785#define SRR1_WAKERESET 0x00100000
786#define SRR1_WAKEHDBELL 0x000c0000
787#define SRR1_WAKESTATE 0x00030000
788#define SRR1_WS_HVLOSS 0x00030000
789#define SRR1_WS_GPRLOSS 0x00020000
790#define SRR1_WS_NOLOSS 0x00010000
791#define SRR1_PROGTM 0x00200000
792#define SRR1_PROGFPE 0x00100000
793#define SRR1_PROGILL 0x00080000
794#define SRR1_PROGPRIV 0x00040000
795#define SRR1_PROGTRAP 0x00020000
796#define SRR1_PROGADDR 0x00010000
797
798#define SRR1_MCE_MCP 0x00080000
799#define SRR1_BOUNDARY 0x10000000
800#define SRR1_PREFIXED 0x20000000
801
802#define SPRN_HSRR0 0x13A
803#define SPRN_HSRR1 0x13B
804#define HSRR1_DENORM 0x00100000
805#define HSRR1_HISI_WRITE 0x00010000
806
807#define SPRN_TBCTL 0x35f
808#define TBCTL_FREEZE 0x0000000000000000ull
809#define TBCTL_RESTART 0x0000000100000000ull
810#define TBCTL_UPDATE_UPPER 0x0000000200000000ull
811#define TBCTL_UPDATE_LOWER 0x0000000300000000ull
812
813#ifndef SPRN_SVR
814#define SPRN_SVR 0x11E
815#endif
816#define SPRN_THRM1 0x3FC
817
818#define THRM1_TIN (1 << 31)
819#define THRM1_TIV (1 << 30)
820#define THRM1_THRES(x) ((x&0x7f)<<23)
821#define THRM3_SITV(x) ((x & 0x1fff) << 1)
822#define THRM1_TID (1<<2)
823#define THRM1_TIE (1<<1)
824#define THRM1_V (1<<0)
825#define SPRN_THRM2 0x3FD
826#define SPRN_THRM3 0x3FE
827#define THRM3_E (1<<0)
828#define SPRN_TLBMISS 0x3D4
829#define SPRN_UMMCR0 0x3A8
830#define SPRN_UMMCR1 0x3AC
831#define SPRN_UPMC1 0x3A9
832#define SPRN_UPMC2 0x3AA
833#define SPRN_UPMC3 0x3AD
834#define SPRN_UPMC4 0x3AE
835#define SPRN_USIA 0x3AB
836#define SPRN_VRSAVE 0x100
837#define SPRN_XER 0x001
838
839#define SPRN_MMCR0_GEKKO 0x3B8
840#define SPRN_MMCR1_GEKKO 0x3BC
841#define SPRN_PMC1_GEKKO 0x3B9
842#define SPRN_PMC2_GEKKO 0x3BA
843#define SPRN_PMC3_GEKKO 0x3BD
844#define SPRN_PMC4_GEKKO 0x3BE
845#define SPRN_WPAR_GEKKO 0x399
846
847#define SPRN_SCOMC 0x114
848#define SPRN_SCOMD 0x115
849
850
851#ifdef CONFIG_PPC64
852#define SPRN_MMCR0 795
853#define MMCR0_FC 0x80000000UL
854#define MMCR0_FCS 0x40000000UL
855#define MMCR0_KERNEL_DISABLE MMCR0_FCS
856#define MMCR0_FCP 0x20000000UL
857#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
858#define MMCR0_FCM1 0x10000000UL
859#define MMCR0_FCM0 0x08000000UL
860#define MMCR0_PMXE ASM_CONST(0x04000000)
861#define MMCR0_FCECE ASM_CONST(0x02000000)
862#define MMCR0_TBEE 0x00400000UL
863#define MMCR0_BHRBA 0x00200000UL
864#define MMCR0_EBE 0x00100000UL
865#define MMCR0_PMCC 0x000c0000UL
866#define MMCR0_PMCCEXT ASM_CONST(0x00000200)
867#define MMCR0_PMCC_U6 0x00080000UL
868#define MMCR0_PMC1CE 0x00008000UL
869#define MMCR0_PMCjCE ASM_CONST(0x00004000)
870#define MMCR0_TRIGGER 0x00002000UL
871#define MMCR0_PMAO_SYNC ASM_CONST(0x00000800)
872#define MMCR0_C56RUN ASM_CONST(0x00000100)
873
874#define MMCR0_PMAO ASM_CONST(0x00000080)
875#define MMCR0_SHRFC 0x00000040UL
876#define MMCR0_FC56 0x00000010UL
877#define MMCR0_FCTI 0x00000008UL
878#define MMCR0_FCTA 0x00000004UL
879#define MMCR0_FCWAIT 0x00000002UL
880#define MMCR0_FCHV 0x00000001UL
881#define SPRN_MMCR1 798
882#define SPRN_MMCR2 785
883#define SPRN_MMCR3 754
884#define SPRN_UMMCR2 769
885#define SPRN_UMMCR3 738
886#define SPRN_MMCRA 0x312
887#define MMCRA_SDSYNC 0x80000000UL
888#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
889#define MMCRA_SDAR_ERAT_MISS 0x20000000UL
890#define MMCRA_SIHV 0x10000000UL
891#define MMCRA_SIPR 0x08000000UL
892#define MMCRA_SLOT 0x07000000UL
893#define MMCRA_SLOT_SHIFT 24
894#define MMCRA_SAMPLE_ENABLE 0x00000001UL
895#define MMCRA_BHRB_DISABLE _UL(0x2000000000)
896#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL
897#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
898#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
899#define POWER6_MMCRA_THRM 0x00000020UL
900#define POWER6_MMCRA_OTHER 0x0000000EUL
901
902#define POWER7P_MMCRA_SIAR_VALID 0x10000000
903#define POWER7P_MMCRA_SDAR_VALID 0x08000000
904
905#define SPRN_MMCRH 316
906#define SPRN_MMCRS 894
907#define SPRN_MMCRC 851
908#define SPRN_EBBHR 804
909#define SPRN_EBBRR 805
910#define SPRN_BESCR 806
911#define BESCR_GE 0x8000000000000000ULL
912#define SPRN_WORT 895
913#define SPRN_WORC 863
914
915#define SPRN_PMC1 787
916#define SPRN_PMC2 788
917#define SPRN_PMC3 789
918#define SPRN_PMC4 790
919#define SPRN_PMC5 791
920#define SPRN_PMC6 792
921#define SPRN_PMC7 793
922#define SPRN_PMC8 794
923#define SPRN_SIER 784
924#define SIER_SIPR 0x2000000
925#define SIER_SIHV 0x1000000
926#define SIER_SIAR_VALID 0x0400000
927#define SIER_SDAR_VALID 0x0200000
928#define SPRN_SIER2 752
929#define SPRN_SIER3 753
930#define SPRN_USIER2 736
931#define SPRN_USIER3 737
932#define SPRN_SIAR 796
933#define SPRN_SDAR 797
934#define SPRN_TACR 888
935#define SPRN_TCSCR 889
936#define SPRN_CSIGR 890
937#define SPRN_SPMC1 892
938#define SPRN_SPMC2 893
939
940
941#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
942#define MMCR2_USER_MASK 0x4020100804020000UL
943#define SIER_USER_MASK 0x7fffffUL
944
945#define SPRN_PA6T_MMCR0 795
946#define PA6T_MMCR0_EN0 0x0000000000000001UL
947#define PA6T_MMCR0_EN1 0x0000000000000002UL
948#define PA6T_MMCR0_EN2 0x0000000000000004UL
949#define PA6T_MMCR0_EN3 0x0000000000000008UL
950#define PA6T_MMCR0_EN4 0x0000000000000010UL
951#define PA6T_MMCR0_EN5 0x0000000000000020UL
952#define PA6T_MMCR0_SUPEN 0x0000000000000040UL
953#define PA6T_MMCR0_PREN 0x0000000000000080UL
954#define PA6T_MMCR0_HYPEN 0x0000000000000100UL
955#define PA6T_MMCR0_FCM0 0x0000000000000200UL
956#define PA6T_MMCR0_FCM1 0x0000000000000400UL
957#define PA6T_MMCR0_INTGEN 0x0000000000000800UL
958#define PA6T_MMCR0_INTEN0 0x0000000000001000UL
959#define PA6T_MMCR0_INTEN1 0x0000000000002000UL
960#define PA6T_MMCR0_INTEN2 0x0000000000004000UL
961#define PA6T_MMCR0_INTEN3 0x0000000000008000UL
962#define PA6T_MMCR0_INTEN4 0x0000000000010000UL
963#define PA6T_MMCR0_INTEN5 0x0000000000020000UL
964#define PA6T_MMCR0_DISCNT 0x0000000000040000UL
965#define PA6T_MMCR0_UOP 0x0000000000080000UL
966#define PA6T_MMCR0_TRG 0x0000000000100000UL
967#define PA6T_MMCR0_TRGEN 0x0000000000200000UL
968#define PA6T_MMCR0_TRGREG 0x0000000001600000UL
969#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
970#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
971#define PA6T_MMCR0_PROEN 0x0000000008000000UL
972#define PA6T_MMCR0_PROLOG 0x0000000010000000UL
973#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
974#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
975#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
976#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
977#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
978#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
979#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
980#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
981#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
982#define PA6T_MMCR0_PCTEN 0x0000004000000000UL
983#define PA6T_MMCR0_SOCEN 0x0000008000000000UL
984#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
985
986#define SPRN_PA6T_MMCR1 798
987#define PA6T_MMCR1_ES2 0x00000000000000ffUL
988#define PA6T_MMCR1_ES3 0x000000000000ff00UL
989#define PA6T_MMCR1_ES4 0x0000000000ff0000UL
990#define PA6T_MMCR1_ES5 0x00000000ff000000UL
991
992#define SPRN_PA6T_UPMC0 771
993#define SPRN_PA6T_UPMC1 772
994#define SPRN_PA6T_UPMC2 773
995#define SPRN_PA6T_UPMC3 774
996#define SPRN_PA6T_UPMC4 775
997#define SPRN_PA6T_UPMC5 776
998#define SPRN_PA6T_UMMCR0 779
999#define SPRN_PA6T_SIAR 780
1000#define SPRN_PA6T_UMMCR1 782
1001#define SPRN_PA6T_SIER 785
1002#define SPRN_PA6T_PMC0 787
1003#define SPRN_PA6T_PMC1 788
1004#define SPRN_PA6T_PMC2 789
1005#define SPRN_PA6T_PMC3 790
1006#define SPRN_PA6T_PMC4 791
1007#define SPRN_PA6T_PMC5 792
1008#define SPRN_PA6T_TSR0 793
1009#define SPRN_PA6T_TSR1 794
1010#define SPRN_PA6T_TSR2 799
1011#define SPRN_PA6T_TSR3 784
1012
1013#define SPRN_PA6T_IER 981
1014#define SPRN_PA6T_DER 982
1015#define SPRN_PA6T_BER 862
1016#define SPRN_PA6T_MER 849
1017
1018#define SPRN_PA6T_IMA0 880
1019#define SPRN_PA6T_IMA1 881
1020#define SPRN_PA6T_IMA2 882
1021#define SPRN_PA6T_IMA3 883
1022#define SPRN_PA6T_IMA4 884
1023#define SPRN_PA6T_IMA5 885
1024#define SPRN_PA6T_IMA6 886
1025#define SPRN_PA6T_IMA7 887
1026#define SPRN_PA6T_IMA8 888
1027#define SPRN_PA6T_IMA9 889
1028#define SPRN_PA6T_BTCR 978
1029#define SPRN_PA6T_IMAAT 979
1030#define SPRN_PA6T_PCCR 1019
1031#define SPRN_BKMK 1020
1032#define SPRN_PA6T_RPCCR 1021
1033
1034
1035#else
1036#define SPRN_MMCR0 952
1037#define MMCR0_FC 0x80000000UL
1038#define MMCR0_FCS 0x40000000UL
1039#define MMCR0_FCP 0x20000000UL
1040#define MMCR0_FCM1 0x10000000UL
1041#define MMCR0_FCM0 0x08000000UL
1042#define MMCR0_PMXE 0x04000000UL
1043#define MMCR0_FCECE 0x02000000UL
1044#define MMCR0_TBEE 0x00400000UL
1045#define MMCR0_PMC1CE 0x00008000UL
1046#define MMCR0_PMCnCE 0x00004000UL
1047#define MMCR0_TRIGGER 0x00002000UL
1048#define MMCR0_PMC1SEL 0x00001fc0UL
1049#define MMCR0_PMC2SEL 0x0000003fUL
1050
1051#define SPRN_MMCR1 956
1052#define MMCR1_PMC3SEL 0xf8000000UL
1053#define MMCR1_PMC4SEL 0x07c00000UL
1054#define MMCR1_PMC5SEL 0x003e0000UL
1055#define MMCR1_PMC6SEL 0x0001f800UL
1056#define SPRN_MMCR2 944
1057#define SPRN_PMC1 953
1058#define SPRN_PMC2 954
1059#define SPRN_PMC3 957
1060#define SPRN_PMC4 958
1061#define SPRN_PMC5 945
1062#define SPRN_PMC6 946
1063
1064#define SPRN_SIAR 955
1065
1066
1067#define MMCR0_PMC1_CYCLES (1 << 7)
1068#define MMCR0_PMC1_ICACHEMISS (5 << 7)
1069#define MMCR0_PMC1_DTLB (6 << 7)
1070#define MMCR0_PMC2_DCACHEMISS 0x6
1071#define MMCR0_PMC2_CYCLES 0x1
1072#define MMCR0_PMC2_ITLB 0x7
1073#define MMCR0_PMC2_LOADMISSTIME 0x5
1074#endif
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
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1140#ifdef CONFIG_PPC64
1141#define SPRN_SPRG_PACA SPRN_SPRG1
1142#else
1143#define SPRN_SPRG_THREAD SPRN_SPRG3
1144#endif
1145
1146#ifdef CONFIG_PPC_BOOK3S_64
1147#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
1148#define SPRN_SPRG_HPACA SPRN_HSPRG0
1149#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
1150#define SPRN_SPRG_VDSO_READ SPRN_USPRG3
1151#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3
1152
1153#define GET_PACA(rX) \
1154 BEGIN_FTR_SECTION_NESTED(66); \
1155 mfspr rX,SPRN_SPRG_PACA; \
1156 FTR_SECTION_ELSE_NESTED(66); \
1157 mfspr rX,SPRN_SPRG_HPACA; \
1158 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1159
1160#define SET_PACA(rX) \
1161 BEGIN_FTR_SECTION_NESTED(66); \
1162 mtspr SPRN_SPRG_PACA,rX; \
1163 FTR_SECTION_ELSE_NESTED(66); \
1164 mtspr SPRN_SPRG_HPACA,rX; \
1165 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1166
1167#define GET_SCRATCH0(rX) \
1168 BEGIN_FTR_SECTION_NESTED(66); \
1169 mfspr rX,SPRN_SPRG_SCRATCH0; \
1170 FTR_SECTION_ELSE_NESTED(66); \
1171 mfspr rX,SPRN_SPRG_HSCRATCH0; \
1172 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1173
1174#define SET_SCRATCH0(rX) \
1175 BEGIN_FTR_SECTION_NESTED(66); \
1176 mtspr SPRN_SPRG_SCRATCH0,rX; \
1177 FTR_SECTION_ELSE_NESTED(66); \
1178 mtspr SPRN_SPRG_HSCRATCH0,rX; \
1179 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1180
1181#else
1182#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0
1183#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX
1184
1185#endif
1186
1187#ifdef CONFIG_PPC_BOOK3E_64
1188#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8
1189#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3
1190#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9
1191#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
1192#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
1193#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
1194#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
1195#define SPRN_SPRG_VDSO_READ SPRN_USPRG7
1196#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7
1197
1198#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
1199#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
1200
1201#endif
1202
1203#ifdef CONFIG_PPC_BOOK3S_32
1204#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1205#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1206#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1207#define SPRN_SPRG_603_LRU SPRN_SPRG4
1208#endif
1209
1210#ifdef CONFIG_40x
1211#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1212#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1213#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1214#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
1215#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
1216#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
1217#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
1218#endif
1219
1220#ifdef CONFIG_BOOKE
1221#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
1222#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
1223#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
1224#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
1225#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
1226#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
1227#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
1228#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
1229#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
1230#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
1231#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
1232#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
1233#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
1234#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
1235#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
1236#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
1237#endif
1238
1239#ifdef CONFIG_PPC_8xx
1240#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1241#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1242#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1243#endif
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253#ifdef CONFIG_PPC64
1254#define MTFSF_L(REG) \
1255 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1256#else
1257#define MTFSF_L(REG) mtfsf 0xff, (REG)
1258#endif
1259
1260
1261
1262#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF)
1263#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF)
1264
1265#define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr))
1266
1267
1268
1269
1270
1271
1272#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF)
1273#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF)
1274#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF)
1275#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF)
1276#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF)
1277#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF)
1278
1279
1280
1281#define PVR_403GA 0x00200000
1282#define PVR_403GB 0x00200100
1283#define PVR_403GC 0x00200200
1284#define PVR_403GCX 0x00201400
1285#define PVR_405GP 0x40110000
1286#define PVR_476 0x11a52000
1287#define PVR_476FPE 0x7ff50000
1288#define PVR_STB03XXX 0x40310000
1289#define PVR_NP405H 0x41410000
1290#define PVR_NP405L 0x41610000
1291#define PVR_601 0x00010000
1292#define PVR_602 0x00050000
1293#define PVR_603 0x00030000
1294#define PVR_603e 0x00060000
1295#define PVR_603ev 0x00070000
1296#define PVR_603r 0x00071000
1297#define PVR_604 0x00040000
1298#define PVR_604e 0x00090000
1299#define PVR_604r 0x000A0000
1300#define PVR_620 0x00140000
1301#define PVR_740 0x00080000
1302#define PVR_750 PVR_740
1303#define PVR_740P 0x10080000
1304#define PVR_750P PVR_740P
1305#define PVR_7400 0x000C0000
1306#define PVR_7410 0x800C0000
1307#define PVR_7450 0x80000000
1308#define PVR_8540 0x80200000
1309#define PVR_8560 0x80200000
1310#define PVR_VER_E500V1 0x8020
1311#define PVR_VER_E500V2 0x8021
1312#define PVR_VER_E500MC 0x8023
1313#define PVR_VER_E5500 0x8024
1314#define PVR_VER_E6500 0x8040
1315
1316
1317
1318
1319
1320
1321
1322#define PVR_8xx 0x00500000
1323
1324#define PVR_8240 0x00810100
1325#define PVR_8245 0x80811014
1326#define PVR_8260 PVR_8240
1327
1328
1329#define PVR_476_ISS 0x00052000
1330
1331
1332#define PVR_NORTHSTAR 0x0033
1333#define PVR_PULSAR 0x0034
1334#define PVR_POWER4 0x0035
1335#define PVR_ICESTAR 0x0036
1336#define PVR_SSTAR 0x0037
1337#define PVR_POWER4p 0x0038
1338#define PVR_970 0x0039
1339#define PVR_POWER5 0x003A
1340#define PVR_POWER5p 0x003B
1341#define PVR_970FX 0x003C
1342#define PVR_POWER6 0x003E
1343#define PVR_POWER7 0x003F
1344#define PVR_630 0x0040
1345#define PVR_630p 0x0041
1346#define PVR_970MP 0x0044
1347#define PVR_970GX 0x0045
1348#define PVR_POWER7p 0x004A
1349#define PVR_POWER8E 0x004B
1350#define PVR_POWER8NVL 0x004C
1351#define PVR_POWER8 0x004D
1352#define PVR_POWER9 0x004E
1353#define PVR_POWER10 0x0080
1354#define PVR_BE 0x0070
1355#define PVR_PA6T 0x0090
1356
1357
1358#define PVR_ARCH_204 0x0f000001
1359#define PVR_ARCH_205 0x0f000002
1360#define PVR_ARCH_206 0x0f000003
1361#define PVR_ARCH_206p 0x0f100003
1362#define PVR_ARCH_207 0x0f000004
1363#define PVR_ARCH_300 0x0f000005
1364#define PVR_ARCH_31 0x0f000006
1365
1366
1367#ifndef __ASSEMBLY__
1368#define mfmsr() ({unsigned long rval; \
1369 asm volatile("mfmsr %0" : "=r" (rval) : \
1370 : "memory"); rval;})
1371#ifdef CONFIG_PPC_BOOK3S_64
1372#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
1373 : : "r" (v) : "memory")
1374#define mtmsr(v) __mtmsrd((v), 0)
1375#define __MTMSR "mtmsrd"
1376#else
1377#define mtmsr(v) asm volatile("mtmsr %0" : \
1378 : "r" ((unsigned long)(v)) \
1379 : "memory")
1380#define __mtmsrd(v, l) BUILD_BUG()
1381#define __MTMSR "mtmsr"
1382#endif
1383
1384static inline void mtmsr_isync(unsigned long val)
1385{
1386 asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : :
1387 "r" (val), "i" (CPU_FTR_ARCH_206) : "memory");
1388}
1389
1390#define mfspr(rn) ({unsigned long rval; \
1391 asm volatile("mfspr %0," __stringify(rn) \
1392 : "=r" (rval)); rval;})
1393#ifndef mtspr
1394#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
1395 : "r" ((unsigned long)(v)) \
1396 : "memory")
1397#endif
1398#define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",2" : : : "memory")
1399
1400static inline void wrtee(unsigned long val)
1401{
1402 if (__builtin_constant_p(val))
1403 asm volatile("wrteei %0" : : "i" ((val & MSR_EE) ? 1 : 0) : "memory");
1404 else
1405 asm volatile("wrtee %0" : : "r" (val) : "memory");
1406}
1407
1408extern unsigned long msr_check_and_set(unsigned long bits);
1409extern bool strict_msr_control;
1410extern void __msr_check_and_clear(unsigned long bits);
1411static inline void msr_check_and_clear(unsigned long bits)
1412{
1413 if (strict_msr_control)
1414 __msr_check_and_clear(bits);
1415}
1416
1417#ifdef CONFIG_PPC32
1418static inline u32 mfsr(u32 idx)
1419{
1420 u32 val;
1421
1422 if (__builtin_constant_p(idx))
1423 asm volatile("mfsr %0, %1" : "=r" (val): "i" (idx >> 28));
1424 else
1425 asm volatile("mfsrin %0, %1" : "=r" (val): "r" (idx));
1426
1427 return val;
1428}
1429
1430static inline void mtsr(u32 val, u32 idx)
1431{
1432 if (__builtin_constant_p(idx))
1433 asm volatile("mtsr %1, %0" : : "r" (val), "i" (idx >> 28));
1434 else
1435 asm volatile("mtsrin %0, %1" : : "r" (val), "r" (idx));
1436}
1437#endif
1438
1439extern unsigned long current_stack_frame(void);
1440
1441register unsigned long current_stack_pointer asm("r1");
1442
1443extern unsigned long scom970_read(unsigned int address);
1444extern void scom970_write(unsigned int address, unsigned long value);
1445
1446struct pt_regs;
1447
1448extern void ppc_save_regs(struct pt_regs *regs);
1449#endif
1450#endif
1451#endif
1452