LXR linux/arch/s390/include/asm/processor.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 *  S390 version
   4 *    Copyright IBM Corp. 1999
   5 *    Author(s): Hartmut Penner (hp@de.ibm.com),
   6 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   7 *
   8 *  Derived from "include/asm-i386/processor.h"
   9 *    Copyright (C) 1994, Linus Torvalds
  10 */
  11
  12#ifndef __ASM_S390_PROCESSOR_H
  13#define __ASM_S390_PROCESSOR_H
  14
  15#include <linux/bits.h>
  16
  17#define CIF_NOHZ_DELAY          2       /* delay HZ disable for a tick */
  18#define CIF_FPU                 3       /* restore FPU registers */
  19#define CIF_ENABLED_WAIT        5       /* in enabled wait state */
  20#define CIF_MCCK_GUEST          6       /* machine check happening in guest */
  21#define CIF_DEDICATED_CPU       7       /* this CPU is dedicated */
  22
  23#define _CIF_NOHZ_DELAY         BIT(CIF_NOHZ_DELAY)
  24#define _CIF_FPU                BIT(CIF_FPU)
  25#define _CIF_ENABLED_WAIT       BIT(CIF_ENABLED_WAIT)
  26#define _CIF_MCCK_GUEST         BIT(CIF_MCCK_GUEST)
  27#define _CIF_DEDICATED_CPU      BIT(CIF_DEDICATED_CPU)
  28
  29#ifndef __ASSEMBLY__
  30
  31#include <linux/cpumask.h>
  32#include <linux/linkage.h>
  33#include <linux/irqflags.h>
  34#include <asm/cpu.h>
  35#include <asm/page.h>
  36#include <asm/ptrace.h>
  37#include <asm/setup.h>
  38#include <asm/runtime_instr.h>
  39#include <asm/fpu/types.h>
  40#include <asm/fpu/internal.h>
  41#include <asm/irqflags.h>
  42
  43typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
  44
  45static inline void set_cpu_flag(int flag)
  46{
  47        S390_lowcore.cpu_flags |= (1UL << flag);
  48}
  49
  50static inline void clear_cpu_flag(int flag)
  51{
  52        S390_lowcore.cpu_flags &= ~(1UL << flag);
  53}
  54
  55static inline int test_cpu_flag(int flag)
  56{
  57        return !!(S390_lowcore.cpu_flags & (1UL << flag));
  58}
  59
  60/*
  61 * Test CIF flag of another CPU. The caller needs to ensure that
  62 * CPU hotplug can not happen, e.g. by disabling preemption.
  63 */
  64static inline int test_cpu_flag_of(int flag, int cpu)
  65{
  66        struct lowcore *lc = lowcore_ptr[cpu];
  67        return !!(lc->cpu_flags & (1UL << flag));
  68}
  69
  70#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
  71
  72static inline void get_cpu_id(struct cpuid *ptr)
  73{
  74        asm volatile("stidp %0" : "=Q" (*ptr));
  75}
  76
  77void s390_adjust_jiffies(void);
  78void s390_update_cpu_mhz(void);
  79void cpu_detect_mhz_feature(void);
  80
  81extern const struct seq_operations cpuinfo_op;
  82extern void execve_tail(void);
  83extern void __bpon(void);
  84
  85/*
  86 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
  87 */
  88
  89#define TASK_SIZE_OF(tsk)       (test_tsk_thread_flag(tsk, TIF_31BIT) ? \
  90                                        _REGION3_SIZE : TASK_SIZE_MAX)
  91#define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_31BIT) ? \
  92                                        (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
  93#define TASK_SIZE               TASK_SIZE_OF(current)
  94#define TASK_SIZE_MAX           (-PAGE_SIZE)
  95
  96#define STACK_TOP               (test_thread_flag(TIF_31BIT) ? \
  97                                        _REGION3_SIZE : _REGION2_SIZE)
  98#define STACK_TOP_MAX           _REGION2_SIZE
  99
 100#define HAVE_ARCH_PICK_MMAP_LAYOUT
 101
 102/*
 103 * Thread structure
 104 */
 105struct thread_struct {
 106        unsigned int  acrs[NUM_ACRS];
 107        unsigned long ksp;                      /* kernel stack pointer */
 108        unsigned long user_timer;               /* task cputime in user space */
 109        unsigned long guest_timer;              /* task cputime in kvm guest */
 110        unsigned long system_timer;             /* task cputime in kernel space */
 111        unsigned long hardirq_timer;            /* task cputime in hardirq context */
 112        unsigned long softirq_timer;            /* task cputime in softirq context */
 113        const sys_call_ptr_t *sys_call_table;   /* system call table address */
 114        unsigned long gmap_addr;                /* address of last gmap fault. */
 115        unsigned int gmap_write_flag;           /* gmap fault write indication */
 116        unsigned int gmap_int_code;             /* int code of last gmap fault */
 117        unsigned int gmap_pfault;               /* signal of a pending guest pfault */
 118
 119        /* Per-thread information related to debugging */
 120        struct per_regs per_user;               /* User specified PER registers */
 121        struct per_event per_event;             /* Cause of the last PER trap */
 122        unsigned long per_flags;                /* Flags to control debug behavior */
 123        unsigned int system_call;               /* system call number in signal */
 124        unsigned long last_break;               /* last breaking-event-address. */
 125        /* pfault_wait is used to block the process on a pfault event */
 126        unsigned long pfault_wait;
 127        struct list_head list;
 128        /* cpu runtime instrumentation */
 129        struct runtime_instr_cb *ri_cb;
 130        struct gs_cb *gs_cb;                    /* Current guarded storage cb */
 131        struct gs_cb *gs_bc_cb;                 /* Broadcast guarded storage cb */
 132        struct pgm_tdb trap_tdb;                /* Transaction abort diagnose block */
 133        /*
 134         * Warning: 'fpu' is dynamically-sized. It *MUST* be at
 135         * the end.
 136         */
 137        struct fpu fpu;                 /* FP and VX register save area */
 138};
 139
 140/* Flag to disable transactions. */
 141#define PER_FLAG_NO_TE                  1UL
 142/* Flag to enable random transaction aborts. */
 143#define PER_FLAG_TE_ABORT_RAND          2UL
 144/* Flag to specify random transaction abort mode:
 145 * - abort each transaction at a random instruction before TEND if set.
 146 * - abort random transactions at a random instruction if cleared.
 147 */
 148#define PER_FLAG_TE_ABORT_RAND_TEND     4UL
 149
 150typedef struct thread_struct thread_struct;
 151
 152#define ARCH_MIN_TASKALIGN      8
 153
 154#define INIT_THREAD {                                                   \
 155        .ksp = sizeof(init_stack) + (unsigned long) &init_stack,        \
 156        .fpu.regs = (void *) init_task.thread.fpu.fprs,                 \
 157        .last_break = 1,                                                \
 158}
 159
 160/*
 161 * Do necessary setup to start up a new thread.
 162 */
 163#define start_thread(regs, new_psw, new_stackp) do {                    \
 164        regs->psw.mask  = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;    \
 165        regs->psw.addr  = new_psw;                                      \
 166        regs->gprs[15]  = new_stackp;                                   \
 167        execve_tail();                                                  \
 168} while (0)
 169
 170#define start_thread31(regs, new_psw, new_stackp) do {                  \
 171        regs->psw.mask  = PSW_USER_BITS | PSW_MASK_BA;                  \
 172        regs->psw.addr  = new_psw;                                      \
 173        regs->gprs[15]  = new_stackp;                                   \
 174        execve_tail();                                                  \
 175} while (0)
 176
 177/* Forward declaration, a strange C thing */
 178struct task_struct;
 179struct mm_struct;
 180struct seq_file;
 181struct pt_regs;
 182
 183void show_registers(struct pt_regs *regs);
 184void show_cacheinfo(struct seq_file *m);
 185
 186/* Free all resources held by a thread. */
 187static inline void release_thread(struct task_struct *tsk) { }
 188
 189/* Free guarded storage control block */
 190void guarded_storage_release(struct task_struct *tsk);
 191void gs_load_bc_cb(struct pt_regs *regs);
 192
 193unsigned long get_wchan(struct task_struct *p);
 194#define task_pt_regs(tsk) ((struct pt_regs *) \
 195        (task_stack_page(tsk) + THREAD_SIZE) - 1)
 196#define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
 197#define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
 198
 199/* Has task runtime instrumentation enabled ? */
 200#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
 201
 202static __always_inline unsigned long current_stack_pointer(void)
 203{
 204        unsigned long sp;
 205
 206        asm volatile("la %0,0(15)" : "=a" (sp));
 207        return sp;
 208}
 209
 210static __always_inline unsigned short stap(void)
 211{
 212        unsigned short cpu_address;
 213
 214        asm volatile("stap %0" : "=Q" (cpu_address));
 215        return cpu_address;
 216}
 217
 218#define cpu_relax() barrier()
 219
 220#define ECAG_CACHE_ATTRIBUTE    0
 221#define ECAG_CPU_ATTRIBUTE      1
 222
 223static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
 224{
 225        unsigned long val;
 226
 227        asm volatile(".insn     rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */
 228                     : "=d" (val) : "a" (asi << 8 | parm));
 229        return val;
 230}
 231
 232static inline void psw_set_key(unsigned int key)
 233{
 234        asm volatile("spka 0(%0)" : : "d" (key));
 235}
 236
 237/*
 238 * Set PSW to specified value.
 239 */
 240static inline void __load_psw(psw_t psw)
 241{
 242        asm volatile("lpswe %0" : : "Q" (psw) : "cc");
 243}
 244
 245/*
 246 * Set PSW mask to specified value, while leaving the
 247 * PSW addr pointing to the next instruction.
 248 */
 249static __always_inline void __load_psw_mask(unsigned long mask)
 250{
 251        unsigned long addr;
 252        psw_t psw;
 253
 254        psw.mask = mask;
 255
 256        asm volatile(
 257                "       larl    %0,1f\n"
 258                "       stg     %0,%1\n"
 259                "       lpswe   %2\n"
 260                "1:"
 261                : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
 262}
 263
 264/*
 265 * Extract current PSW mask
 266 */
 267static inline unsigned long __extract_psw(void)
 268{
 269        unsigned int reg1, reg2;
 270
 271        asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
 272        return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
 273}
 274
 275static inline void local_mcck_enable(void)
 276{
 277        __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
 278}
 279
 280static inline void local_mcck_disable(void)
 281{
 282        __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
 283}
 284
 285/*
 286 * Rewind PSW instruction address by specified number of bytes.
 287 */
 288static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
 289{
 290        unsigned long mask;
 291
 292        mask = (psw.mask & PSW_MASK_EA) ? -1UL :
 293               (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
 294                                          (1UL << 24) - 1;
 295        return (psw.addr - ilc) & mask;
 296}
 297
 298/*
 299 * Function to drop a processor into disabled wait state
 300 */
 301static __always_inline void __noreturn disabled_wait(void)
 302{
 303        psw_t psw;
 304
 305        psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
 306        psw.addr = _THIS_IP_;
 307        __load_psw(psw);
 308        while (1);
 309}
 310
 311/*
 312 * Basic Program Check Handler.
 313 */
 314extern void s390_base_pgm_handler(void);
 315extern void (*s390_base_pgm_handler_fn)(void);
 316
 317#define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
 318
 319extern int memcpy_real(void *, void *, size_t);
 320extern void memcpy_absolute(void *, void *, size_t);
 321
 322#define mem_assign_absolute(dest, val) do {                     \
 323        __typeof__(dest) __tmp = (val);                         \
 324                                                                \
 325        BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));             \
 326        memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));        \
 327} while (0)
 328
 329extern int s390_isolate_bp(void);
 330extern int s390_isolate_bp_guest(void);
 331
 332static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
 333{
 334        return arch_irqs_disabled_flags(regs->psw.mask);
 335}
 336
 337#endif /* __ASSEMBLY__ */
 338
 339#endif /* __ASM_S390_PROCESSOR_H */
 340