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9#include <linux/io.h>
10
11#include <asm/cpu.h>
12#include <asm/smp.h>
13#include <asm/numa.h>
14#include <asm/cacheinfo.h>
15#include <asm/spec-ctrl.h>
16#include <asm/delay.h>
17
18#include "cpu.h"
19
20#define APICID_SOCKET_ID_BIT 6
21
22
23
24
25
26static u32 nodes_per_socket = 1;
27
28#ifdef CONFIG_NUMA
29
30
31
32
33static int nearby_node(int apicid)
34{
35 int i, node;
36
37 for (i = apicid - 1; i >= 0; i--) {
38 node = __apicid_to_node[i];
39 if (node != NUMA_NO_NODE && node_online(node))
40 return node;
41 }
42 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
43 node = __apicid_to_node[i];
44 if (node != NUMA_NO_NODE && node_online(node))
45 return node;
46 }
47 return first_node(node_online_map);
48}
49#endif
50
51static void hygon_get_topology_early(struct cpuinfo_x86 *c)
52{
53 if (cpu_has(c, X86_FEATURE_TOPOEXT))
54 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
55}
56
57
58
59
60
61
62
63static void hygon_get_topology(struct cpuinfo_x86 *c)
64{
65 int cpu = smp_processor_id();
66
67
68 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
69 int err;
70 u32 eax, ebx, ecx, edx;
71
72 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
73
74 c->cpu_die_id = ecx & 0xff;
75
76 c->cpu_core_id = ebx & 0xff;
77
78 if (smp_num_siblings > 1)
79 c->x86_max_cores /= smp_num_siblings;
80
81
82
83
84
85 err = detect_extended_topology(c);
86 if (!err)
87 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
88
89
90 c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;
91
92 cacheinfo_hygon_init_llc_id(c, cpu);
93 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
94 u64 value;
95
96 rdmsrl(MSR_FAM10H_NODE_ID, value);
97 c->cpu_die_id = value & 7;
98
99 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
100 } else
101 return;
102
103 if (nodes_per_socket > 1)
104 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
105}
106
107
108
109
110
111static void hygon_detect_cmp(struct cpuinfo_x86 *c)
112{
113 unsigned int bits;
114 int cpu = smp_processor_id();
115
116 bits = c->x86_coreid_bits;
117
118 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
119
120 c->phys_proc_id = c->initial_apicid >> bits;
121
122 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
123}
124
125static void srat_detect_node(struct cpuinfo_x86 *c)
126{
127#ifdef CONFIG_NUMA
128 int cpu = smp_processor_id();
129 int node;
130 unsigned int apicid = c->apicid;
131
132 node = numa_cpu_node(cpu);
133 if (node == NUMA_NO_NODE)
134 node = per_cpu(cpu_llc_id, cpu);
135
136
137
138
139
140
141 if (x86_cpuinit.fixup_cpu_id)
142 x86_cpuinit.fixup_cpu_id(c, node);
143
144 if (!node_online(node)) {
145
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162
163 int ht_nodeid = c->initial_apicid;
164
165 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
166 node = __apicid_to_node[ht_nodeid];
167
168 if (!node_online(node))
169 node = nearby_node(apicid);
170 }
171 numa_set_node(cpu, node);
172#endif
173}
174
175static void early_init_hygon_mc(struct cpuinfo_x86 *c)
176{
177#ifdef CONFIG_SMP
178 unsigned int bits, ecx;
179
180
181 if (c->extended_cpuid_level < 0x80000008)
182 return;
183
184 ecx = cpuid_ecx(0x80000008);
185
186 c->x86_max_cores = (ecx & 0xff) + 1;
187
188
189 bits = (ecx >> 12) & 0xF;
190
191
192 if (bits == 0) {
193 while ((1 << bits) < c->x86_max_cores)
194 bits++;
195 }
196
197 c->x86_coreid_bits = bits;
198#endif
199}
200
201static void bsp_init_hygon(struct cpuinfo_x86 *c)
202{
203 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
204 u64 val;
205
206 rdmsrl(MSR_K7_HWCR, val);
207 if (!(val & BIT(24)))
208 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
209 }
210
211 if (cpu_has(c, X86_FEATURE_MWAITX))
212 use_mwaitx_delay();
213
214 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
215 u32 ecx;
216
217 ecx = cpuid_ecx(0x8000001e);
218 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
219 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
220 u64 value;
221
222 rdmsrl(MSR_FAM10H_NODE_ID, value);
223 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
224 }
225
226 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
227 !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) {
228
229
230
231
232 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
233 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
234 setup_force_cpu_cap(X86_FEATURE_SSBD);
235 x86_amd_ls_cfg_ssbd_mask = 1ULL << 10;
236 }
237 }
238}
239
240static void early_init_hygon(struct cpuinfo_x86 *c)
241{
242 u32 dummy;
243
244 early_init_hygon_mc(c);
245
246 set_cpu_cap(c, X86_FEATURE_K8);
247
248 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
249
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254 if (c->x86_power & (1 << 8)) {
255 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
256 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
257 }
258
259
260 if (c->x86_power & BIT(12))
261 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
262
263
264 if (c->x86_power & BIT(14))
265 set_cpu_cap(c, X86_FEATURE_RAPL);
266
267#ifdef CONFIG_X86_64
268 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
269#endif
270
271#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
272
273
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275
276 if (boot_cpu_has(X86_FEATURE_APIC))
277 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
278#endif
279
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285 set_cpu_cap(c, X86_FEATURE_VMMCALL);
286
287 hygon_get_topology_early(c);
288}
289
290static void init_hygon(struct cpuinfo_x86 *c)
291{
292 early_init_hygon(c);
293
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298 clear_cpu_cap(c, 0*32+31);
299
300 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
301
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303 c->apicid = hard_smp_processor_id();
304
305 set_cpu_cap(c, X86_FEATURE_ZEN);
306 set_cpu_cap(c, X86_FEATURE_CPB);
307
308 cpu_detect_cache_sizes(c);
309
310 hygon_detect_cmp(c);
311 hygon_get_topology(c);
312 srat_detect_node(c);
313
314 init_hygon_cacheinfo(c);
315
316 if (cpu_has(c, X86_FEATURE_XMM2)) {
317
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321
322
323 msr_set_bit(MSR_F10H_DECFG,
324 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
325
326
327 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
328 }
329
330
331
332
333 set_cpu_cap(c, X86_FEATURE_ARAT);
334
335
336 if (!cpu_has(c, X86_FEATURE_XENPV))
337 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
338}
339
340static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)
341{
342 u32 ebx, eax, ecx, edx;
343 u16 mask = 0xfff;
344
345 if (c->extended_cpuid_level < 0x80000006)
346 return;
347
348 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
349
350 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
351 tlb_lli_4k[ENTRIES] = ebx & mask;
352
353
354 if (!((eax >> 16) & mask))
355 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
356 else
357 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
358
359
360 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
361
362
363 if (!(eax & mask)) {
364 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
365 tlb_lli_2m[ENTRIES] = eax & 0xff;
366 } else
367 tlb_lli_2m[ENTRIES] = eax & mask;
368
369 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
370}
371
372static const struct cpu_dev hygon_cpu_dev = {
373 .c_vendor = "Hygon",
374 .c_ident = { "HygonGenuine" },
375 .c_early_init = early_init_hygon,
376 .c_detect_tlb = cpu_detect_tlb_hygon,
377 .c_bsp_init = bsp_init_hygon,
378 .c_init = init_hygon,
379 .c_x86_vendor = X86_VENDOR_HYGON,
380};
381
382cpu_dev_register(hygon_cpu_dev);
383