1
2config XTENSA
3 def_bool y
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_BINFMT_FLAT if !MMU
6 select ARCH_HAS_DMA_PREP_COHERENT if MMU
7 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
9 select ARCH_HAS_DMA_SET_UNCACHED if MMU
10 select ARCH_USE_MEMTEST
11 select ARCH_USE_QUEUED_RWLOCKS
12 select ARCH_USE_QUEUED_SPINLOCKS
13 select ARCH_WANT_FRAME_POINTERS
14 select ARCH_WANT_IPC_PARSE_VERSION
15 select BUILDTIME_TABLE_SORT
16 select CLONE_BACKWARDS
17 select COMMON_CLK
18 select DMA_REMAP if MMU
19 select GENERIC_ATOMIC64
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_STRNCPY_FROM_USER if KASAN
24 select HAVE_ARCH_AUDITSYSCALL
25 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
26 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
27 select HAVE_ARCH_SECCOMP_FILTER
28 select HAVE_ARCH_TRACEHOOK
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_CONTIGUOUS
31 select HAVE_EXIT_THREAD
32 select HAVE_FUNCTION_TRACER
33 select HAVE_FUTEX_CMPXCHG if !MMU
34 select HAVE_HW_BREAKPOINT if PERF_EVENTS
35 select HAVE_IRQ_TIME_ACCOUNTING
36 select HAVE_PCI
37 select HAVE_PERF_EVENTS
38 select HAVE_STACKPROTECTOR
39 select HAVE_SYSCALL_TRACEPOINTS
40 select IRQ_DOMAIN
41 select MODULES_USE_ELF_RELA
42 select PERF_USE_VMALLOC
43 select SET_FS
44 select VIRT_TO_BUS
45 help
46 Xtensa processors are 32-bit RISC machines designed by Tensilica
47 primarily for embedded systems. These processors are both
48 configurable and extensible. The Linux port to the Xtensa
49 architecture supports all processor configurations and extensions,
50 with reasonable minimum requirements. The Xtensa Linux project has
51 a home page at <http://www.linux-xtensa.org/>.
52
53config GENERIC_HWEIGHT
54 def_bool y
55
56config ARCH_HAS_ILOG2_U32
57 def_bool n
58
59config ARCH_HAS_ILOG2_U64
60 def_bool n
61
62config NO_IOPORT_MAP
63 def_bool n
64
65config HZ
66 int
67 default 100
68
69config LOCKDEP_SUPPORT
70 def_bool y
71
72config STACKTRACE_SUPPORT
73 def_bool y
74
75config TRACE_IRQFLAGS_SUPPORT
76 def_bool y
77
78config MMU
79 def_bool n
80
81config HAVE_XTENSA_GPIO32
82 def_bool n
83
84config KASAN_SHADOW_OFFSET
85 hex
86 default 0x6e400000
87
88config CPU_BIG_ENDIAN
89 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
90
91config CPU_LITTLE_ENDIAN
92 def_bool !CPU_BIG_ENDIAN
93
94menu "Processor type and features"
95
96choice
97 prompt "Xtensa Processor Configuration"
98 default XTENSA_VARIANT_FSF
99
100config XTENSA_VARIANT_FSF
101 bool "fsf - default (not generic) configuration"
102 select MMU
103
104config XTENSA_VARIANT_DC232B
105 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
106 select MMU
107 select HAVE_XTENSA_GPIO32
108 help
109 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
110
111config XTENSA_VARIANT_DC233C
112 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
113 select MMU
114 select HAVE_XTENSA_GPIO32
115 help
116 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
117
118config XTENSA_VARIANT_CUSTOM
119 bool "Custom Xtensa processor configuration"
120 select HAVE_XTENSA_GPIO32
121 help
122 Select this variant to use a custom Xtensa processor configuration.
123 You will be prompted for a processor variant CORENAME.
124endchoice
125
126config XTENSA_VARIANT_CUSTOM_NAME
127 string "Xtensa Processor Custom Core Variant Name"
128 depends on XTENSA_VARIANT_CUSTOM
129 help
130 Provide the name of a custom Xtensa processor variant.
131 This CORENAME selects arch/xtensa/variant/CORENAME.
132 Don't forget you have to select MMU if you have one.
133
134config XTENSA_VARIANT_NAME
135 string
136 default "dc232b" if XTENSA_VARIANT_DC232B
137 default "dc233c" if XTENSA_VARIANT_DC233C
138 default "fsf" if XTENSA_VARIANT_FSF
139 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
140
141config XTENSA_VARIANT_MMU
142 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
143 depends on XTENSA_VARIANT_CUSTOM
144 default y
145 select MMU
146 help
147 Build a Conventional Kernel with full MMU support,
148 ie: it supports a TLB with auto-loading, page protection.
149
150config XTENSA_VARIANT_HAVE_PERF_EVENTS
151 bool "Core variant has Performance Monitor Module"
152 depends on XTENSA_VARIANT_CUSTOM
153 default n
154 help
155 Enable if core variant has Performance Monitor Module with
156 External Registers Interface.
157
158 If unsure, say N.
159
160config XTENSA_FAKE_NMI
161 bool "Treat PMM IRQ as NMI"
162 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
163 default n
164 help
165 If PMM IRQ is the only IRQ at EXCM level it is safe to
166 treat it as NMI, which improves accuracy of profiling.
167
168 If there are other interrupts at or above PMM IRQ priority level
169 but not above the EXCM level, PMM IRQ still may be treated as NMI,
170 but only if these IRQs are not used. There will be a build warning
171 saying that this is not safe, and a bugcheck if one of these IRQs
172 actually fire.
173
174 If unsure, say N.
175
176config XTENSA_UNALIGNED_USER
177 bool "Unaligned memory access in user space"
178 help
179 The Xtensa architecture currently does not handle unaligned
180 memory accesses in hardware but through an exception handler.
181 Per default, unaligned memory accesses are disabled in user space.
182
183 Say Y here to enable unaligned memory access in user space.
184
185config HAVE_SMP
186 bool "System Supports SMP (MX)"
187 depends on XTENSA_VARIANT_CUSTOM
188 select XTENSA_MX
189 help
190 This option is used to indicate that the system-on-a-chip (SOC)
191 supports Multiprocessing. Multiprocessor support implemented above
192 the CPU core definition and currently needs to be selected manually.
193
194 Multiprocessor support is implemented with external cache and
195 interrupt controllers.
196
197 The MX interrupt distributer adds Interprocessor Interrupts
198 and causes the IRQ numbers to be increased by 4 for devices
199 like the open cores ethernet driver and the serial interface.
200
201 You still have to select "Enable SMP" to enable SMP on this SOC.
202
203config SMP
204 bool "Enable Symmetric multi-processing support"
205 depends on HAVE_SMP
206 select GENERIC_SMP_IDLE_THREAD
207 help
208 Enabled SMP Software; allows more than one CPU/CORE
209 to be activated during startup.
210
211config NR_CPUS
212 depends on SMP
213 int "Maximum number of CPUs (2-32)"
214 range 2 32
215 default "4"
216
217config HOTPLUG_CPU
218 bool "Enable CPU hotplug support"
219 depends on SMP
220 help
221 Say Y here to allow turning CPUs off and on. CPUs can be
222 controlled through /sys/devices/system/cpu.
223
224 Say N if you want to disable CPU hotplug.
225
226config FAST_SYSCALL_XTENSA
227 bool "Enable fast atomic syscalls"
228 default n
229 help
230 fast_syscall_xtensa is a syscall that can make atomic operations
231 on UP kernel when processor has no s32c1i support.
232
233 This syscall is deprecated. It may have issues when called with
234 invalid arguments. It is provided only for backwards compatibility.
235 Only enable it if your userspace software requires it.
236
237 If unsure, say N.
238
239config FAST_SYSCALL_SPILL_REGISTERS
240 bool "Enable spill registers syscall"
241 default n
242 help
243 fast_syscall_spill_registers is a syscall that spills all active
244 register windows of a calling userspace task onto its stack.
245
246 This syscall is deprecated. It may have issues when called with
247 invalid arguments. It is provided only for backwards compatibility.
248 Only enable it if your userspace software requires it.
249
250 If unsure, say N.
251
252config USER_ABI_CALL0
253 bool
254
255choice
256 prompt "Userspace ABI"
257 default USER_ABI_DEFAULT
258 help
259 Select supported userspace ABI.
260
261 If unsure, choose the default ABI.
262
263config USER_ABI_DEFAULT
264 bool "Default ABI only"
265 help
266 Assume default userspace ABI. For XEA2 cores it is windowed ABI.
267 call0 ABI binaries may be run on such kernel, but signal delivery
268 will not work correctly for them.
269
270config USER_ABI_CALL0_ONLY
271 bool "Call0 ABI only"
272 select USER_ABI_CALL0
273 help
274 Select this option to support only call0 ABI in userspace.
275 Windowed ABI binaries will crash with a segfault caused by
276 an illegal instruction exception on the first 'entry' opcode.
277
278 Choose this option if you're planning to run only user code
279 built with call0 ABI.
280
281config USER_ABI_CALL0_PROBE
282 bool "Support both windowed and call0 ABI by probing"
283 select USER_ABI_CALL0
284 help
285 Select this option to support both windowed and call0 userspace
286 ABIs. When enabled all processes are started with PS.WOE disabled
287 and a fast user exception handler for an illegal instruction is
288 used to turn on PS.WOE bit on the first 'entry' opcode executed by
289 the userspace.
290
291 This option should be enabled for the kernel that must support
292 both call0 and windowed ABIs in userspace at the same time.
293
294 Note that Xtensa ISA does not guarantee that entry opcode will
295 raise an illegal instruction exception on cores with XEA2 when
296 PS.WOE is disabled, check whether the target core supports it.
297
298endchoice
299
300endmenu
301
302config XTENSA_CALIBRATE_CCOUNT
303 def_bool n
304 help
305 On some platforms (XT2000, for example), the CPU clock rate can
306 vary. The frequency can be determined, however, by measuring
307 against a well known, fixed frequency, such as an UART oscillator.
308
309config SERIAL_CONSOLE
310 def_bool n
311
312config PLATFORM_HAVE_XIP
313 def_bool n
314
315menu "Platform options"
316
317choice
318 prompt "Xtensa System Type"
319 default XTENSA_PLATFORM_ISS
320
321config XTENSA_PLATFORM_ISS
322 bool "ISS"
323 select XTENSA_CALIBRATE_CCOUNT
324 select SERIAL_CONSOLE
325 help
326 ISS is an acronym for Tensilica's Instruction Set Simulator.
327
328config XTENSA_PLATFORM_XT2000
329 bool "XT2000"
330 help
331 XT2000 is the name of Tensilica's feature-rich emulation platform.
332 This hardware is capable of running a full Linux distribution.
333
334config XTENSA_PLATFORM_XTFPGA
335 bool "XTFPGA"
336 select ETHOC if ETHERNET
337 select PLATFORM_WANT_DEFAULT_MEM if !MMU
338 select SERIAL_CONSOLE
339 select XTENSA_CALIBRATE_CCOUNT
340 select PLATFORM_HAVE_XIP
341 help
342 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
343 This hardware is capable of running a full Linux distribution.
344
345endchoice
346
347config PLATFORM_NR_IRQS
348 int
349 default 3 if XTENSA_PLATFORM_XT2000
350 default 0
351
352config XTENSA_CPU_CLOCK
353 int "CPU clock rate [MHz]"
354 depends on !XTENSA_CALIBRATE_CCOUNT
355 default 16
356
357config GENERIC_CALIBRATE_DELAY
358 bool "Auto calibration of the BogoMIPS value"
359 help
360 The BogoMIPS value can easily be derived from the CPU frequency.
361
362config CMDLINE_BOOL
363 bool "Default bootloader kernel arguments"
364
365config CMDLINE
366 string "Initial kernel command string"
367 depends on CMDLINE_BOOL
368 default "console=ttyS0,38400 root=/dev/ram"
369 help
370 On some architectures (EBSA110 and CATS), there is currently no way
371 for the boot loader to pass arguments to the kernel. For these
372 architectures, you should supply some command-line options at build
373 time by entering them here. As a minimum, you should specify the
374 memory size and the root device (e.g., mem=64M root=/dev/nfs).
375
376config USE_OF
377 bool "Flattened Device Tree support"
378 select OF
379 select OF_EARLY_FLATTREE
380 help
381 Include support for flattened device tree machine descriptions.
382
383config BUILTIN_DTB_SOURCE
384 string "DTB to build into the kernel image"
385 depends on OF
386
387config PARSE_BOOTPARAM
388 bool "Parse bootparam block"
389 default y
390 help
391 Parse parameters passed to the kernel from the bootloader. It may
392 be disabled if the kernel is known to run without the bootloader.
393
394 If unsure, say Y.
395
396choice
397 prompt "Semihosting interface"
398 default XTENSA_SIMCALL_ISS
399 depends on XTENSA_PLATFORM_ISS
400 help
401 Choose semihosting interface that will be used for serial port,
402 block device and networking.
403
404config XTENSA_SIMCALL_ISS
405 bool "simcall"
406 help
407 Use simcall instruction. simcall is only available on simulators,
408 it does nothing on hardware.
409
410config XTENSA_SIMCALL_GDBIO
411 bool "GDBIO"
412 help
413 Use break instruction. It is available on real hardware when GDB
414 is attached to it via JTAG.
415
416endchoice
417
418config BLK_DEV_SIMDISK
419 tristate "Host file-based simulated block device support"
420 default n
421 depends on XTENSA_PLATFORM_ISS && BLOCK
422 help
423 Create block devices that map to files in the host file system.
424 Device binding to host file may be changed at runtime via proc
425 interface provided the device is not in use.
426
427config BLK_DEV_SIMDISK_COUNT
428 int "Number of host file-based simulated block devices"
429 range 1 10
430 depends on BLK_DEV_SIMDISK
431 default 2
432 help
433 This is the default minimal number of created block devices.
434 Kernel/module parameter 'simdisk_count' may be used to change this
435 value at runtime. More file names (but no more than 10) may be
436 specified as parameters, simdisk_count grows accordingly.
437
438config SIMDISK0_FILENAME
439 string "Host filename for the first simulated device"
440 depends on BLK_DEV_SIMDISK = y
441 default ""
442 help
443 Attach a first simdisk to a host file. Conventionally, this file
444 contains a root file system.
445
446config SIMDISK1_FILENAME
447 string "Host filename for the second simulated device"
448 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
449 default ""
450 help
451 Another simulated disk in a host file for a buildroot-independent
452 storage.
453
454config XTFPGA_LCD
455 bool "Enable XTFPGA LCD driver"
456 depends on XTENSA_PLATFORM_XTFPGA
457 default n
458 help
459 There's a 2x16 LCD on most of XTFPGA boards, kernel may output
460 progress messages there during bootup/shutdown. It may be useful
461 during board bringup.
462
463 If unsure, say N.
464
465config XTFPGA_LCD_BASE_ADDR
466 hex "XTFPGA LCD base address"
467 depends on XTFPGA_LCD
468 default "0x0d0c0000"
469 help
470 Base address of the LCD controller inside KIO region.
471 Different boards from XTFPGA family have LCD controller at different
472 addresses. Please consult prototyping user guide for your board for
473 the correct address. Wrong address here may lead to hardware lockup.
474
475config XTFPGA_LCD_8BIT_ACCESS
476 bool "Use 8-bit access to XTFPGA LCD"
477 depends on XTFPGA_LCD
478 default n
479 help
480 LCD may be connected with 4- or 8-bit interface, 8-bit access may
481 only be used with 8-bit interface. Please consult prototyping user
482 guide for your board for the correct interface width.
483
484comment "Kernel memory layout"
485
486config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
487 bool "Initialize Xtensa MMU inside the Linux kernel code"
488 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
489 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
490 help
491 Earlier version initialized the MMU in the exception vector
492 before jumping to _startup in head.S and had an advantage that
493 it was possible to place a software breakpoint at 'reset' and
494 then enter your normal kernel breakpoints once the MMU was mapped
495 to the kernel mappings (0XC0000000).
496
497 This unfortunately won't work for U-Boot and likely also won't
498 work for using KEXEC to have a hot kernel ready for doing a
499 KDUMP.
500
501 So now the MMU is initialized in head.S but it's necessary to
502 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
503 xt-gdb can't place a Software Breakpoint in the 0XD region prior
504 to mapping the MMU and after mapping even if the area of low memory
505 was mapped gdb wouldn't remove the breakpoint on hitting it as the
506 PC wouldn't match. Since Hardware Breakpoints are recommended for
507 Linux configurations it seems reasonable to just assume they exist
508 and leave this older mechanism for unfortunate souls that choose
509 not to follow Tensilica's recommendation.
510
511 Selecting this will cause U-Boot to set the KERNEL Load and Entry
512 address at 0x00003000 instead of the mapped std of 0xD0003000.
513
514 If in doubt, say Y.
515
516config XIP_KERNEL
517 bool "Kernel Execute-In-Place from ROM"
518 depends on PLATFORM_HAVE_XIP
519 help
520 Execute-In-Place allows the kernel to run from non-volatile storage
521 directly addressable by the CPU, such as NOR flash. This saves RAM
522 space since the text section of the kernel is not loaded from flash
523 to RAM. Read-write sections, such as the data section and stack,
524 are still copied to RAM. The XIP kernel is not compressed since
525 it has to run directly from flash, so it will take more space to
526 store it. The flash address used to link the kernel object files,
527 and for storing it, is configuration dependent. Therefore, if you
528 say Y here, you must know the proper physical address where to
529 store the kernel image depending on your own flash memory usage.
530
531 Also note that the make target becomes "make xipImage" rather than
532 "make Image" or "make uImage". The final kernel binary to put in
533 ROM memory will be arch/xtensa/boot/xipImage.
534
535 If unsure, say N.
536
537config MEMMAP_CACHEATTR
538 hex "Cache attributes for the memory address space"
539 depends on !MMU
540 default 0x22222222
541 help
542 These cache attributes are set up for noMMU systems. Each hex digit
543 specifies cache attributes for the corresponding 512MB memory
544 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
545 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
546
547 Cache attribute values are specific for the MMU type.
548 For region protection MMUs:
549 1: WT cached,
550 2: cache bypass,
551 4: WB cached,
552 f: illegal.
553 For full MMU:
554 bit 0: executable,
555 bit 1: writable,
556 bits 2..3:
557 0: cache bypass,
558 1: WB cache,
559 2: WT cache,
560 3: special (c and e are illegal, f is reserved).
561 For MPU:
562 0: illegal,
563 1: WB cache,
564 2: WB, no-write-allocate cache,
565 3: WT cache,
566 4: cache bypass.
567
568config KSEG_PADDR
569 hex "Physical address of the KSEG mapping"
570 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
571 default 0x00000000
572 help
573 This is the physical address where KSEG is mapped. Please refer to
574 the chosen KSEG layout help for the required address alignment.
575 Unpacked kernel image (including vectors) must be located completely
576 within KSEG.
577 Physical memory below this address is not available to linux.
578
579 If unsure, leave the default value here.
580
581config KERNEL_VIRTUAL_ADDRESS
582 hex "Kernel virtual address"
583 depends on MMU && XIP_KERNEL
584 default 0xd0003000
585 help
586 This is the virtual address where the XIP kernel is mapped.
587 XIP kernel may be mapped into KSEG or KIO region, virtual address
588 provided here must match kernel load address provided in
589 KERNEL_LOAD_ADDRESS.
590
591config KERNEL_LOAD_ADDRESS
592 hex "Kernel load address"
593 default 0x60003000 if !MMU
594 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
595 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
596 help
597 This is the address where the kernel is loaded.
598 It is virtual address for MMUv2 configurations and physical address
599 for all other configurations.
600
601 If unsure, leave the default value here.
602
603choice
604 prompt "Relocatable vectors location"
605 default XTENSA_VECTORS_IN_TEXT
606 help
607 Choose whether relocatable vectors are merged into the kernel .text
608 or placed separately at runtime. This option does not affect
609 configurations without VECBASE register where vectors are always
610 placed at their hardware-defined locations.
611
612config XTENSA_VECTORS_IN_TEXT
613 bool "Merge relocatable vectors into kernel text"
614 depends on !MTD_XIP
615 help
616 This option puts relocatable vectors into the kernel .text section
617 with proper alignment.
618 This is a safe choice for most configurations.
619
620config XTENSA_VECTORS_SEPARATE
621 bool "Put relocatable vectors at fixed address"
622 help
623 This option puts relocatable vectors at specific virtual address.
624 Vectors are merged with the .init data in the kernel image and
625 are copied into their designated location during kernel startup.
626 Use it to put vectors into IRAM or out of FLASH on kernels with
627 XIP-aware MTD support.
628
629endchoice
630
631config VECTORS_ADDR
632 hex "Kernel vectors virtual address"
633 default 0x00000000
634 depends on XTENSA_VECTORS_SEPARATE
635 help
636 This is the virtual address of the (relocatable) vectors base.
637 It must be within KSEG if MMU is used.
638
639config XIP_DATA_ADDR
640 hex "XIP kernel data virtual address"
641 depends on XIP_KERNEL
642 default 0x00000000
643 help
644 This is the virtual address where XIP kernel data is copied.
645 It must be within KSEG if MMU is used.
646
647config PLATFORM_WANT_DEFAULT_MEM
648 def_bool n
649
650config DEFAULT_MEM_START
651 hex
652 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
653 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
654 default 0x00000000
655 help
656 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
657 in noMMU configurations.
658
659 If unsure, leave the default value here.
660
661choice
662 prompt "KSEG layout"
663 depends on MMU
664 default XTENSA_KSEG_MMU_V2
665
666config XTENSA_KSEG_MMU_V2
667 bool "MMUv2: 128MB cached + 128MB uncached"
668 help
669 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
670 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
671 without cache.
672 KSEG_PADDR must be aligned to 128MB.
673
674config XTENSA_KSEG_256M
675 bool "256MB cached + 256MB uncached"
676 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
677 help
678 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
679 with cache and to 0xc0000000 without cache.
680 KSEG_PADDR must be aligned to 256MB.
681
682config XTENSA_KSEG_512M
683 bool "512MB cached + 512MB uncached"
684 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
685 help
686 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
687 with cache and to 0xc0000000 without cache.
688 KSEG_PADDR must be aligned to 256MB.
689
690endchoice
691
692config HIGHMEM
693 bool "High Memory Support"
694 depends on MMU
695 select KMAP_LOCAL
696 help
697 Linux can use the full amount of RAM in the system by
698 default. However, the default MMUv2 setup only maps the
699 lowermost 128 MB of memory linearly to the areas starting
700 at 0xd0000000 (cached) and 0xd8000000 (uncached).
701 When there are more than 128 MB memory in the system not
702 all of it can be "permanently mapped" by the kernel.
703 The physical memory that's not permanently mapped is called
704 "high memory".
705
706 If you are compiling a kernel which will never run on a
707 machine with more than 128 MB total physical RAM, answer
708 N here.
709
710 If unsure, say Y.
711
712config FORCE_MAX_ZONEORDER
713 int "Maximum zone order"
714 default "11"
715 help
716 The kernel memory allocator divides physically contiguous memory
717 blocks into "zones", where each zone is a power of two number of
718 pages. This option selects the largest power of two that the kernel
719 keeps in the memory allocator. If you need to allocate very large
720 blocks of physically contiguous memory, then you may need to
721 increase this value.
722
723 This config option is actually maximum order plus one. For example,
724 a value of 11 means that the largest free memory block is 2^10 pages.
725
726endmenu
727
728menu "Power management options"
729
730source "kernel/power/Kconfig"
731
732endmenu
733
