1
2
3#include "adf_gen2_hw_data.h"
4#include "icp_qat_hw.h"
5#include <linux/pci.h>
6
7void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
8 int num_a_regs, int num_b_regs)
9{
10 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
11 void __iomem *pmisc_addr;
12 struct adf_bar *pmisc;
13 int pmisc_id, i;
14 u32 reg;
15
16 pmisc_id = hw_data->get_misc_bar_id(hw_data);
17 pmisc = &GET_BARS(accel_dev)[pmisc_id];
18 pmisc_addr = pmisc->virt_addr;
19
20
21 for (i = 0; i < num_a_regs; i++) {
22 reg = READ_CSR_AE2FUNCTION_MAP_A(pmisc_addr, i);
23 if (enable)
24 reg |= AE2FUNCTION_MAP_VALID;
25 else
26 reg &= ~AE2FUNCTION_MAP_VALID;
27 WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_addr, i, reg);
28 }
29
30
31 for (i = 0; i < num_b_regs; i++) {
32 reg = READ_CSR_AE2FUNCTION_MAP_B(pmisc_addr, i);
33 if (enable)
34 reg |= AE2FUNCTION_MAP_VALID;
35 else
36 reg &= ~AE2FUNCTION_MAP_VALID;
37 WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_addr, i, reg);
38 }
39}
40EXPORT_SYMBOL_GPL(adf_gen2_cfg_iov_thds);
41
42void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info)
43{
44 admin_csrs_info->mailbox_offset = ADF_MAILBOX_BASE_OFFSET;
45 admin_csrs_info->admin_msg_ur = ADF_ADMINMSGUR_OFFSET;
46 admin_csrs_info->admin_msg_lr = ADF_ADMINMSGLR_OFFSET;
47}
48EXPORT_SYMBOL_GPL(adf_gen2_get_admin_info);
49
50void adf_gen2_get_arb_info(struct arb_info *arb_info)
51{
52 arb_info->arb_cfg = ADF_ARB_CONFIG;
53 arb_info->arb_offset = ADF_ARB_OFFSET;
54 arb_info->wt2sam_offset = ADF_ARB_WRK_2_SER_MAP_OFFSET;
55}
56EXPORT_SYMBOL_GPL(adf_gen2_get_arb_info);
57
58static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
59{
60 return BUILD_RING_BASE_ADDR(addr, size);
61}
62
63static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
64{
65 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
66}
67
68static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
69 u32 value)
70{
71 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
72}
73
74static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
75{
76 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
77}
78
79static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
80 u32 value)
81{
82 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
83}
84
85static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
86{
87 return READ_CSR_E_STAT(csr_base_addr, bank);
88}
89
90static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
91 u32 ring, u32 value)
92{
93 WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
94}
95
96static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
97 dma_addr_t addr)
98{
99 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
100}
101
102static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value)
103{
104 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
105}
106
107static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
108{
109 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
110}
111
112static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank,
113 u32 value)
114{
115 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
116}
117
118static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
119 u32 value)
120{
121 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
122}
123
124static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
125 u32 value)
126{
127 WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
128}
129
130static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
131 u32 value)
132{
133 WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
134}
135
136void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
137{
138 csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
139 csr_ops->read_csr_ring_head = read_csr_ring_head;
140 csr_ops->write_csr_ring_head = write_csr_ring_head;
141 csr_ops->read_csr_ring_tail = read_csr_ring_tail;
142 csr_ops->write_csr_ring_tail = write_csr_ring_tail;
143 csr_ops->read_csr_e_stat = read_csr_e_stat;
144 csr_ops->write_csr_ring_config = write_csr_ring_config;
145 csr_ops->write_csr_ring_base = write_csr_ring_base;
146 csr_ops->write_csr_int_flag = write_csr_int_flag;
147 csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
148 csr_ops->write_csr_int_col_en = write_csr_int_col_en;
149 csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
150 csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
151 csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
152}
153EXPORT_SYMBOL_GPL(adf_gen2_init_hw_csr_ops);
154
155u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev)
156{
157 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
158 struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
159 u32 straps = hw_data->straps;
160 u32 fuses = hw_data->fuses;
161 u32 legfuses;
162 u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
163 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
164 ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
165
166
167 pci_read_config_dword(pdev, ADF_DEVICE_LEGFUSE_OFFSET, &legfuses);
168
169 if (legfuses & ICP_ACCEL_MASK_CIPHER_SLICE)
170 capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
171 if (legfuses & ICP_ACCEL_MASK_PKE_SLICE)
172 capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
173 if (legfuses & ICP_ACCEL_MASK_AUTH_SLICE)
174 capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
175
176 if ((straps | fuses) & ADF_POWERGATE_PKE)
177 capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
178
179 return capabilities;
180}
181EXPORT_SYMBOL_GPL(adf_gen2_get_accel_cap);
182
183void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)
184{
185 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
186 u32 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;
187 u32 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;
188 unsigned long accel_mask = hw_data->accel_mask;
189 void __iomem *pmisc_addr;
190 struct adf_bar *pmisc;
191 int pmisc_id;
192 u32 i = 0;
193
194 pmisc_id = hw_data->get_misc_bar_id(hw_data);
195 pmisc = &GET_BARS(accel_dev)[pmisc_id];
196 pmisc_addr = pmisc->virt_addr;
197
198
199 for_each_set_bit(i, &accel_mask, hw_data->num_accel) {
200
201 ADF_CSR_WR(pmisc_addr, ADF_SSMWDT(i), timer_val);
202
203 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKE(i), timer_val_pke);
204 }
205}
206EXPORT_SYMBOL_GPL(adf_gen2_set_ssm_wdtimer);
207
