LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1// SPDX-License-Identifier: MIT
   2/* Copyright 2021 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: David Nieto
  23 *          Roy Sun
  24 */
  25
  26#include <linux/debugfs.h>
  27#include <linux/list.h>
  28#include <linux/module.h>
  29#include <linux/uaccess.h>
  30#include <linux/reboot.h>
  31#include <linux/syscalls.h>
  32
  33#include <drm/amdgpu_drm.h>
  34#include <drm/drm_debugfs.h>
  35
  36#include "amdgpu.h"
  37#include "amdgpu_vm.h"
  38#include "amdgpu_gem.h"
  39#include "amdgpu_ctx.h"
  40#include "amdgpu_fdinfo.h"
  41
  42
  43static const char *amdgpu_ip_name[AMDGPU_HW_IP_NUM] = {
  44        [AMDGPU_HW_IP_GFX]      =       "gfx",
  45        [AMDGPU_HW_IP_COMPUTE]  =       "compute",
  46        [AMDGPU_HW_IP_DMA]      =       "dma",
  47        [AMDGPU_HW_IP_UVD]      =       "dec",
  48        [AMDGPU_HW_IP_VCE]      =       "enc",
  49        [AMDGPU_HW_IP_UVD_ENC]  =       "enc_1",
  50        [AMDGPU_HW_IP_VCN_DEC]  =       "dec",
  51        [AMDGPU_HW_IP_VCN_ENC]  =       "enc",
  52        [AMDGPU_HW_IP_VCN_JPEG] =       "jpeg",
  53};
  54
  55void amdgpu_show_fdinfo(struct seq_file *m, struct file *f)
  56{
  57        struct amdgpu_fpriv *fpriv;
  58        uint32_t bus, dev, fn, i, domain;
  59        uint64_t vram_mem = 0, gtt_mem = 0, cpu_mem = 0;
  60        struct drm_file *file = f->private_data;
  61        struct amdgpu_device *adev = drm_to_adev(file->minor->dev);
  62        int ret;
  63
  64        ret = amdgpu_file_to_fpriv(f, &fpriv);
  65        if (ret)
  66                return;
  67        bus = adev->pdev->bus->number;
  68        domain = pci_domain_nr(adev->pdev->bus);
  69        dev = PCI_SLOT(adev->pdev->devfn);
  70        fn = PCI_FUNC(adev->pdev->devfn);
  71
  72        ret = amdgpu_bo_reserve(fpriv->vm.root.bo, false);
  73        if (ret) {
  74                DRM_ERROR("Fail to reserve bo\n");
  75                return;
  76        }
  77        amdgpu_vm_get_memory(&fpriv->vm, &vram_mem, &gtt_mem, &cpu_mem);
  78        amdgpu_bo_unreserve(fpriv->vm.root.bo);
  79        seq_printf(m, "pdev:\t%04x:%02x:%02x.%d\npasid:\t%u\n", domain, bus,
  80                        dev, fn, fpriv->vm.pasid);
  81        seq_printf(m, "vram mem:\t%llu kB\n", vram_mem/1024UL);
  82        seq_printf(m, "gtt mem:\t%llu kB\n", gtt_mem/1024UL);
  83        seq_printf(m, "cpu mem:\t%llu kB\n", cpu_mem/1024UL);
  84        for (i = 0; i < AMDGPU_HW_IP_NUM; i++) {
  85                uint32_t count = amdgpu_ctx_num_entities[i];
  86                int idx = 0;
  87                uint64_t total = 0, min = 0;
  88                uint32_t perc, frac;
  89
  90                for (idx = 0; idx < count; idx++) {
  91                        total = amdgpu_ctx_mgr_fence_usage(&fpriv->ctx_mgr,
  92                                i, idx, &min);
  93                        if ((total == 0) || (min == 0))
  94                                continue;
  95
  96                        perc = div64_u64(10000 * total, min);
  97                        frac = perc % 100;
  98
  99                        seq_printf(m, "%s%d:\t%d.%d%%\n",
 100                                        amdgpu_ip_name[i],
 101                                        idx, perc/100, frac);
 102                }
 103        }
 104}
 105