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29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include "amdgpu.h"
37#include "amdgpu_trace.h"
38#include "amdgpu_amdkfd.h"
39#include "amdgpu_gmc.h"
40#include "amdgpu_xgmi.h"
41#include "amdgpu_dma_buf.h"
42#include "amdgpu_res_cursor.h"
43#include "kfd_svm.h"
44
45
46
47
48
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50
51
52
53
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60
61
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63
64
65
66#define START(node) ((node)->start)
67#define LAST(node) ((node)->last)
68
69INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
70 START, LAST, static, amdgpu_vm_it)
71
72#undef START
73#undef LAST
74
75
76
77
78struct amdgpu_prt_cb {
79
80
81
82
83 struct amdgpu_device *adev;
84
85
86
87
88 struct dma_fence_cb cb;
89};
90
91
92
93
94
95
96static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
97{
98 mutex_lock(&vm->eviction_lock);
99 vm->saved_flags = memalloc_noreclaim_save();
100}
101
102static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
103{
104 if (mutex_trylock(&vm->eviction_lock)) {
105 vm->saved_flags = memalloc_noreclaim_save();
106 return 1;
107 }
108 return 0;
109}
110
111static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
112{
113 memalloc_noreclaim_restore(vm->saved_flags);
114 mutex_unlock(&vm->eviction_lock);
115}
116
117
118
119
120
121
122
123
124
125
126static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
127 unsigned level)
128{
129 switch (level) {
130 case AMDGPU_VM_PDB2:
131 case AMDGPU_VM_PDB1:
132 case AMDGPU_VM_PDB0:
133 return 9 * (AMDGPU_VM_PDB0 - level) +
134 adev->vm_manager.block_size;
135 case AMDGPU_VM_PTB:
136 return 0;
137 default:
138 return ~0;
139 }
140}
141
142
143
144
145
146
147
148
149
150
151static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
152 unsigned level)
153{
154 unsigned shift = amdgpu_vm_level_shift(adev,
155 adev->vm_manager.root_level);
156
157 if (level == adev->vm_manager.root_level)
158
159 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
160 >> shift;
161 else if (level != AMDGPU_VM_PTB)
162
163 return 512;
164 else
165
166 return AMDGPU_VM_PTE_COUNT(adev);
167}
168
169
170
171
172
173
174
175
176
177static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
178{
179 unsigned shift;
180
181 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
182 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
183}
184
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192
193
194static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
195 unsigned int level)
196{
197 if (level <= adev->vm_manager.root_level)
198 return 0xffffffff;
199 else if (level != AMDGPU_VM_PTB)
200 return 0x1ff;
201 else
202 return AMDGPU_VM_PTE_COUNT(adev) - 1;
203}
204
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212
213
214static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
215{
216 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
217}
218
219
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225
226
227static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
228{
229 struct amdgpu_vm *vm = vm_bo->vm;
230 struct amdgpu_bo *bo = vm_bo->bo;
231
232 vm_bo->moved = true;
233 if (bo->tbo.type == ttm_bo_type_kernel)
234 list_move(&vm_bo->vm_status, &vm->evicted);
235 else
236 list_move_tail(&vm_bo->vm_status, &vm->evicted);
237}
238
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243
244
245
246static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
247{
248 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
249}
250
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258
259static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
260{
261 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
262 vm_bo->moved = false;
263}
264
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271
272
273static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
274{
275 spin_lock(&vm_bo->vm->invalidated_lock);
276 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
277 spin_unlock(&vm_bo->vm->invalidated_lock);
278}
279
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286
287
288static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
289{
290 if (vm_bo->bo->parent)
291 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
292 else
293 amdgpu_vm_bo_idle(vm_bo);
294}
295
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302
303
304static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
305{
306 spin_lock(&vm_bo->vm->invalidated_lock);
307 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
308 spin_unlock(&vm_bo->vm->invalidated_lock);
309}
310
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319
320
321static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
322 struct amdgpu_vm *vm,
323 struct amdgpu_bo *bo)
324{
325 base->vm = vm;
326 base->bo = bo;
327 base->next = NULL;
328 INIT_LIST_HEAD(&base->vm_status);
329
330 if (!bo)
331 return;
332 base->next = bo->vm_bo;
333 bo->vm_bo = base;
334
335 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
336 return;
337
338 vm->bulk_moveable = false;
339 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
340 amdgpu_vm_bo_relocated(base);
341 else
342 amdgpu_vm_bo_idle(base);
343
344 if (bo->preferred_domains &
345 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
346 return;
347
348
349
350
351
352
353 amdgpu_vm_bo_evicted(base);
354}
355
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363
364static struct amdgpu_vm_bo_base *amdgpu_vm_pt_parent(struct amdgpu_vm_bo_base *pt)
365{
366 struct amdgpu_bo *parent = pt->bo->parent;
367
368 if (!parent)
369 return NULL;
370
371 return parent->vm_bo;
372}
373
374
375
376
377struct amdgpu_vm_pt_cursor {
378 uint64_t pfn;
379 struct amdgpu_vm_bo_base *parent;
380 struct amdgpu_vm_bo_base *entry;
381 unsigned level;
382};
383
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393
394static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm, uint64_t start,
396 struct amdgpu_vm_pt_cursor *cursor)
397{
398 cursor->pfn = start;
399 cursor->parent = NULL;
400 cursor->entry = &vm->root;
401 cursor->level = adev->vm_manager.root_level;
402}
403
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411
412
413
414static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
415 struct amdgpu_vm_pt_cursor *cursor)
416{
417 unsigned mask, shift, idx;
418
419 if ((cursor->level == AMDGPU_VM_PTB) || !cursor->entry ||
420 !cursor->entry->bo)
421 return false;
422
423 mask = amdgpu_vm_entries_mask(adev, cursor->level);
424 shift = amdgpu_vm_level_shift(adev, cursor->level);
425
426 ++cursor->level;
427 idx = (cursor->pfn >> shift) & mask;
428 cursor->parent = cursor->entry;
429 cursor->entry = &to_amdgpu_bo_vm(cursor->entry->bo)->entries[idx];
430 return true;
431}
432
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441
442
443static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
444 struct amdgpu_vm_pt_cursor *cursor)
445{
446 unsigned shift, num_entries;
447
448
449 if (!cursor->parent)
450 return false;
451
452
453 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
454 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
455
456 if (cursor->entry == &to_amdgpu_bo_vm(cursor->parent->bo)->entries[num_entries - 1])
457 return false;
458
459 cursor->pfn += 1ULL << shift;
460 cursor->pfn &= ~((1ULL << shift) - 1);
461 ++cursor->entry;
462 return true;
463}
464
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471
472
473
474static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
475{
476 if (!cursor->parent)
477 return false;
478
479 --cursor->level;
480 cursor->entry = cursor->parent;
481 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
482 return true;
483}
484
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491
492
493static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
494 struct amdgpu_vm_pt_cursor *cursor)
495{
496
497 if (amdgpu_vm_pt_descendant(adev, cursor))
498 return;
499
500
501 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
502
503 if (!amdgpu_vm_pt_ancestor(cursor)) {
504 cursor->pfn = ~0ll;
505 return;
506 }
507 }
508}
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519
520static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
521 struct amdgpu_vm *vm,
522 struct amdgpu_vm_pt_cursor *start,
523 struct amdgpu_vm_pt_cursor *cursor)
524{
525 if (start)
526 *cursor = *start;
527 else
528 amdgpu_vm_pt_start(adev, vm, 0, cursor);
529 while (amdgpu_vm_pt_descendant(adev, cursor));
530}
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540
541static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
542 struct amdgpu_vm_bo_base *entry)
543{
544 return entry && (!start || entry != start->entry);
545}
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553
554
555static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
556 struct amdgpu_vm_pt_cursor *cursor)
557{
558 if (!cursor->entry)
559 return;
560
561 if (!cursor->parent)
562 cursor->entry = NULL;
563 else if (amdgpu_vm_pt_sibling(adev, cursor))
564 while (amdgpu_vm_pt_descendant(adev, cursor));
565 else
566 amdgpu_vm_pt_ancestor(cursor);
567}
568
569
570
571
572#define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
573 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
574 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
575 amdgpu_vm_pt_continue_dfs((start), (entry)); \
576 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
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588void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
589 struct list_head *validated,
590 struct amdgpu_bo_list_entry *entry)
591{
592 entry->priority = 0;
593 entry->tv.bo = &vm->root.bo->tbo;
594
595 entry->tv.num_shared = 4;
596 entry->user_pages = NULL;
597 list_add(&entry->tv.head, validated);
598}
599
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607
608void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
609{
610 struct amdgpu_bo *abo;
611 struct amdgpu_vm_bo_base *bo_base;
612
613 if (!amdgpu_bo_is_amdgpu_bo(bo))
614 return;
615
616 if (bo->pin_count)
617 return;
618
619 abo = ttm_to_amdgpu_bo(bo);
620 if (!abo->parent)
621 return;
622 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
623 struct amdgpu_vm *vm = bo_base->vm;
624
625 if (abo->tbo.base.resv == vm->root.bo->tbo.base.resv)
626 vm->bulk_moveable = false;
627 }
628
629}
630
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637
638
639void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
640 struct amdgpu_vm *vm)
641{
642 struct amdgpu_vm_bo_base *bo_base;
643
644 if (vm->bulk_moveable) {
645 spin_lock(&adev->mman.bdev.lru_lock);
646 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
647 spin_unlock(&adev->mman.bdev.lru_lock);
648 return;
649 }
650
651 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
652
653 spin_lock(&adev->mman.bdev.lru_lock);
654 list_for_each_entry(bo_base, &vm->idle, vm_status) {
655 struct amdgpu_bo *bo = bo_base->bo;
656 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
657
658 if (!bo->parent)
659 continue;
660
661 ttm_bo_move_to_lru_tail(&bo->tbo, bo->tbo.resource,
662 &vm->lru_bulk_move);
663 if (shadow)
664 ttm_bo_move_to_lru_tail(&shadow->tbo,
665 shadow->tbo.resource,
666 &vm->lru_bulk_move);
667 }
668 spin_unlock(&adev->mman.bdev.lru_lock);
669
670 vm->bulk_moveable = true;
671}
672
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685
686int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
687 int (*validate)(void *p, struct amdgpu_bo *bo),
688 void *param)
689{
690 struct amdgpu_vm_bo_base *bo_base, *tmp;
691 int r;
692
693 vm->bulk_moveable &= list_empty(&vm->evicted);
694
695 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
696 struct amdgpu_bo *bo = bo_base->bo;
697 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
698
699 r = validate(param, bo);
700 if (r)
701 return r;
702 if (shadow) {
703 r = validate(param, shadow);
704 if (r)
705 return r;
706 }
707
708 if (bo->tbo.type != ttm_bo_type_kernel) {
709 amdgpu_vm_bo_moved(bo_base);
710 } else {
711 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
712 amdgpu_vm_bo_relocated(bo_base);
713 }
714 }
715
716 amdgpu_vm_eviction_lock(vm);
717 vm->evicting = false;
718 amdgpu_vm_eviction_unlock(vm);
719
720 return 0;
721}
722
723
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730
731
732
733bool amdgpu_vm_ready(struct amdgpu_vm *vm)
734{
735 return list_empty(&vm->evicted);
736}
737
738
739
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741
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749
750
751static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
752 struct amdgpu_vm *vm,
753 struct amdgpu_bo_vm *vmbo,
754 bool immediate)
755{
756 struct ttm_operation_ctx ctx = { true, false };
757 unsigned level = adev->vm_manager.root_level;
758 struct amdgpu_vm_update_params params;
759 struct amdgpu_bo *ancestor = &vmbo->bo;
760 struct amdgpu_bo *bo = &vmbo->bo;
761 unsigned entries, ats_entries;
762 uint64_t addr;
763 int r;
764
765
766 if (ancestor->parent) {
767 ++level;
768 while (ancestor->parent->parent) {
769 ++level;
770 ancestor = ancestor->parent;
771 }
772 }
773
774 entries = amdgpu_bo_size(bo) / 8;
775 if (!vm->pte_support_ats) {
776 ats_entries = 0;
777
778 } else if (!bo->parent) {
779 ats_entries = amdgpu_vm_num_ats_entries(adev);
780 ats_entries = min(ats_entries, entries);
781 entries -= ats_entries;
782
783 } else {
784 struct amdgpu_vm_bo_base *pt;
785
786 pt = ancestor->vm_bo;
787 ats_entries = amdgpu_vm_num_ats_entries(adev);
788 if ((pt - to_amdgpu_bo_vm(vm->root.bo)->entries) >= ats_entries) {
789 ats_entries = 0;
790 } else {
791 ats_entries = entries;
792 entries = 0;
793 }
794 }
795
796 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
797 if (r)
798 return r;
799
800 if (vmbo->shadow) {
801 struct amdgpu_bo *shadow = vmbo->shadow;
802
803 r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx);
804 if (r)
805 return r;
806 }
807
808 r = vm->update_funcs->map_table(vmbo);
809 if (r)
810 return r;
811
812 memset(¶ms, 0, sizeof(params));
813 params.adev = adev;
814 params.vm = vm;
815 params.immediate = immediate;
816
817 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
818 if (r)
819 return r;
820
821 addr = 0;
822 if (ats_entries) {
823 uint64_t value = 0, flags;
824
825 flags = AMDGPU_PTE_DEFAULT_ATC;
826 if (level != AMDGPU_VM_PTB) {
827
828 flags |= AMDGPU_PDE_PTE;
829 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
830 }
831
832 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, ats_entries,
833 value, flags);
834 if (r)
835 return r;
836
837 addr += ats_entries * 8;
838 }
839
840 if (entries) {
841 uint64_t value = 0, flags = 0;
842
843 if (adev->asic_type >= CHIP_VEGA10) {
844 if (level != AMDGPU_VM_PTB) {
845
846 flags |= AMDGPU_PDE_PTE;
847 amdgpu_gmc_get_vm_pde(adev, level,
848 &value, &flags);
849 } else {
850
851 flags = AMDGPU_PTE_EXECUTABLE;
852 }
853 }
854
855 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, entries,
856 value, flags);
857 if (r)
858 return r;
859 }
860
861 return vm->update_funcs->commit(¶ms, NULL);
862}
863
864
865
866
867
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869
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871
872
873static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
874 struct amdgpu_vm *vm,
875 int level, bool immediate,
876 struct amdgpu_bo_vm **vmbo)
877{
878 struct amdgpu_bo_param bp;
879 struct amdgpu_bo *bo;
880 struct dma_resv *resv;
881 unsigned int num_entries;
882 int r;
883
884 memset(&bp, 0, sizeof(bp));
885
886 bp.size = amdgpu_vm_bo_size(adev, level);
887 bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
888 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
889 bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
890 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
891 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
892
893 if (level < AMDGPU_VM_PTB)
894 num_entries = amdgpu_vm_num_entries(adev, level);
895 else
896 num_entries = 0;
897
898 bp.bo_ptr_size = struct_size((*vmbo), entries, num_entries);
899
900 if (vm->use_cpu_for_update)
901 bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
902
903 bp.type = ttm_bo_type_kernel;
904 bp.no_wait_gpu = immediate;
905 if (vm->root.bo)
906 bp.resv = vm->root.bo->tbo.base.resv;
907
908 r = amdgpu_bo_create_vm(adev, &bp, vmbo);
909 if (r)
910 return r;
911
912 bo = &(*vmbo)->bo;
913 if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) {
914 (*vmbo)->shadow = NULL;
915 return 0;
916 }
917
918 if (!bp.resv)
919 WARN_ON(dma_resv_lock(bo->tbo.base.resv,
920 NULL));
921 resv = bp.resv;
922 memset(&bp, 0, sizeof(bp));
923 bp.size = amdgpu_vm_bo_size(adev, level);
924 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
925 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
926 bp.type = ttm_bo_type_kernel;
927 bp.resv = bo->tbo.base.resv;
928 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
929
930 r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow);
931
932 if (!resv)
933 dma_resv_unlock(bo->tbo.base.resv);
934
935 if (r) {
936 amdgpu_bo_unref(&bo);
937 return r;
938 }
939
940 (*vmbo)->shadow->parent = amdgpu_bo_ref(bo);
941 amdgpu_bo_add_to_shadow_list(*vmbo);
942
943 return 0;
944}
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946
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958
959
960static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
961 struct amdgpu_vm *vm,
962 struct amdgpu_vm_pt_cursor *cursor,
963 bool immediate)
964{
965 struct amdgpu_vm_bo_base *entry = cursor->entry;
966 struct amdgpu_bo *pt_bo;
967 struct amdgpu_bo_vm *pt;
968 int r;
969
970 if (entry->bo)
971 return 0;
972
973 r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
974 if (r)
975 return r;
976
977
978
979
980 pt_bo = &pt->bo;
981 pt_bo->parent = amdgpu_bo_ref(cursor->parent->bo);
982 amdgpu_vm_bo_base_init(entry, vm, pt_bo);
983 r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
984 if (r)
985 goto error_free_pt;
986
987 return 0;
988
989error_free_pt:
990 amdgpu_bo_unref(&pt->shadow);
991 amdgpu_bo_unref(&pt_bo);
992 return r;
993}
994
995
996
997
998
999
1000static void amdgpu_vm_free_table(struct amdgpu_vm_bo_base *entry)
1001{
1002 struct amdgpu_bo *shadow;
1003
1004 if (!entry->bo)
1005 return;
1006 shadow = amdgpu_bo_shadowed(entry->bo);
1007 entry->bo->vm_bo = NULL;
1008 list_del(&entry->vm_status);
1009 amdgpu_bo_unref(&shadow);
1010 amdgpu_bo_unref(&entry->bo);
1011}
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
1023 struct amdgpu_vm *vm,
1024 struct amdgpu_vm_pt_cursor *start)
1025{
1026 struct amdgpu_vm_pt_cursor cursor;
1027 struct amdgpu_vm_bo_base *entry;
1028
1029 vm->bulk_moveable = false;
1030
1031 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
1032 amdgpu_vm_free_table(entry);
1033
1034 if (start)
1035 amdgpu_vm_free_table(start->entry);
1036}
1037
1038
1039
1040
1041
1042
1043void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
1044{
1045 const struct amdgpu_ip_block *ip_block;
1046 bool has_compute_vm_bug;
1047 struct amdgpu_ring *ring;
1048 int i;
1049
1050 has_compute_vm_bug = false;
1051
1052 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
1053 if (ip_block) {
1054
1055
1056 if (ip_block->version->major <= 7)
1057 has_compute_vm_bug = true;
1058 else if (ip_block->version->major == 8)
1059 if (adev->gfx.mec_fw_version < 673)
1060 has_compute_vm_bug = true;
1061 }
1062
1063 for (i = 0; i < adev->num_rings; i++) {
1064 ring = adev->rings[i];
1065 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1066
1067 ring->has_compute_vm_bug = has_compute_vm_bug;
1068 else
1069 ring->has_compute_vm_bug = false;
1070 }
1071}
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1083 struct amdgpu_job *job)
1084{
1085 struct amdgpu_device *adev = ring->adev;
1086 unsigned vmhub = ring->funcs->vmhub;
1087 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1088 struct amdgpu_vmid *id;
1089 bool gds_switch_needed;
1090 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1091
1092 if (job->vmid == 0)
1093 return false;
1094 id = &id_mgr->ids[job->vmid];
1095 gds_switch_needed = ring->funcs->emit_gds_switch && (
1096 id->gds_base != job->gds_base ||
1097 id->gds_size != job->gds_size ||
1098 id->gws_base != job->gws_base ||
1099 id->gws_size != job->gws_size ||
1100 id->oa_base != job->oa_base ||
1101 id->oa_size != job->oa_size);
1102
1103 if (amdgpu_vmid_had_gpu_reset(adev, id))
1104 return true;
1105
1106 return vm_flush_needed || gds_switch_needed;
1107}
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1122 bool need_pipe_sync)
1123{
1124 struct amdgpu_device *adev = ring->adev;
1125 unsigned vmhub = ring->funcs->vmhub;
1126 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1127 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1128 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1129 id->gds_base != job->gds_base ||
1130 id->gds_size != job->gds_size ||
1131 id->gws_base != job->gws_base ||
1132 id->gws_size != job->gws_size ||
1133 id->oa_base != job->oa_base ||
1134 id->oa_size != job->oa_size);
1135 bool vm_flush_needed = job->vm_needs_flush;
1136 struct dma_fence *fence = NULL;
1137 bool pasid_mapping_needed = false;
1138 unsigned patch_offset = 0;
1139 bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
1140 int r;
1141
1142 if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
1143 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
1144
1145 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1146 gds_switch_needed = true;
1147 vm_flush_needed = true;
1148 pasid_mapping_needed = true;
1149 }
1150
1151 mutex_lock(&id_mgr->lock);
1152 if (id->pasid != job->pasid || !id->pasid_mapping ||
1153 !dma_fence_is_signaled(id->pasid_mapping))
1154 pasid_mapping_needed = true;
1155 mutex_unlock(&id_mgr->lock);
1156
1157 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1158 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1159 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1160 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1161 ring->funcs->emit_wreg;
1162
1163 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1164 return 0;
1165
1166 if (ring->funcs->init_cond_exec)
1167 patch_offset = amdgpu_ring_init_cond_exec(ring);
1168
1169 if (need_pipe_sync)
1170 amdgpu_ring_emit_pipeline_sync(ring);
1171
1172 if (vm_flush_needed) {
1173 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1174 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1175 }
1176
1177 if (pasid_mapping_needed)
1178 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1179
1180 if (vm_flush_needed || pasid_mapping_needed) {
1181 r = amdgpu_fence_emit(ring, &fence, 0);
1182 if (r)
1183 return r;
1184 }
1185
1186 if (vm_flush_needed) {
1187 mutex_lock(&id_mgr->lock);
1188 dma_fence_put(id->last_flush);
1189 id->last_flush = dma_fence_get(fence);
1190 id->current_gpu_reset_count =
1191 atomic_read(&adev->gpu_reset_counter);
1192 mutex_unlock(&id_mgr->lock);
1193 }
1194
1195 if (pasid_mapping_needed) {
1196 mutex_lock(&id_mgr->lock);
1197 id->pasid = job->pasid;
1198 dma_fence_put(id->pasid_mapping);
1199 id->pasid_mapping = dma_fence_get(fence);
1200 mutex_unlock(&id_mgr->lock);
1201 }
1202 dma_fence_put(fence);
1203
1204 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1205 id->gds_base = job->gds_base;
1206 id->gds_size = job->gds_size;
1207 id->gws_base = job->gws_base;
1208 id->gws_size = job->gws_size;
1209 id->oa_base = job->oa_base;
1210 id->oa_size = job->oa_size;
1211 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1212 job->gds_size, job->gws_base,
1213 job->gws_size, job->oa_base,
1214 job->oa_size);
1215 }
1216
1217 if (ring->funcs->patch_cond_exec)
1218 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1219
1220
1221 if (ring->funcs->emit_switch_buffer) {
1222 amdgpu_ring_emit_switch_buffer(ring);
1223 amdgpu_ring_emit_switch_buffer(ring);
1224 }
1225 return 0;
1226}
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1244 struct amdgpu_bo *bo)
1245{
1246 struct amdgpu_vm_bo_base *base;
1247
1248 for (base = bo->vm_bo; base; base = base->next) {
1249 if (base->vm != vm)
1250 continue;
1251
1252 return container_of(base, struct amdgpu_bo_va, base);
1253 }
1254 return NULL;
1255}
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1270{
1271 uint64_t result;
1272
1273
1274 result = pages_addr[addr >> PAGE_SHIFT];
1275
1276
1277 result |= addr & (~PAGE_MASK);
1278
1279 result &= 0xFFFFFFFFFFFFF000ULL;
1280
1281 return result;
1282}
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1294 struct amdgpu_vm *vm,
1295 struct amdgpu_vm_bo_base *entry)
1296{
1297 struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
1298 struct amdgpu_bo *bo = parent->bo, *pbo;
1299 uint64_t pde, pt, flags;
1300 unsigned level;
1301
1302 for (level = 0, pbo = bo->parent; pbo; ++level)
1303 pbo = pbo->parent;
1304
1305 level += params->adev->vm_manager.root_level;
1306 amdgpu_gmc_get_pde_for_bo(entry->bo, level, &pt, &flags);
1307 pde = (entry - to_amdgpu_bo_vm(parent->bo)->entries) * 8;
1308 return vm->update_funcs->update(params, to_amdgpu_bo_vm(bo), pde, pt,
1309 1, 0, flags);
1310}
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1321 struct amdgpu_vm *vm)
1322{
1323 struct amdgpu_vm_pt_cursor cursor;
1324 struct amdgpu_vm_bo_base *entry;
1325
1326 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1327 if (entry->bo && !entry->moved)
1328 amdgpu_vm_bo_relocated(entry);
1329}
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1344 struct amdgpu_vm *vm, bool immediate)
1345{
1346 struct amdgpu_vm_update_params params;
1347 int r;
1348
1349 if (list_empty(&vm->relocated))
1350 return 0;
1351
1352 memset(¶ms, 0, sizeof(params));
1353 params.adev = adev;
1354 params.vm = vm;
1355 params.immediate = immediate;
1356
1357 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
1358 if (r)
1359 return r;
1360
1361 while (!list_empty(&vm->relocated)) {
1362 struct amdgpu_vm_bo_base *entry;
1363
1364 entry = list_first_entry(&vm->relocated,
1365 struct amdgpu_vm_bo_base,
1366 vm_status);
1367 amdgpu_vm_bo_idle(entry);
1368
1369 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1370 if (r)
1371 goto error;
1372 }
1373
1374 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1375 if (r)
1376 goto error;
1377 return 0;
1378
1379error:
1380 amdgpu_vm_invalidate_pds(adev, vm);
1381 return r;
1382}
1383
1384
1385
1386
1387
1388
1389static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1390 struct amdgpu_bo_vm *pt, unsigned int level,
1391 uint64_t pe, uint64_t addr,
1392 unsigned int count, uint32_t incr,
1393 uint64_t flags)
1394
1395{
1396 if (level != AMDGPU_VM_PTB) {
1397 flags |= AMDGPU_PDE_PTE;
1398 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1399
1400 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1401 !(flags & AMDGPU_PTE_VALID) &&
1402 !(flags & AMDGPU_PTE_PRT)) {
1403
1404
1405 flags |= AMDGPU_PTE_EXECUTABLE;
1406 }
1407
1408 params->vm->update_funcs->update(params, pt, pe, addr, count, incr,
1409 flags);
1410}
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1425 uint64_t start, uint64_t end, uint64_t flags,
1426 unsigned int *frag, uint64_t *frag_end)
1427{
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449 unsigned max_frag;
1450
1451 if (params->adev->asic_type < CHIP_VEGA10)
1452 max_frag = params->adev->vm_manager.fragment_size;
1453 else
1454 max_frag = 31;
1455
1456
1457 if (params->pages_addr) {
1458 *frag = 0;
1459 *frag_end = end;
1460 return;
1461 }
1462
1463
1464 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1465 if (*frag >= max_frag) {
1466 *frag = max_frag;
1467 *frag_end = end & ~((1ULL << max_frag) - 1);
1468 } else {
1469 *frag_end = start + (1 << *frag);
1470 }
1471}
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1488 uint64_t start, uint64_t end,
1489 uint64_t dst, uint64_t flags)
1490{
1491 struct amdgpu_device *adev = params->adev;
1492 struct amdgpu_vm_pt_cursor cursor;
1493 uint64_t frag_start = start, frag_end;
1494 unsigned int frag;
1495 int r;
1496
1497
1498 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1499
1500
1501 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1502 while (cursor.pfn < end) {
1503 unsigned shift, parent_shift, mask;
1504 uint64_t incr, entry_end, pe_start;
1505 struct amdgpu_bo *pt;
1506
1507 if (!params->unlocked) {
1508
1509
1510
1511 r = amdgpu_vm_alloc_pts(params->adev, params->vm,
1512 &cursor, params->immediate);
1513 if (r)
1514 return r;
1515 }
1516
1517 shift = amdgpu_vm_level_shift(adev, cursor.level);
1518 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1519 if (params->unlocked) {
1520
1521 if (amdgpu_vm_pt_descendant(adev, &cursor))
1522 continue;
1523 } else if (adev->asic_type < CHIP_VEGA10 &&
1524 (flags & AMDGPU_PTE_VALID)) {
1525
1526 if (cursor.level != AMDGPU_VM_PTB) {
1527 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1528 return -ENOENT;
1529 continue;
1530 }
1531 } else if (frag < shift) {
1532
1533
1534
1535
1536 if (amdgpu_vm_pt_descendant(adev, &cursor))
1537 continue;
1538 } else if (frag >= parent_shift) {
1539
1540
1541
1542 if (!amdgpu_vm_pt_ancestor(&cursor))
1543 return -EINVAL;
1544 continue;
1545 }
1546
1547 pt = cursor.entry->bo;
1548 if (!pt) {
1549
1550 if (flags & AMDGPU_PTE_VALID)
1551 return -ENOENT;
1552
1553
1554
1555
1556 if (!amdgpu_vm_pt_ancestor(&cursor))
1557 return -EINVAL;
1558
1559 pt = cursor.entry->bo;
1560 shift = parent_shift;
1561 frag_end = max(frag_end, ALIGN(frag_start + 1,
1562 1ULL << shift));
1563 }
1564
1565
1566 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1567 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1568 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1569 entry_end = ((uint64_t)mask + 1) << shift;
1570 entry_end += cursor.pfn & ~(entry_end - 1);
1571 entry_end = min(entry_end, end);
1572
1573 do {
1574 struct amdgpu_vm *vm = params->vm;
1575 uint64_t upd_end = min(entry_end, frag_end);
1576 unsigned nptes = (upd_end - frag_start) >> shift;
1577 uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag);
1578
1579
1580
1581
1582 nptes = max(nptes, 1u);
1583
1584 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
1585 nptes, dst, incr, upd_flags,
1586 vm->task_info.pid,
1587 vm->immediate.fence_context);
1588 amdgpu_vm_update_flags(params, to_amdgpu_bo_vm(pt),
1589 cursor.level, pe_start, dst,
1590 nptes, incr, upd_flags);
1591
1592 pe_start += nptes * 8;
1593 dst += nptes * incr;
1594
1595 frag_start = upd_end;
1596 if (frag_start >= frag_end) {
1597
1598 amdgpu_vm_fragment(params, frag_start, end,
1599 flags, &frag, &frag_end);
1600 if (frag < shift)
1601 break;
1602 }
1603 } while (frag_start < entry_end);
1604
1605 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1606
1607
1608
1609
1610
1611
1612 while (cursor.pfn < frag_start) {
1613
1614 if (cursor.entry->bo) {
1615 params->table_freed = true;
1616 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1617 }
1618 amdgpu_vm_pt_next(adev, &cursor);
1619 }
1620
1621 } else if (frag >= shift) {
1622
1623 amdgpu_vm_pt_next(adev, &cursor);
1624 }
1625 }
1626
1627 return 0;
1628}
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1654 struct amdgpu_device *bo_adev,
1655 struct amdgpu_vm *vm, bool immediate,
1656 bool unlocked, struct dma_resv *resv,
1657 uint64_t start, uint64_t last,
1658 uint64_t flags, uint64_t offset,
1659 struct ttm_resource *res,
1660 dma_addr_t *pages_addr,
1661 struct dma_fence **fence,
1662 bool *table_freed)
1663{
1664 struct amdgpu_vm_update_params params;
1665 struct amdgpu_res_cursor cursor;
1666 enum amdgpu_sync_mode sync_mode;
1667 int r, idx;
1668
1669 if (!drm_dev_enter(&adev->ddev, &idx))
1670 return -ENODEV;
1671
1672 memset(¶ms, 0, sizeof(params));
1673 params.adev = adev;
1674 params.vm = vm;
1675 params.immediate = immediate;
1676 params.pages_addr = pages_addr;
1677 params.unlocked = unlocked;
1678
1679
1680
1681
1682 if (!(flags & AMDGPU_PTE_VALID))
1683 sync_mode = AMDGPU_SYNC_EQ_OWNER;
1684 else
1685 sync_mode = AMDGPU_SYNC_EXPLICIT;
1686
1687 amdgpu_vm_eviction_lock(vm);
1688 if (vm->evicting) {
1689 r = -EBUSY;
1690 goto error_unlock;
1691 }
1692
1693 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1694 struct dma_fence *tmp = dma_fence_get_stub();
1695
1696 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
1697 swap(vm->last_unlocked, tmp);
1698 dma_fence_put(tmp);
1699 }
1700
1701 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1702 if (r)
1703 goto error_unlock;
1704
1705 amdgpu_res_first(pages_addr ? NULL : res, offset,
1706 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
1707 while (cursor.remaining) {
1708 uint64_t tmp, num_entries, addr;
1709
1710 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1711 if (pages_addr) {
1712 bool contiguous = true;
1713
1714 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1715 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1716 uint64_t count;
1717
1718 contiguous = pages_addr[pfn + 1] ==
1719 pages_addr[pfn] + PAGE_SIZE;
1720
1721 tmp = num_entries /
1722 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1723 for (count = 2; count < tmp; ++count) {
1724 uint64_t idx = pfn + count;
1725
1726 if (contiguous != (pages_addr[idx] ==
1727 pages_addr[idx - 1] + PAGE_SIZE))
1728 break;
1729 }
1730 num_entries = count *
1731 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1732 }
1733
1734 if (!contiguous) {
1735 addr = cursor.start;
1736 params.pages_addr = pages_addr;
1737 } else {
1738 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1739 params.pages_addr = NULL;
1740 }
1741
1742 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1743 addr = bo_adev->vm_manager.vram_base_offset +
1744 cursor.start;
1745 } else {
1746 addr = 0;
1747 }
1748
1749 tmp = start + num_entries;
1750 r = amdgpu_vm_update_ptes(¶ms, start, tmp, addr, flags);
1751 if (r)
1752 goto error_unlock;
1753
1754 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1755 start = tmp;
1756 }
1757
1758 r = vm->update_funcs->commit(¶ms, fence);
1759
1760 if (table_freed)
1761 *table_freed = params.table_freed;
1762
1763error_unlock:
1764 amdgpu_vm_eviction_unlock(vm);
1765 drm_dev_exit(idx);
1766 return r;
1767}
1768
1769void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
1770 uint64_t *gtt_mem, uint64_t *cpu_mem)
1771{
1772 struct amdgpu_bo_va *bo_va, *tmp;
1773
1774 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
1775 if (!bo_va->base.bo)
1776 continue;
1777 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1778 gtt_mem, cpu_mem);
1779 }
1780 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
1781 if (!bo_va->base.bo)
1782 continue;
1783 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1784 gtt_mem, cpu_mem);
1785 }
1786 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
1787 if (!bo_va->base.bo)
1788 continue;
1789 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1790 gtt_mem, cpu_mem);
1791 }
1792 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1793 if (!bo_va->base.bo)
1794 continue;
1795 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1796 gtt_mem, cpu_mem);
1797 }
1798 spin_lock(&vm->invalidated_lock);
1799 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
1800 if (!bo_va->base.bo)
1801 continue;
1802 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1803 gtt_mem, cpu_mem);
1804 }
1805 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
1806 if (!bo_va->base.bo)
1807 continue;
1808 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1809 gtt_mem, cpu_mem);
1810 }
1811 spin_unlock(&vm->invalidated_lock);
1812}
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1826 bool clear)
1827{
1828 struct amdgpu_bo *bo = bo_va->base.bo;
1829 struct amdgpu_vm *vm = bo_va->base.vm;
1830 struct amdgpu_bo_va_mapping *mapping;
1831 dma_addr_t *pages_addr = NULL;
1832 struct ttm_resource *mem;
1833 struct dma_fence **last_update;
1834 struct dma_resv *resv;
1835 uint64_t flags;
1836 struct amdgpu_device *bo_adev = adev;
1837 int r;
1838
1839 if (clear || !bo) {
1840 mem = NULL;
1841 resv = vm->root.bo->tbo.base.resv;
1842 } else {
1843 struct drm_gem_object *obj = &bo->tbo.base;
1844
1845 resv = bo->tbo.base.resv;
1846 if (obj->import_attach && bo_va->is_xgmi) {
1847 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1848 struct drm_gem_object *gobj = dma_buf->priv;
1849 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1850
1851 if (abo->tbo.resource->mem_type == TTM_PL_VRAM)
1852 bo = gem_to_amdgpu_bo(gobj);
1853 }
1854 mem = bo->tbo.resource;
1855 if (mem->mem_type == TTM_PL_TT ||
1856 mem->mem_type == AMDGPU_PL_PREEMPT)
1857 pages_addr = bo->tbo.ttm->dma_address;
1858 }
1859
1860 if (bo) {
1861 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1862
1863 if (amdgpu_bo_encrypted(bo))
1864 flags |= AMDGPU_PTE_TMZ;
1865
1866 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1867 } else {
1868 flags = 0x0;
1869 }
1870
1871 if (clear || (bo && bo->tbo.base.resv ==
1872 vm->root.bo->tbo.base.resv))
1873 last_update = &vm->last_update;
1874 else
1875 last_update = &bo_va->last_pt_update;
1876
1877 if (!clear && bo_va->base.moved) {
1878 bo_va->base.moved = false;
1879 list_splice_init(&bo_va->valids, &bo_va->invalids);
1880
1881 } else if (bo_va->cleared != clear) {
1882 list_splice_init(&bo_va->valids, &bo_va->invalids);
1883 }
1884
1885 list_for_each_entry(mapping, &bo_va->invalids, list) {
1886 uint64_t update_flags = flags;
1887
1888
1889
1890
1891 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1892 update_flags &= ~AMDGPU_PTE_READABLE;
1893 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1894 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1895
1896
1897 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1898
1899 trace_amdgpu_vm_bo_update(mapping);
1900
1901 r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
1902 resv, mapping->start,
1903 mapping->last, update_flags,
1904 mapping->offset, mem,
1905 pages_addr, last_update, NULL);
1906 if (r)
1907 return r;
1908 }
1909
1910
1911
1912
1913
1914 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1915 uint32_t mem_type = bo->tbo.resource->mem_type;
1916
1917 if (!(bo->preferred_domains &
1918 amdgpu_mem_type_to_domain(mem_type)))
1919 amdgpu_vm_bo_evicted(&bo_va->base);
1920 else
1921 amdgpu_vm_bo_idle(&bo_va->base);
1922 } else {
1923 amdgpu_vm_bo_done(&bo_va->base);
1924 }
1925
1926 list_splice_init(&bo_va->invalids, &bo_va->valids);
1927 bo_va->cleared = clear;
1928
1929 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1930 list_for_each_entry(mapping, &bo_va->valids, list)
1931 trace_amdgpu_vm_bo_mapping(mapping);
1932 }
1933
1934 return 0;
1935}
1936
1937
1938
1939
1940
1941
1942static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1943{
1944 unsigned long flags;
1945 bool enable;
1946
1947 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1948 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1949 adev->gmc.gmc_funcs->set_prt(adev, enable);
1950 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1951}
1952
1953
1954
1955
1956
1957
1958static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1959{
1960 if (!adev->gmc.gmc_funcs->set_prt)
1961 return;
1962
1963 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1964 amdgpu_vm_update_prt_state(adev);
1965}
1966
1967
1968
1969
1970
1971
1972static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1973{
1974 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1975 amdgpu_vm_update_prt_state(adev);
1976}
1977
1978
1979
1980
1981
1982
1983
1984static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1985{
1986 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1987
1988 amdgpu_vm_prt_put(cb->adev);
1989 kfree(cb);
1990}
1991
1992
1993
1994
1995
1996
1997
1998static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1999 struct dma_fence *fence)
2000{
2001 struct amdgpu_prt_cb *cb;
2002
2003 if (!adev->gmc.gmc_funcs->set_prt)
2004 return;
2005
2006 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
2007 if (!cb) {
2008
2009 if (fence)
2010 dma_fence_wait(fence, false);
2011
2012 amdgpu_vm_prt_put(adev);
2013 } else {
2014 cb->adev = adev;
2015 if (!fence || dma_fence_add_callback(fence, &cb->cb,
2016 amdgpu_vm_prt_cb))
2017 amdgpu_vm_prt_cb(fence, &cb->cb);
2018 }
2019}
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
2032 struct amdgpu_vm *vm,
2033 struct amdgpu_bo_va_mapping *mapping,
2034 struct dma_fence *fence)
2035{
2036 if (mapping->flags & AMDGPU_PTE_PRT)
2037 amdgpu_vm_add_prt_cb(adev, fence);
2038 kfree(mapping);
2039}
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2050{
2051 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2052 struct dma_fence *excl, **shared;
2053 unsigned i, shared_count;
2054 int r;
2055
2056 r = dma_resv_get_fences(resv, &excl, &shared_count, &shared);
2057 if (r) {
2058
2059
2060
2061 dma_resv_wait_timeout(resv, true, false,
2062 MAX_SCHEDULE_TIMEOUT);
2063 return;
2064 }
2065
2066
2067 amdgpu_vm_prt_get(adev);
2068 amdgpu_vm_add_prt_cb(adev, excl);
2069
2070 for (i = 0; i < shared_count; ++i) {
2071 amdgpu_vm_prt_get(adev);
2072 amdgpu_vm_add_prt_cb(adev, shared[i]);
2073 }
2074
2075 kfree(shared);
2076}
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2094 struct amdgpu_vm *vm,
2095 struct dma_fence **fence)
2096{
2097 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2098 struct amdgpu_bo_va_mapping *mapping;
2099 uint64_t init_pte_value = 0;
2100 struct dma_fence *f = NULL;
2101 int r;
2102
2103 while (!list_empty(&vm->freed)) {
2104 mapping = list_first_entry(&vm->freed,
2105 struct amdgpu_bo_va_mapping, list);
2106 list_del(&mapping->list);
2107
2108 if (vm->pte_support_ats &&
2109 mapping->start < AMDGPU_GMC_HOLE_START)
2110 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2111
2112 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
2113 resv, mapping->start,
2114 mapping->last, init_pte_value,
2115 0, NULL, NULL, &f, NULL);
2116 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2117 if (r) {
2118 dma_fence_put(f);
2119 return r;
2120 }
2121 }
2122
2123 if (fence && f) {
2124 dma_fence_put(*fence);
2125 *fence = f;
2126 } else {
2127 dma_fence_put(f);
2128 }
2129
2130 return 0;
2131
2132}
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2148 struct amdgpu_vm *vm)
2149{
2150 struct amdgpu_bo_va *bo_va, *tmp;
2151 struct dma_resv *resv;
2152 bool clear;
2153 int r;
2154
2155 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2156
2157 r = amdgpu_vm_bo_update(adev, bo_va, false);
2158 if (r)
2159 return r;
2160 }
2161
2162 spin_lock(&vm->invalidated_lock);
2163 while (!list_empty(&vm->invalidated)) {
2164 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2165 base.vm_status);
2166 resv = bo_va->base.bo->tbo.base.resv;
2167 spin_unlock(&vm->invalidated_lock);
2168
2169
2170 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
2171 clear = false;
2172
2173 else
2174 clear = true;
2175
2176 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2177 if (r)
2178 return r;
2179
2180 if (!clear)
2181 dma_resv_unlock(resv);
2182 spin_lock(&vm->invalidated_lock);
2183 }
2184 spin_unlock(&vm->invalidated_lock);
2185
2186 return 0;
2187}
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2205 struct amdgpu_vm *vm,
2206 struct amdgpu_bo *bo)
2207{
2208 struct amdgpu_bo_va *bo_va;
2209
2210 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2211 if (bo_va == NULL) {
2212 return NULL;
2213 }
2214 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2215
2216 bo_va->ref_count = 1;
2217 INIT_LIST_HEAD(&bo_va->valids);
2218 INIT_LIST_HEAD(&bo_va->invalids);
2219
2220 if (!bo)
2221 return bo_va;
2222
2223 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
2224 bo_va->is_xgmi = true;
2225
2226 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
2227 }
2228
2229 return bo_va;
2230}
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2243 struct amdgpu_bo_va *bo_va,
2244 struct amdgpu_bo_va_mapping *mapping)
2245{
2246 struct amdgpu_vm *vm = bo_va->base.vm;
2247 struct amdgpu_bo *bo = bo_va->base.bo;
2248
2249 mapping->bo_va = bo_va;
2250 list_add(&mapping->list, &bo_va->invalids);
2251 amdgpu_vm_it_insert(mapping, &vm->va);
2252
2253 if (mapping->flags & AMDGPU_PTE_PRT)
2254 amdgpu_vm_prt_get(adev);
2255
2256 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
2257 !bo_va->base.moved) {
2258 list_move(&bo_va->base.vm_status, &vm->moved);
2259 }
2260 trace_amdgpu_vm_bo_map(bo_va, mapping);
2261}
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2281 struct amdgpu_bo_va *bo_va,
2282 uint64_t saddr, uint64_t offset,
2283 uint64_t size, uint64_t flags)
2284{
2285 struct amdgpu_bo_va_mapping *mapping, *tmp;
2286 struct amdgpu_bo *bo = bo_va->base.bo;
2287 struct amdgpu_vm *vm = bo_va->base.vm;
2288 uint64_t eaddr;
2289
2290
2291 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2292 size == 0 || size & ~PAGE_MASK)
2293 return -EINVAL;
2294
2295
2296 eaddr = saddr + size - 1;
2297 if (saddr >= eaddr ||
2298 (bo && offset + size > amdgpu_bo_size(bo)) ||
2299 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2300 return -EINVAL;
2301
2302 saddr /= AMDGPU_GPU_PAGE_SIZE;
2303 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2304
2305 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2306 if (tmp) {
2307
2308 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2309 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2310 tmp->start, tmp->last + 1);
2311 return -EINVAL;
2312 }
2313
2314 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2315 if (!mapping)
2316 return -ENOMEM;
2317
2318 mapping->start = saddr;
2319 mapping->last = eaddr;
2320 mapping->offset = offset;
2321 mapping->flags = flags;
2322
2323 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2324
2325 return 0;
2326}
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2347 struct amdgpu_bo_va *bo_va,
2348 uint64_t saddr, uint64_t offset,
2349 uint64_t size, uint64_t flags)
2350{
2351 struct amdgpu_bo_va_mapping *mapping;
2352 struct amdgpu_bo *bo = bo_va->base.bo;
2353 uint64_t eaddr;
2354 int r;
2355
2356
2357 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2358 size == 0 || size & ~PAGE_MASK)
2359 return -EINVAL;
2360
2361
2362 eaddr = saddr + size - 1;
2363 if (saddr >= eaddr ||
2364 (bo && offset + size > amdgpu_bo_size(bo)) ||
2365 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2366 return -EINVAL;
2367
2368
2369 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2370 if (!mapping)
2371 return -ENOMEM;
2372
2373 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2374 if (r) {
2375 kfree(mapping);
2376 return r;
2377 }
2378
2379 saddr /= AMDGPU_GPU_PAGE_SIZE;
2380 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2381
2382 mapping->start = saddr;
2383 mapping->last = eaddr;
2384 mapping->offset = offset;
2385 mapping->flags = flags;
2386
2387 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2388
2389 return 0;
2390}
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2407 struct amdgpu_bo_va *bo_va,
2408 uint64_t saddr)
2409{
2410 struct amdgpu_bo_va_mapping *mapping;
2411 struct amdgpu_vm *vm = bo_va->base.vm;
2412 bool valid = true;
2413
2414 saddr /= AMDGPU_GPU_PAGE_SIZE;
2415
2416 list_for_each_entry(mapping, &bo_va->valids, list) {
2417 if (mapping->start == saddr)
2418 break;
2419 }
2420
2421 if (&mapping->list == &bo_va->valids) {
2422 valid = false;
2423
2424 list_for_each_entry(mapping, &bo_va->invalids, list) {
2425 if (mapping->start == saddr)
2426 break;
2427 }
2428
2429 if (&mapping->list == &bo_va->invalids)
2430 return -ENOENT;
2431 }
2432
2433 list_del(&mapping->list);
2434 amdgpu_vm_it_remove(mapping, &vm->va);
2435 mapping->bo_va = NULL;
2436 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2437
2438 if (valid)
2439 list_add(&mapping->list, &vm->freed);
2440 else
2441 amdgpu_vm_free_mapping(adev, vm, mapping,
2442 bo_va->last_pt_update);
2443
2444 return 0;
2445}
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2461 struct amdgpu_vm *vm,
2462 uint64_t saddr, uint64_t size)
2463{
2464 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2465 LIST_HEAD(removed);
2466 uint64_t eaddr;
2467
2468 eaddr = saddr + size - 1;
2469 saddr /= AMDGPU_GPU_PAGE_SIZE;
2470 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2471
2472
2473 before = kzalloc(sizeof(*before), GFP_KERNEL);
2474 if (!before)
2475 return -ENOMEM;
2476 INIT_LIST_HEAD(&before->list);
2477
2478 after = kzalloc(sizeof(*after), GFP_KERNEL);
2479 if (!after) {
2480 kfree(before);
2481 return -ENOMEM;
2482 }
2483 INIT_LIST_HEAD(&after->list);
2484
2485
2486 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2487 while (tmp) {
2488
2489 if (tmp->start < saddr) {
2490 before->start = tmp->start;
2491 before->last = saddr - 1;
2492 before->offset = tmp->offset;
2493 before->flags = tmp->flags;
2494 before->bo_va = tmp->bo_va;
2495 list_add(&before->list, &tmp->bo_va->invalids);
2496 }
2497
2498
2499 if (tmp->last > eaddr) {
2500 after->start = eaddr + 1;
2501 after->last = tmp->last;
2502 after->offset = tmp->offset;
2503 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
2504 after->flags = tmp->flags;
2505 after->bo_va = tmp->bo_va;
2506 list_add(&after->list, &tmp->bo_va->invalids);
2507 }
2508
2509 list_del(&tmp->list);
2510 list_add(&tmp->list, &removed);
2511
2512 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2513 }
2514
2515
2516 list_for_each_entry_safe(tmp, next, &removed, list) {
2517 amdgpu_vm_it_remove(tmp, &vm->va);
2518 list_del(&tmp->list);
2519
2520 if (tmp->start < saddr)
2521 tmp->start = saddr;
2522 if (tmp->last > eaddr)
2523 tmp->last = eaddr;
2524
2525 tmp->bo_va = NULL;
2526 list_add(&tmp->list, &vm->freed);
2527 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2528 }
2529
2530
2531 if (!list_empty(&before->list)) {
2532 amdgpu_vm_it_insert(before, &vm->va);
2533 if (before->flags & AMDGPU_PTE_PRT)
2534 amdgpu_vm_prt_get(adev);
2535 } else {
2536 kfree(before);
2537 }
2538
2539
2540 if (!list_empty(&after->list)) {
2541 amdgpu_vm_it_insert(after, &vm->va);
2542 if (after->flags & AMDGPU_PTE_PRT)
2543 amdgpu_vm_prt_get(adev);
2544 } else {
2545 kfree(after);
2546 }
2547
2548 return 0;
2549}
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2564 uint64_t addr)
2565{
2566 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2567}
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2578{
2579 struct amdgpu_bo_va_mapping *mapping;
2580
2581 if (!trace_amdgpu_vm_bo_cs_enabled())
2582 return;
2583
2584 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2585 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2586 if (mapping->bo_va && mapping->bo_va->base.bo) {
2587 struct amdgpu_bo *bo;
2588
2589 bo = mapping->bo_va->base.bo;
2590 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2591 ticket)
2592 continue;
2593 }
2594
2595 trace_amdgpu_vm_bo_cs(mapping);
2596 }
2597}
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2610 struct amdgpu_bo_va *bo_va)
2611{
2612 struct amdgpu_bo_va_mapping *mapping, *next;
2613 struct amdgpu_bo *bo = bo_va->base.bo;
2614 struct amdgpu_vm *vm = bo_va->base.vm;
2615 struct amdgpu_vm_bo_base **base;
2616
2617 if (bo) {
2618 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2619 vm->bulk_moveable = false;
2620
2621 for (base = &bo_va->base.bo->vm_bo; *base;
2622 base = &(*base)->next) {
2623 if (*base != &bo_va->base)
2624 continue;
2625
2626 *base = bo_va->base.next;
2627 break;
2628 }
2629 }
2630
2631 spin_lock(&vm->invalidated_lock);
2632 list_del(&bo_va->base.vm_status);
2633 spin_unlock(&vm->invalidated_lock);
2634
2635 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2636 list_del(&mapping->list);
2637 amdgpu_vm_it_remove(mapping, &vm->va);
2638 mapping->bo_va = NULL;
2639 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2640 list_add(&mapping->list, &vm->freed);
2641 }
2642 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2643 list_del(&mapping->list);
2644 amdgpu_vm_it_remove(mapping, &vm->va);
2645 amdgpu_vm_free_mapping(adev, vm, mapping,
2646 bo_va->last_pt_update);
2647 }
2648
2649 dma_fence_put(bo_va->last_pt_update);
2650
2651 if (bo && bo_va->is_xgmi)
2652 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2653
2654 kfree(bo_va);
2655}
2656
2657
2658
2659
2660
2661
2662
2663
2664bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2665{
2666 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2667
2668
2669 if (!bo_base || !bo_base->vm)
2670 return true;
2671
2672
2673 if (!dma_resv_test_signaled(bo->tbo.base.resv, true))
2674 return false;
2675
2676
2677 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2678 return false;
2679
2680
2681 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2682 amdgpu_vm_eviction_unlock(bo_base->vm);
2683 return false;
2684 }
2685
2686 bo_base->vm->evicting = true;
2687 amdgpu_vm_eviction_unlock(bo_base->vm);
2688 return true;
2689}
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2701 struct amdgpu_bo *bo, bool evicted)
2702{
2703 struct amdgpu_vm_bo_base *bo_base;
2704
2705
2706 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2707 bo = bo->parent;
2708
2709 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2710 struct amdgpu_vm *vm = bo_base->vm;
2711
2712 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2713 amdgpu_vm_bo_evicted(bo_base);
2714 continue;
2715 }
2716
2717 if (bo_base->moved)
2718 continue;
2719 bo_base->moved = true;
2720
2721 if (bo->tbo.type == ttm_bo_type_kernel)
2722 amdgpu_vm_bo_relocated(bo_base);
2723 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2724 amdgpu_vm_bo_moved(bo_base);
2725 else
2726 amdgpu_vm_bo_invalidated(bo_base);
2727 }
2728}
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2739{
2740
2741 unsigned bits = ilog2(vm_size) + 18;
2742
2743
2744
2745 if (vm_size <= 8)
2746 return (bits - 9);
2747 else
2748 return ((bits + 3) / 2);
2749}
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2762 uint32_t fragment_size_default, unsigned max_level,
2763 unsigned max_bits)
2764{
2765 unsigned int max_size = 1 << (max_bits - 30);
2766 unsigned int vm_size;
2767 uint64_t tmp;
2768
2769
2770 if (amdgpu_vm_size != -1) {
2771 vm_size = amdgpu_vm_size;
2772 if (vm_size > max_size) {
2773 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2774 amdgpu_vm_size, max_size);
2775 vm_size = max_size;
2776 }
2777 } else {
2778 struct sysinfo si;
2779 unsigned int phys_ram_gb;
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796 si_meminfo(&si);
2797 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2798 (1 << 30) - 1) >> 30;
2799 vm_size = roundup_pow_of_two(
2800 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2801 }
2802
2803 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2804
2805 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2806 if (amdgpu_vm_block_size != -1)
2807 tmp >>= amdgpu_vm_block_size - 9;
2808 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2809 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2810 switch (adev->vm_manager.num_level) {
2811 case 3:
2812 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2813 break;
2814 case 2:
2815 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2816 break;
2817 case 1:
2818 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2819 break;
2820 default:
2821 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2822 }
2823
2824 if (amdgpu_vm_block_size != -1)
2825 adev->vm_manager.block_size =
2826 min((unsigned)amdgpu_vm_block_size, max_bits
2827 - AMDGPU_GPU_PAGE_SHIFT
2828 - 9 * adev->vm_manager.num_level);
2829 else if (adev->vm_manager.num_level > 1)
2830 adev->vm_manager.block_size = 9;
2831 else
2832 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2833
2834 if (amdgpu_vm_fragment_size == -1)
2835 adev->vm_manager.fragment_size = fragment_size_default;
2836 else
2837 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2838
2839 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2840 vm_size, adev->vm_manager.num_level + 1,
2841 adev->vm_manager.block_size,
2842 adev->vm_manager.fragment_size);
2843}
2844
2845
2846
2847
2848
2849
2850
2851long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2852{
2853 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, true,
2854 true, timeout);
2855 if (timeout <= 0)
2856 return timeout;
2857
2858 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2859}
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
2874{
2875 struct amdgpu_bo *root_bo;
2876 struct amdgpu_bo_vm *root;
2877 int r, i;
2878
2879 vm->va = RB_ROOT_CACHED;
2880 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2881 vm->reserved_vmid[i] = NULL;
2882 INIT_LIST_HEAD(&vm->evicted);
2883 INIT_LIST_HEAD(&vm->relocated);
2884 INIT_LIST_HEAD(&vm->moved);
2885 INIT_LIST_HEAD(&vm->idle);
2886 INIT_LIST_HEAD(&vm->invalidated);
2887 spin_lock_init(&vm->invalidated_lock);
2888 INIT_LIST_HEAD(&vm->freed);
2889 INIT_LIST_HEAD(&vm->done);
2890
2891
2892 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2893 adev->vm_manager.vm_pte_scheds,
2894 adev->vm_manager.vm_pte_num_scheds, NULL);
2895 if (r)
2896 return r;
2897
2898 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2899 adev->vm_manager.vm_pte_scheds,
2900 adev->vm_manager.vm_pte_num_scheds, NULL);
2901 if (r)
2902 goto error_free_immediate;
2903
2904 vm->pte_support_ats = false;
2905 vm->is_compute_context = false;
2906
2907 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2908 AMDGPU_VM_USE_CPU_FOR_GFX);
2909
2910 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2911 vm->use_cpu_for_update ? "CPU" : "SDMA");
2912 WARN_ONCE((vm->use_cpu_for_update &&
2913 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2914 "CPU update of VM recommended only for large BAR system\n");
2915
2916 if (vm->use_cpu_for_update)
2917 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2918 else
2919 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2920 vm->last_update = NULL;
2921 vm->last_unlocked = dma_fence_get_stub();
2922
2923 mutex_init(&vm->eviction_lock);
2924 vm->evicting = false;
2925
2926 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2927 false, &root);
2928 if (r)
2929 goto error_free_delayed;
2930 root_bo = &root->bo;
2931 r = amdgpu_bo_reserve(root_bo, true);
2932 if (r)
2933 goto error_free_root;
2934
2935 r = dma_resv_reserve_shared(root_bo->tbo.base.resv, 1);
2936 if (r)
2937 goto error_unreserve;
2938
2939 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2940
2941 r = amdgpu_vm_clear_bo(adev, vm, root, false);
2942 if (r)
2943 goto error_unreserve;
2944
2945 amdgpu_bo_unreserve(vm->root.bo);
2946
2947 if (pasid) {
2948 unsigned long flags;
2949
2950 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2951 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2952 GFP_ATOMIC);
2953 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2954 if (r < 0)
2955 goto error_free_root;
2956
2957 vm->pasid = pasid;
2958 }
2959
2960 INIT_KFIFO(vm->faults);
2961
2962 return 0;
2963
2964error_unreserve:
2965 amdgpu_bo_unreserve(vm->root.bo);
2966
2967error_free_root:
2968 amdgpu_bo_unref(&root->shadow);
2969 amdgpu_bo_unref(&root_bo);
2970 vm->root.bo = NULL;
2971
2972error_free_delayed:
2973 dma_fence_put(vm->last_unlocked);
2974 drm_sched_entity_destroy(&vm->delayed);
2975
2976error_free_immediate:
2977 drm_sched_entity_destroy(&vm->immediate);
2978
2979 return r;
2980}
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
2996 struct amdgpu_vm *vm)
2997{
2998 enum amdgpu_vm_level root = adev->vm_manager.root_level;
2999 unsigned int entries = amdgpu_vm_num_entries(adev, root);
3000 unsigned int i = 0;
3001
3002 for (i = 0; i < entries; i++) {
3003 if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo)
3004 return -EINVAL;
3005 }
3006
3007 return 0;
3008}
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
3032 u32 pasid)
3033{
3034 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3035 int r;
3036
3037 r = amdgpu_bo_reserve(vm->root.bo, true);
3038 if (r)
3039 return r;
3040
3041
3042 r = amdgpu_vm_check_clean_reserved(adev, vm);
3043 if (r)
3044 goto unreserve_bo;
3045
3046 if (pasid) {
3047 unsigned long flags;
3048
3049 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3050 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3051 GFP_ATOMIC);
3052 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3053
3054 if (r == -ENOSPC)
3055 goto unreserve_bo;
3056 r = 0;
3057 }
3058
3059
3060
3061
3062 if (pte_support_ats != vm->pte_support_ats) {
3063 vm->pte_support_ats = pte_support_ats;
3064 r = amdgpu_vm_clear_bo(adev, vm,
3065 to_amdgpu_bo_vm(vm->root.bo),
3066 false);
3067 if (r)
3068 goto free_idr;
3069 }
3070
3071
3072 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3073 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3074 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3075 vm->use_cpu_for_update ? "CPU" : "SDMA");
3076 WARN_ONCE((vm->use_cpu_for_update &&
3077 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3078 "CPU update of VM recommended only for large BAR system\n");
3079
3080 if (vm->use_cpu_for_update) {
3081
3082 r = amdgpu_bo_sync_wait(vm->root.bo,
3083 AMDGPU_FENCE_OWNER_UNDEFINED, true);
3084 if (r)
3085 goto free_idr;
3086
3087 vm->update_funcs = &amdgpu_vm_cpu_funcs;
3088 } else {
3089 vm->update_funcs = &amdgpu_vm_sdma_funcs;
3090 }
3091 dma_fence_put(vm->last_update);
3092 vm->last_update = NULL;
3093 vm->is_compute_context = true;
3094
3095 if (vm->pasid) {
3096 unsigned long flags;
3097
3098 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3099 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3100 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3101
3102
3103
3104
3105 amdgpu_pasid_free(vm->pasid);
3106 vm->pasid = 0;
3107 }
3108
3109
3110 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
3111
3112 if (pasid)
3113 vm->pasid = pasid;
3114
3115 goto unreserve_bo;
3116
3117free_idr:
3118 if (pasid) {
3119 unsigned long flags;
3120
3121 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3122 idr_remove(&adev->vm_manager.pasid_idr, pasid);
3123 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3124 }
3125unreserve_bo:
3126 amdgpu_bo_unreserve(vm->root.bo);
3127 return r;
3128}
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3139{
3140 if (vm->pasid) {
3141 unsigned long flags;
3142
3143 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3144 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3145 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3146 }
3147 vm->pasid = 0;
3148 vm->is_compute_context = false;
3149}
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3161{
3162 struct amdgpu_bo_va_mapping *mapping, *tmp;
3163 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3164 struct amdgpu_bo *root;
3165 int i;
3166
3167 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3168
3169 root = amdgpu_bo_ref(vm->root.bo);
3170 amdgpu_bo_reserve(root, true);
3171 if (vm->pasid) {
3172 unsigned long flags;
3173
3174 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3175 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3176 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3177 vm->pasid = 0;
3178 }
3179
3180 dma_fence_wait(vm->last_unlocked, false);
3181 dma_fence_put(vm->last_unlocked);
3182
3183 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3184 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3185 amdgpu_vm_prt_fini(adev, vm);
3186 prt_fini_needed = false;
3187 }
3188
3189 list_del(&mapping->list);
3190 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3191 }
3192
3193 amdgpu_vm_free_pts(adev, vm, NULL);
3194 amdgpu_bo_unreserve(root);
3195 amdgpu_bo_unref(&root);
3196 WARN_ON(vm->root.bo);
3197
3198 drm_sched_entity_destroy(&vm->immediate);
3199 drm_sched_entity_destroy(&vm->delayed);
3200
3201 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3202 dev_err(adev->dev, "still active bo inside vm\n");
3203 }
3204 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3205 &vm->va.rb_root, rb) {
3206
3207
3208
3209 list_del(&mapping->list);
3210 kfree(mapping);
3211 }
3212
3213 dma_fence_put(vm->last_update);
3214 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3215 amdgpu_vmid_free_reserved(adev, vm, i);
3216}
3217
3218
3219
3220
3221
3222
3223
3224
3225void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3226{
3227 unsigned i;
3228
3229
3230
3231
3232 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
3233 adev->asic_type == CHIP_NAVI10 ||
3234 adev->asic_type == CHIP_NAVI14);
3235 amdgpu_vmid_mgr_init(adev);
3236
3237 adev->vm_manager.fence_context =
3238 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3239 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3240 adev->vm_manager.seqno[i] = 0;
3241
3242 spin_lock_init(&adev->vm_manager.prt_lock);
3243 atomic_set(&adev->vm_manager.num_prt_users, 0);
3244
3245
3246
3247
3248#ifdef CONFIG_X86_64
3249 if (amdgpu_vm_update_mode == -1) {
3250 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3251 adev->vm_manager.vm_update_mode =
3252 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3253 else
3254 adev->vm_manager.vm_update_mode = 0;
3255 } else
3256 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3257#else
3258 adev->vm_manager.vm_update_mode = 0;
3259#endif
3260
3261 idr_init(&adev->vm_manager.pasid_idr);
3262 spin_lock_init(&adev->vm_manager.pasid_lock);
3263}
3264
3265
3266
3267
3268
3269
3270
3271
3272void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3273{
3274 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3275 idr_destroy(&adev->vm_manager.pasid_idr);
3276
3277 amdgpu_vmid_mgr_fini(adev);
3278}
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3291{
3292 union drm_amdgpu_vm *args = data;
3293 struct amdgpu_device *adev = drm_to_adev(dev);
3294 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3295 long timeout = msecs_to_jiffies(2000);
3296 int r;
3297
3298 switch (args->in.op) {
3299 case AMDGPU_VM_OP_RESERVE_VMID:
3300
3301 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
3302 AMDGPU_GFXHUB_0);
3303 if (r)
3304 return r;
3305 break;
3306 case AMDGPU_VM_OP_UNRESERVE_VMID:
3307 if (amdgpu_sriov_runtime(adev))
3308 timeout = 8 * timeout;
3309
3310
3311
3312
3313 r = amdgpu_bo_reserve(fpriv->vm.root.bo, true);
3314 if (r)
3315 return r;
3316
3317 r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3318 if (r < 0)
3319 return r;
3320
3321 amdgpu_bo_unreserve(fpriv->vm.root.bo);
3322 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3323 break;
3324 default:
3325 return -EINVAL;
3326 }
3327
3328 return 0;
3329}
3330
3331
3332
3333
3334
3335
3336
3337
3338void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
3339 struct amdgpu_task_info *task_info)
3340{
3341 struct amdgpu_vm *vm;
3342 unsigned long flags;
3343
3344 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3345
3346 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3347 if (vm)
3348 *task_info = vm->task_info;
3349
3350 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3351}
3352
3353
3354
3355
3356
3357
3358void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3359{
3360 if (vm->task_info.pid)
3361 return;
3362
3363 vm->task_info.pid = current->pid;
3364 get_task_comm(vm->task_info.task_name, current);
3365
3366 if (current->group_leader->mm != current->mm)
3367 return;
3368
3369 vm->task_info.tgid = current->group_leader->pid;
3370 get_task_comm(vm->task_info.process_name, current->group_leader);
3371}
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
3383 uint64_t addr)
3384{
3385 bool is_compute_context = false;
3386 struct amdgpu_bo *root;
3387 unsigned long irqflags;
3388 uint64_t value, flags;
3389 struct amdgpu_vm *vm;
3390 int r;
3391
3392 spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
3393 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3394 if (vm) {
3395 root = amdgpu_bo_ref(vm->root.bo);
3396 is_compute_context = vm->is_compute_context;
3397 } else {
3398 root = NULL;
3399 }
3400 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
3401
3402 if (!root)
3403 return false;
3404
3405 addr /= AMDGPU_GPU_PAGE_SIZE;
3406
3407 if (is_compute_context &&
3408 !svm_range_restore_pages(adev, pasid, addr)) {
3409 amdgpu_bo_unref(&root);
3410 return true;
3411 }
3412
3413 r = amdgpu_bo_reserve(root, true);
3414 if (r)
3415 goto error_unref;
3416
3417
3418 spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
3419 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3420 if (vm && vm->root.bo != root)
3421 vm = NULL;
3422 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
3423 if (!vm)
3424 goto error_unlock;
3425
3426 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
3427 AMDGPU_PTE_SYSTEM;
3428
3429 if (is_compute_context) {
3430
3431
3432
3433 flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
3434 AMDGPU_PTE_TF;
3435 value = 0;
3436 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
3437
3438 value = adev->dummy_page_addr;
3439 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
3440 AMDGPU_PTE_WRITEABLE;
3441
3442 } else {
3443
3444 value = 0;
3445 }
3446
3447 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
3448 if (r) {
3449 pr_debug("failed %d to reserve fence slot\n", r);
3450 goto error_unlock;
3451 }
3452
3453 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
3454 addr, flags, value, NULL, NULL, NULL,
3455 NULL);
3456 if (r)
3457 goto error_unlock;
3458
3459 r = amdgpu_vm_update_pdes(adev, vm, true);
3460
3461error_unlock:
3462 amdgpu_bo_unreserve(root);
3463 if (r < 0)
3464 DRM_ERROR("Can't handle page fault (%d)\n", r);
3465
3466error_unref:
3467 amdgpu_bo_unref(&root);
3468
3469 return false;
3470}
3471
3472#if defined(CONFIG_DEBUG_FS)
3473
3474
3475
3476
3477
3478
3479
3480
3481void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
3482{
3483 struct amdgpu_bo_va *bo_va, *tmp;
3484 u64 total_idle = 0;
3485 u64 total_evicted = 0;
3486 u64 total_relocated = 0;
3487 u64 total_moved = 0;
3488 u64 total_invalidated = 0;
3489 u64 total_done = 0;
3490 unsigned int total_idle_objs = 0;
3491 unsigned int total_evicted_objs = 0;
3492 unsigned int total_relocated_objs = 0;
3493 unsigned int total_moved_objs = 0;
3494 unsigned int total_invalidated_objs = 0;
3495 unsigned int total_done_objs = 0;
3496 unsigned int id = 0;
3497
3498 seq_puts(m, "\tIdle BOs:\n");
3499 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
3500 if (!bo_va->base.bo)
3501 continue;
3502 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3503 }
3504 total_idle_objs = id;
3505 id = 0;
3506
3507 seq_puts(m, "\tEvicted BOs:\n");
3508 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
3509 if (!bo_va->base.bo)
3510 continue;
3511 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3512 }
3513 total_evicted_objs = id;
3514 id = 0;
3515
3516 seq_puts(m, "\tRelocated BOs:\n");
3517 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
3518 if (!bo_va->base.bo)
3519 continue;
3520 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3521 }
3522 total_relocated_objs = id;
3523 id = 0;
3524
3525 seq_puts(m, "\tMoved BOs:\n");
3526 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
3527 if (!bo_va->base.bo)
3528 continue;
3529 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3530 }
3531 total_moved_objs = id;
3532 id = 0;
3533
3534 seq_puts(m, "\tInvalidated BOs:\n");
3535 spin_lock(&vm->invalidated_lock);
3536 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
3537 if (!bo_va->base.bo)
3538 continue;
3539 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3540 }
3541 total_invalidated_objs = id;
3542 id = 0;
3543
3544 seq_puts(m, "\tDone BOs:\n");
3545 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
3546 if (!bo_va->base.bo)
3547 continue;
3548 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3549 }
3550 spin_unlock(&vm->invalidated_lock);
3551 total_done_objs = id;
3552
3553 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
3554 total_idle_objs);
3555 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
3556 total_evicted_objs);
3557 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
3558 total_relocated_objs);
3559 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
3560 total_moved_objs);
3561 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
3562 total_invalidated_objs);
3563 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
3564 total_done_objs);
3565}
3566#endif
3567