LXR linux/drivers/gpu/drm/amd/amdgpu/vcn_v2

   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#ifndef __VCN_V2_0_H__
  25#define __VCN_V2_0_H__
  26
  27extern void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
  28extern void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
  29extern void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
  30extern void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
  31                                unsigned flags);
  32extern void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
  33                                struct amdgpu_ib *ib, uint32_t flags);
  34extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
  35                                uint32_t val, uint32_t mask);
  36extern void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
  37                                unsigned vmid, uint64_t pd_addr);
  38extern void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
  39                                uint32_t reg, uint32_t val);
  40extern int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring);
  41
  42extern void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring);
  43extern void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
  44                                u64 seq, unsigned flags);
  45extern void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
  46                                struct amdgpu_ib *ib, uint32_t flags);
  47extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
  48                                uint32_t val, uint32_t mask);
  49extern void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
  50                                unsigned int vmid, uint64_t pd_addr);
  51extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
  52
  53extern const struct amdgpu_ip_block_version vcn_v2_0_ip_block;
  54
  55#endif /* __VCN_V2_0_H__ */
  56