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24#include <linux/printk.h>
25#include <linux/slab.h>
26#include <linux/mm_types.h>
27
28#include "kfd_priv.h"
29#include "kfd_mqd_manager.h"
30#include "vi_structs.h"
31#include "gca/gfx_8_0_sh_mask.h"
32#include "gca/gfx_8_0_enum.h"
33#include "oss/oss_3_0_sh_mask.h"
34
35#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
36
37static inline struct vi_mqd *get_mqd(void *mqd)
38{
39 return (struct vi_mqd *)mqd;
40}
41
42static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
43{
44 return (struct vi_sdma_mqd *)mqd;
45}
46
47static void update_cu_mask(struct mqd_manager *mm, void *mqd,
48 struct queue_properties *q)
49{
50 struct vi_mqd *m;
51 uint32_t se_mask[4] = {0};
52
53 if (q->cu_mask_count == 0)
54 return;
55
56 mqd_symmetrically_map_cu_mask(mm,
57 q->cu_mask, q->cu_mask_count, se_mask);
58
59 m = get_mqd(mqd);
60 m->compute_static_thread_mgmt_se0 = se_mask[0];
61 m->compute_static_thread_mgmt_se1 = se_mask[1];
62 m->compute_static_thread_mgmt_se2 = se_mask[2];
63 m->compute_static_thread_mgmt_se3 = se_mask[3];
64
65 pr_debug("Update cu mask to %#x %#x %#x %#x\n",
66 m->compute_static_thread_mgmt_se0,
67 m->compute_static_thread_mgmt_se1,
68 m->compute_static_thread_mgmt_se2,
69 m->compute_static_thread_mgmt_se3);
70}
71
72static void set_priority(struct vi_mqd *m, struct queue_properties *q)
73{
74 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
75 m->cp_hqd_queue_priority = q->priority;
76}
77
78static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
79 struct queue_properties *q)
80{
81 struct kfd_mem_obj *mqd_mem_obj;
82
83 if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd),
84 &mqd_mem_obj))
85 return NULL;
86
87 return mqd_mem_obj;
88}
89
90static void init_mqd(struct mqd_manager *mm, void **mqd,
91 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
92 struct queue_properties *q)
93{
94 uint64_t addr;
95 struct vi_mqd *m;
96
97 m = (struct vi_mqd *) mqd_mem_obj->cpu_ptr;
98 addr = mqd_mem_obj->gpu_addr;
99
100 memset(m, 0, sizeof(struct vi_mqd));
101
102 m->header = 0xC0310800;
103 m->compute_pipelinestat_enable = 1;
104 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
105 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
106 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
107 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
108
109 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
110 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
111
112 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT |
113 MTYPE_UC << CP_MQD_CONTROL__MTYPE__SHIFT;
114
115 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
116 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
117
118 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
119 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
120 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
121
122 set_priority(m, q);
123 m->cp_hqd_eop_rptr = 1 << CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT;
124
125 if (q->format == KFD_QUEUE_FORMAT_AQL)
126 m->cp_hqd_iq_rptr = 1;
127
128 if (q->tba_addr) {
129 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8);
130 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8);
131 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8);
132 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8);
133 m->compute_pgm_rsrc2 |=
134 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT);
135 }
136
137 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) {
138 m->cp_hqd_persistent_state |=
139 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
140 m->cp_hqd_ctx_save_base_addr_lo =
141 lower_32_bits(q->ctx_save_restore_area_address);
142 m->cp_hqd_ctx_save_base_addr_hi =
143 upper_32_bits(q->ctx_save_restore_area_address);
144 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
145 m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
146 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
147 m->cp_hqd_wg_state_offset = q->ctl_stack_size;
148 }
149
150 *mqd = m;
151 if (gart_addr)
152 *gart_addr = addr;
153 mm->update_mqd(mm, m, q);
154}
155
156static int load_mqd(struct mqd_manager *mm, void *mqd,
157 uint32_t pipe_id, uint32_t queue_id,
158 struct queue_properties *p, struct mm_struct *mms)
159{
160
161 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
162 uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
163
164 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
165 (uint32_t __user *)p->write_ptr,
166 wptr_shift, wptr_mask, mms);
167}
168
169static void __update_mqd(struct mqd_manager *mm, void *mqd,
170 struct queue_properties *q, unsigned int mtype,
171 unsigned int atc_bit)
172{
173 struct vi_mqd *m;
174
175 m = get_mqd(mqd);
176
177 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
178 atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
179 mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
180 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
181 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
182
183 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
184 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
185
186 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
187 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
188 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
189 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
190
191 m->cp_hqd_pq_doorbell_control =
192 q->doorbell_off <<
193 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
194 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
195 m->cp_hqd_pq_doorbell_control);
196
197 m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT |
198 mtype << CP_HQD_EOP_CONTROL__MTYPE__SHIFT;
199
200 m->cp_hqd_ib_control = atc_bit << CP_HQD_IB_CONTROL__IB_ATC__SHIFT |
201 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
202 mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT;
203
204
205
206
207
208
209
210
211 m->cp_hqd_eop_control |= min(0xA,
212 order_base_2(q->eop_ring_buffer_size / 4) - 1);
213 m->cp_hqd_eop_base_addr_lo =
214 lower_32_bits(q->eop_ring_buffer_address >> 8);
215 m->cp_hqd_eop_base_addr_hi =
216 upper_32_bits(q->eop_ring_buffer_address >> 8);
217
218 m->cp_hqd_iq_timer = atc_bit << CP_HQD_IQ_TIMER__IQ_ATC__SHIFT |
219 mtype << CP_HQD_IQ_TIMER__MTYPE__SHIFT;
220
221 m->cp_hqd_vmid = q->vmid;
222
223 if (q->format == KFD_QUEUE_FORMAT_AQL) {
224 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
225 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT;
226 }
227
228 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address)
229 m->cp_hqd_ctx_save_control =
230 atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT |
231 mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT;
232
233 update_cu_mask(mm, mqd, q);
234 set_priority(m, q);
235
236 q->is_active = QUEUE_IS_ACTIVE(*q);
237}
238
239
240static void update_mqd(struct mqd_manager *mm, void *mqd,
241 struct queue_properties *q)
242{
243 __update_mqd(mm, mqd, q, MTYPE_CC, 1);
244}
245
246static uint32_t read_doorbell_id(void *mqd)
247{
248 struct vi_mqd *m = (struct vi_mqd *)mqd;
249
250 return m->queue_doorbell_id0;
251}
252
253static void update_mqd_tonga(struct mqd_manager *mm, void *mqd,
254 struct queue_properties *q)
255{
256 __update_mqd(mm, mqd, q, MTYPE_UC, 0);
257}
258
259static int destroy_mqd(struct mqd_manager *mm, void *mqd,
260 enum kfd_preempt_type type,
261 unsigned int timeout, uint32_t pipe_id,
262 uint32_t queue_id)
263{
264 return mm->dev->kfd2kgd->hqd_destroy
265 (mm->dev->kgd, mqd, type, timeout,
266 pipe_id, queue_id);
267}
268
269static void free_mqd(struct mqd_manager *mm, void *mqd,
270 struct kfd_mem_obj *mqd_mem_obj)
271{
272 kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
273}
274
275static bool is_occupied(struct mqd_manager *mm, void *mqd,
276 uint64_t queue_address, uint32_t pipe_id,
277 uint32_t queue_id)
278{
279 return mm->dev->kfd2kgd->hqd_is_occupied(
280 mm->dev->kgd, queue_address,
281 pipe_id, queue_id);
282}
283
284static int get_wave_state(struct mqd_manager *mm, void *mqd,
285 void __user *ctl_stack,
286 u32 *ctl_stack_used_size,
287 u32 *save_area_used_size)
288{
289 struct vi_mqd *m;
290
291 m = get_mqd(mqd);
292
293 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
294 m->cp_hqd_cntl_stack_offset;
295 *save_area_used_size = m->cp_hqd_wg_state_offset -
296 m->cp_hqd_cntl_stack_size;
297
298
299
300
301
302
303 return 0;
304}
305
306static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
307 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
308 struct queue_properties *q)
309{
310 struct vi_mqd *m;
311 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
312
313 m = get_mqd(*mqd);
314
315 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
316 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
317}
318
319static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
320 struct queue_properties *q)
321{
322 __update_mqd(mm, mqd, q, MTYPE_UC, 0);
323}
324
325static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
326 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
327 struct queue_properties *q)
328{
329 struct vi_sdma_mqd *m;
330
331 m = (struct vi_sdma_mqd *) mqd_mem_obj->cpu_ptr;
332
333 memset(m, 0, sizeof(struct vi_sdma_mqd));
334
335 *mqd = m;
336 if (gart_addr)
337 *gart_addr = mqd_mem_obj->gpu_addr;
338
339 mm->update_mqd(mm, m, q);
340}
341
342static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
343 uint32_t pipe_id, uint32_t queue_id,
344 struct queue_properties *p, struct mm_struct *mms)
345{
346 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
347 (uint32_t __user *)p->write_ptr,
348 mms);
349}
350
351static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
352 struct queue_properties *q)
353{
354 struct vi_sdma_mqd *m;
355
356 m = get_sdma_mqd(mqd);
357 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
358 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
359 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
360 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
361 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
362
363 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
364 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
365 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
366 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
367 m->sdmax_rlcx_doorbell =
368 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
369
370 m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr;
371
372 m->sdma_engine_id = q->sdma_engine_id;
373 m->sdma_queue_id = q->sdma_queue_id;
374
375 q->is_active = QUEUE_IS_ACTIVE(*q);
376}
377
378
379
380
381
382static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
383 enum kfd_preempt_type type,
384 unsigned int timeout, uint32_t pipe_id,
385 uint32_t queue_id)
386{
387 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
388}
389
390static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
391 uint64_t queue_address, uint32_t pipe_id,
392 uint32_t queue_id)
393{
394 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
395}
396
397#if defined(CONFIG_DEBUG_FS)
398
399static int debugfs_show_mqd(struct seq_file *m, void *data)
400{
401 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
402 data, sizeof(struct vi_mqd), false);
403 return 0;
404}
405
406static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
407{
408 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
409 data, sizeof(struct vi_sdma_mqd), false);
410 return 0;
411}
412
413#endif
414
415struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
416 struct kfd_dev *dev)
417{
418 struct mqd_manager *mqd;
419
420 if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
421 return NULL;
422
423 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
424 if (!mqd)
425 return NULL;
426
427 mqd->dev = dev;
428
429 switch (type) {
430 case KFD_MQD_TYPE_CP:
431 mqd->allocate_mqd = allocate_mqd;
432 mqd->init_mqd = init_mqd;
433 mqd->free_mqd = free_mqd;
434 mqd->load_mqd = load_mqd;
435 mqd->update_mqd = update_mqd;
436 mqd->destroy_mqd = destroy_mqd;
437 mqd->is_occupied = is_occupied;
438 mqd->get_wave_state = get_wave_state;
439 mqd->mqd_size = sizeof(struct vi_mqd);
440#if defined(CONFIG_DEBUG_FS)
441 mqd->debugfs_show_mqd = debugfs_show_mqd;
442#endif
443 break;
444 case KFD_MQD_TYPE_HIQ:
445 mqd->allocate_mqd = allocate_hiq_mqd;
446 mqd->init_mqd = init_mqd_hiq;
447 mqd->free_mqd = free_mqd_hiq_sdma;
448 mqd->load_mqd = load_mqd;
449 mqd->update_mqd = update_mqd_hiq;
450 mqd->destroy_mqd = destroy_mqd;
451 mqd->is_occupied = is_occupied;
452 mqd->mqd_size = sizeof(struct vi_mqd);
453#if defined(CONFIG_DEBUG_FS)
454 mqd->debugfs_show_mqd = debugfs_show_mqd;
455#endif
456 mqd->read_doorbell_id = read_doorbell_id;
457 break;
458 case KFD_MQD_TYPE_DIQ:
459 mqd->allocate_mqd = allocate_mqd;
460 mqd->init_mqd = init_mqd_hiq;
461 mqd->free_mqd = free_mqd;
462 mqd->load_mqd = load_mqd;
463 mqd->update_mqd = update_mqd_hiq;
464 mqd->destroy_mqd = destroy_mqd;
465 mqd->is_occupied = is_occupied;
466 mqd->mqd_size = sizeof(struct vi_mqd);
467#if defined(CONFIG_DEBUG_FS)
468 mqd->debugfs_show_mqd = debugfs_show_mqd;
469#endif
470 break;
471 case KFD_MQD_TYPE_SDMA:
472 mqd->allocate_mqd = allocate_sdma_mqd;
473 mqd->init_mqd = init_mqd_sdma;
474 mqd->free_mqd = free_mqd_hiq_sdma;
475 mqd->load_mqd = load_mqd_sdma;
476 mqd->update_mqd = update_mqd_sdma;
477 mqd->destroy_mqd = destroy_mqd_sdma;
478 mqd->is_occupied = is_occupied_sdma;
479 mqd->mqd_size = sizeof(struct vi_sdma_mqd);
480#if defined(CONFIG_DEBUG_FS)
481 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
482#endif
483 break;
484 default:
485 kfree(mqd);
486 return NULL;
487 }
488
489 return mqd;
490}
491
492struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
493 struct kfd_dev *dev)
494{
495 struct mqd_manager *mqd;
496
497 mqd = mqd_manager_init_vi(type, dev);
498 if (!mqd)
499 return NULL;
500 if (type == KFD_MQD_TYPE_CP)
501 mqd->update_mqd = update_mqd_tonga;
502 return mqd;
503}
504
