LXR linux/drivers/gpu/drm/amd/display/dc/dcn20/dcn20

   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DCN20_DCCG_H__
  27#define __DCN20_DCCG_H__
  28
  29#include "dccg.h"
  30
  31#define DCCG_COMMON_REG_LIST_DCN_BASE() \
  32        SR(DPPCLK_DTO_CTRL),\
  33        DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
  34        DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
  35        DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
  36        DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
  37        SR(REFCLK_CNTL),\
  38        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
  39        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
  40        SR(DISPCLK_FREQ_CHANGE_CNTL)
  41
  42#define DCCG_REG_LIST_DCN2() \
  43        DCCG_COMMON_REG_LIST_DCN_BASE(),\
  44        DCCG_SRII(DTO_PARAM, DPPCLK, 4),\
  45        DCCG_SRII(DTO_PARAM, DPPCLK, 5),\
  46        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
  47        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
  48        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
  49        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
  50
  51#define DCCG_SF(reg_name, field_name, post_fix)\
  52        .field_name = reg_name ## __ ## field_name ## post_fix
  53
  54#define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\
  55        .field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
  56
  57#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
  58        .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
  59
  60#define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
  61        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
  62        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
  63        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
  64        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
  65        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
  66        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
  67        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
  68        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
  69        DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
  70        DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
  71        DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
  72        DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
  73        DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
  74        DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
  75        DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
  76        DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
  77        DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
  78        DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
  79        DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
  80        DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
  81        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
  82        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
  83        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
  84        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
  85
  86
  87
  88
  89#define DCCG_MASK_SH_LIST_DCN2(mask_sh) \
  90        DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
  91        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
  92        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
  93        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
  94        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
  95        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
  96        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
  97        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\
  98        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\
  99        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
 100        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
 101        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\
 102        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)
 103
 104#define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \
 105        DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
 106        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
 107        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
 108        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
 109        DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
 110        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
 111        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
 112        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
 113        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh)
 114
 115
 116#define DCCG_REG_FIELD_LIST(type) \
 117        type DPPCLK0_DTO_PHASE;\
 118        type DPPCLK0_DTO_MODULO;\
 119        type DPPCLK_DTO_ENABLE[6];\
 120        type DPPCLK_DTO_DB_EN[6];\
 121        type REFCLK_CLOCK_EN;\
 122        type REFCLK_SRC_SEL;\
 123        type DISPCLK_STEP_DELAY;\
 124        type DISPCLK_STEP_SIZE;\
 125        type DISPCLK_FREQ_RAMP_DONE;\
 126        type DISPCLK_MAX_ERRDET_CYCLES;\
 127        type DCCG_FIFO_ERRDET_RESET;\
 128        type DCCG_FIFO_ERRDET_STATE;\
 129        type DCCG_FIFO_ERRDET_OVR_EN;\
 130        type DISPCLK_CHG_FWD_CORR_DISABLE;\
 131        type DISPCLK_FREQ_CHANGE_CNTL;\
 132        type OTG_ADD_PIXEL[MAX_PIPES];\
 133        type OTG_DROP_PIXEL[MAX_PIPES];
 134
 135#define DCCG3_REG_FIELD_LIST(type) \
 136        type PHYASYMCLK_FORCE_EN;\
 137        type PHYASYMCLK_FORCE_SRC_SEL;\
 138        type PHYBSYMCLK_FORCE_EN;\
 139        type PHYBSYMCLK_FORCE_SRC_SEL;\
 140        type PHYCSYMCLK_FORCE_EN;\
 141        type PHYCSYMCLK_FORCE_SRC_SEL;
 142
 143#define DCCG31_REG_FIELD_LIST(type) \
 144        type PHYDSYMCLK_FORCE_EN;\
 145        type PHYDSYMCLK_FORCE_SRC_SEL;\
 146        type PHYESYMCLK_FORCE_EN;\
 147        type PHYESYMCLK_FORCE_SRC_SEL;\
 148        type DPSTREAMCLK_PIPE0_EN;\
 149        type DPSTREAMCLK_PIPE1_EN;\
 150        type DPSTREAMCLK_PIPE2_EN;\
 151        type DPSTREAMCLK_PIPE3_EN;\
 152        type HDMISTREAMCLK0_SRC_SEL;\
 153        type HDMISTREAMCLK0_DTO_FORCE_DIS;\
 154        type SYMCLK32_SE0_SRC_SEL;\
 155        type SYMCLK32_SE1_SRC_SEL;\
 156        type SYMCLK32_SE2_SRC_SEL;\
 157        type SYMCLK32_SE3_SRC_SEL;\
 158        type SYMCLK32_SE0_EN;\
 159        type SYMCLK32_SE1_EN;\
 160        type SYMCLK32_SE2_EN;\
 161        type SYMCLK32_SE3_EN;\
 162        type SYMCLK32_LE0_SRC_SEL;\
 163        type SYMCLK32_LE1_SRC_SEL;\
 164        type SYMCLK32_LE0_EN;\
 165        type SYMCLK32_LE1_EN;\
 166        type DTBCLK_DTO_ENABLE[MAX_PIPES];\
 167        type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
 168        type PIPE_DTO_SRC_SEL[MAX_PIPES];\
 169        type DTBCLK_DTO_DIV[MAX_PIPES];\
 170        type DCCG_AUDIO_DTO_SEL;\
 171        type DCCG_AUDIO_DTO0_SOURCE_SEL;\
 172        type DENTIST_DISPCLK_CHG_MODE;
 173
 174struct dccg_shift {
 175        DCCG_REG_FIELD_LIST(uint8_t)
 176        DCCG3_REG_FIELD_LIST(uint8_t)
 177        DCCG31_REG_FIELD_LIST(uint8_t)
 178};
 179
 180struct dccg_mask {
 181        DCCG_REG_FIELD_LIST(uint32_t)
 182        DCCG3_REG_FIELD_LIST(uint32_t)
 183        DCCG31_REG_FIELD_LIST(uint32_t)
 184};
 185
 186struct dccg_registers {
 187        uint32_t DPPCLK_DTO_CTRL;
 188        uint32_t DPPCLK_DTO_PARAM[6];
 189        uint32_t REFCLK_CNTL;
 190        uint32_t DISPCLK_FREQ_CHANGE_CNTL;
 191        uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
 192        uint32_t HDMICHARCLK_CLOCK_CNTL[6];
 193        uint32_t PHYASYMCLK_CLOCK_CNTL;
 194        uint32_t PHYBSYMCLK_CLOCK_CNTL;
 195        uint32_t PHYCSYMCLK_CLOCK_CNTL;
 196        uint32_t PHYDSYMCLK_CLOCK_CNTL;
 197        uint32_t PHYESYMCLK_CLOCK_CNTL;
 198        uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
 199        uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
 200        uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
 201        uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE;
 202        uint32_t DCCG_AUDIO_DTO_SOURCE;
 203        uint32_t DPSTREAMCLK_CNTL;
 204        uint32_t HDMISTREAMCLK_CNTL;
 205        uint32_t SYMCLK32_SE_CNTL;
 206        uint32_t SYMCLK32_LE_CNTL;
 207        uint32_t DENTIST_DISPCLK_CNTL;
 208};
 209
 210struct dcn_dccg {
 211        struct dccg base;
 212        const struct dccg_registers *regs;
 213        const struct dccg_shift *dccg_shift;
 214        const struct dccg_mask *dccg_mask;
 215};
 216
 217void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
 218
 219void dccg2_get_dccg_ref_freq(struct dccg *dccg,
 220                unsigned int xtalin_freq_inKhz,
 221                unsigned int *dccg_ref_freq_inKhz);
 222
 223void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
 224                bool en);
 225void dccg2_otg_add_pixel(struct dccg *dccg,
 226                uint32_t otg_inst);
 227void dccg2_otg_drop_pixel(struct dccg *dccg,
 228                uint32_t otg_inst);
 229
 230
 231void dccg2_init(struct dccg *dccg);
 232
 233struct dccg *dccg2_create(
 234        struct dc_context *ctx,
 235        const struct dccg_registers *regs,
 236        const struct dccg_shift *dccg_shift,
 237        const struct dccg_mask *dccg_mask);
 238
 239void dcn_dccg_destroy(struct dccg **dccg);
 240
 241#endif //__DCN20_DCCG_H__
 242